\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
SPI Configuration Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCK_HIGH : SCK High Count
bits : 0 - 7 (8 bit)
access : read-write
SCK_LOW : SCK Low Count
bits : 8 - 15 (8 bit)
access : read-write
CS_HOLD : CS hold Count
bits : 16 - 23 (8 bit)
access : read-write
CS_SETUP : CS Setup Count
bits : 24 - 31 (8 bit)
access : read-write
SPI Data Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 15 (16 bit)
access : read-write
SPI configuration register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MNDC : Master No Overflow mode enable bit
bits : 1 - 1 (1 bit)
access : read-write
TOEN : TX only mode enable bit
bits : 2 - 2 (1 bit)
access : read-write
ROEN : RX only mode enable bit
bits : 3 - 3 (1 bit)
access : read-write
SPI Configuration Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS_IDLE : CS idle count
bits : 0 - 7 (8 bit)
access : read-write
TXEIE : TX buffer empty interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
RXFIE : no description available
bits : 9 - 9 (1 bit)
access : read-write
TXUIE : TX buffer underflow interrupt enable
bits : 10 - 10 (1 bit)
access : read-write
RXOIE : RX buffer overflow interrupt enable
bits : 11 - 11 (1 bit)
access : read-write
MSTR : master/slave mode selection
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
slave mode
#1 : 1
master mode
End of enumeration elements list.
MODFIE : mode fault interrupt enable
bits : 13 - 13 (1 bit)
access : read-write
DMATXEN : DMA TX channel enable
bits : 14 - 14 (1 bit)
access : read-write
DMARXEN : DMA RX channel enable
bits : 15 - 15 (1 bit)
access : read-write
CPOL : clock polarity
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
SCK is 0 when idle
#1 : 1
SCK is 1 when idle
End of enumeration elements list.
CPHA : clock phase
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
the second SCK transition is the first data capture edge
#1 : 1
the first SCK transition is the first data capture edge
End of enumeration elements list.
MSBF : TX MSB first Select
bits : 18 - 18 (1 bit)
access : read-write
RMSBF : RX MSB first Select
bits : 19 - 19 (1 bit)
access : read-write
FRMSIZE : frame size
bits : 20 - 23 (4 bit)
access : read-write
CSOE : CS hardware output enable
bits : 25 - 25 (1 bit)
access : read-write
MODFEN : mode fault detect enable
bits : 26 - 26 (1 bit)
access : read-write
CONT_CS : CS continuous output enable
bits : 28 - 28 (1 bit)
access : read-write
WKUEN : wake up function enable(only valid for slave mode)
bits : 30 - 30 (1 bit)
access : read-write
SPI Command Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIEN : SPI Enable
bits : 0 - 0 (1 bit)
access : read-write
SWRST : software reset
bits : 4 - 4 (1 bit)
access : read-write
CSRLS : CS release(only valid for CS continuous output)
bits : 5 - 5 (1 bit)
access : read-write
ROTRIG : Master RX only mode trigger
bits : 6 - 6 (1 bit)
access : read-write
SPI Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEF : TX buffer empty flag
bits : 0 - 0 (1 bit)
access : read-write
RXFF : RX buffer Full flag
bits : 1 - 1 (1 bit)
access : read-write
TXUF : TX buffer underflow flag
bits : 2 - 2 (1 bit)
access : read-write
RXOF : RX buffer overflow flag
bits : 3 - 3 (1 bit)
access : read-write
MODEF : Mode error flag
bits : 4 - 4 (1 bit)
access : read-write
MEBY : SPI master engine busy flag
bits : 7 - 7 (1 bit)
access : read-write
IDLEF : SPI IDLE flag
bits : 8 - 8 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.