\n
address_offset : 0x0 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection : not protected
I2C Address Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AD : Address
bits : 1 - 7 (7 bit)
access : read-write
I2C Control Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUEN : wakeup enable
bits : 2 - 2 (1 bit)
access : read-write
TACK : Transmit Acknowledge Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACK will sent to the bus on the following receiving byte
#1 : 1
NACK will sent to the bus on the following receiving byte
End of enumeration elements list.
TX : Transmit Mode Select(valid for master)
bits : 4 - 4 (1 bit)
access : read-write
MSTR : I2C operation mode Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave Mode
#1 : 1
Master Mode
End of enumeration elements list.
IICIE : I2C interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
IICEN : I2C Module Enable
bits : 7 - 7 (1 bit)
access : read-write
I2C Control Register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STREN : SCL Strech enable(Valid for slave)
bits : 0 - 0 (1 bit)
access : read-write
ARBEN : Arbitration Enable
bits : 3 - 3 (1 bit)
access : read-write
SYNCEN : SCL Sync Enable
bits : 4 - 4 (1 bit)
access : read-write
ADEXT : Address Extension(valid for Slave)
bits : 6 - 6 (1 bit)
access : read-write
GCAEN : General Call enable(valid for Slave)
bits : 7 - 7 (1 bit)
access : read-write
I2C Control Register 3
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MNTEN : Monitor Function Enable
bits : 0 - 0 (1 bit)
access : read-write
NACKIE : NACK get interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
TXEMIE : TX buffer empty interrupt enable
bits : 4 - 4 (1 bit)
access : read-write
RXFIE : RX buffer full interrupt enable
bits : 5 - 5 (1 bit)
access : read-write
TXUFIE : TX buffer underflow error interrupt enable
bits : 6 - 6 (1 bit)
access : read-write
RXOFIE : RX buffer overflow interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
I2C Control Register 4
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMATXEN : DMATX enable
bits : 0 - 0 (1 bit)
access : read-write
DMARXEN : DMARX enable
bits : 1 - 1 (1 bit)
access : read-write
I2C Status Register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RACK : Acknowledge received(master or Slave TX mode)
bits : 0 - 0 (1 bit)
access : read-Only
SRW : Slave read/write
bits : 2 - 2 (1 bit)
access : read-only
READY : internal hardware core is ready for new command or not
bits : 3 - 3 (1 bit)
access : read-only
ARBLOST : Arbitration lost flag
bits : 4 - 4 (1 bit)
access : read-write
BUSY : indicates the status of the bus regardless of slave or master mode
bits : 5 - 5 (1 bit)
access : read-only
SAMF : Address match
bits : 6 - 6 (1 bit)
access : read-write
BND : Byte end flag
bits : 7 - 7 (1 bit)
access : read-only
I2C Status Register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEF : TX buffer empty flag(only valid for slave)
bits : 0 - 0 (1 bit)
access : read-write
RXFF : RX buffer Full flag(only valid for slave)
bits : 1 - 1 (1 bit)
access : read-write
TXUF : TX buffer underflow flag(only valid for slave)
bits : 2 - 2 (1 bit)
access : read-only
RXOF : RX buffer overflow flag(only valid for slave)
bits : 3 - 3 (1 bit)
access : read-only
IDLE : I2C Core Hardware state
bits : 7 - 7 (1 bit)
access : read-only
I2C Deglitch Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DGL_CNT : Deglitch Counter
bits : 0 - 3 (4 bit)
access : read-write
STARTF : I2C Bus Start Detect Flag
bits : 4 - 4 (1 bit)
access : read-write
SSIE : I2C Bus STOP or START interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
STOPF : I2C Bus Stop detect Flag
bits : 6 - 6 (1 bit)
access : read-write
DGLEN : I2C Deglitch filter Enable
bits : 7 - 7 (1 bit)
access : read-write
I2C Data Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 7 (8 bit)
access : read-write
MAK : Slave Monitor Function ACK bit
bits : 8 - 8 (1 bit)
access : read-only
I2C START_STOP Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : I2C Start(valid for master)
bits : 0 - 0 (1 bit)
access : read-write
STOP : I2C Stop(valid for master)
bits : 1 - 1 (1 bit)
access : read-write
I2C ADDR register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AD : Address
bits : 0 - 2 (3 bit)
access : read-write
I2C SAMPLE CNT Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAMPLE_CNT_DIV : Adjust the width of each sample
bits : 0 - 7 (8 bit)
access : read-write
I2C STEP CNT Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STEP_CNT_DIV : Specifies the number of Samples per half pulse width
bits : 0 - 7 (8 bit)
access : read-write
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