Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
Watchdog Control and Status Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOP : Stop Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog disabled in chip stop mode.
#1 : 1
Watchdog enabled in chip stop mode.
End of enumeration elements list.
WAIT : Wait Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog disabled in chip wait mode.
#1 : 1
Watchdog enabled in chip wait mode.
End of enumeration elements list.
DBG : Debug Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog disabled in chip debug mode.
#1 : 1
Watchdog enabled in chip debug mode.
End of enumeration elements list.
TST : Watchdog Test
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 00
Watchdog test mode disabled.
#01 : 01
Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode.
#10 : 10
Watchdog test mode enabled, only the low byte is used. WDOG_CNTL is compared with WDOG_TOVALL.
#11 : 11
Watchdog test mode enabled, only the high byte is used. WDOG_CNTH is compared with WDOG_TOVALH.
End of enumeration elements list.
UPDATE : Allow updates
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
#1 : 1
Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
End of enumeration elements list.
INT : Watchdog Interrupt
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog interrupts are disabled. Watchdog resets are not delayed.
#1 : 1
Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks.
End of enumeration elements list.
EN : Watchdog Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog disabled.
#1 : 1
Watchdog enabled.
End of enumeration elements list.
Watchdog Window Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIN : Watchdog Window
bits : 0 - 31 (32 bit)
access : read-write
Watchdog Control and Status Register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK : Watchdog Clock
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus clock.
#01 : 01
1 kHz internal low-power oscillator (LPOCLK).
#10 : 10
32 kHz internal oscillator (ICSIRCLK).
#11 : 11
External clock source.
End of enumeration elements list.
PRES : Watchdog Prescalar
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
256 prescalar disabled.
#1 : 1
256 prescalar enabled.
End of enumeration elements list.
FLG : Watchdog Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt occurred.
#1 : 1
An interrupt occurred.
End of enumeration elements list.
WIN : Watchdog Window
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Window mode disabled.
#1 : 1
Window mode enabled.
End of enumeration elements list.
Watchdog Counter Value
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Watchdog Counter Value
bits : 0 - 31 (32 bit)
access : read-write
Watchdog Timeout Value Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOVAL : WatchDog Timeout Value
bits : 0 - 31 (32 bit)
access : read-write
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