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PWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xA0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

INIT

CH0SCR

CH0V

CH1SCR

CH1V

CNT

CH2SCR

CNTIN

STR

FUNCSEL

CH2V

SYNC

OUTINIT

OMCR

MODESEL

DTSET

CH3SCR

EXTTRIG

CHOPOLCR

FDSR

CAPFILTER

FFAFER

MCVR

CH3V

QEI

CONF

FLTPOL

SYNCONF

INVCR

CHOSWCR

CH4SCR

CH4V

CH5SCR

CH5V


INIT

PWM Initialize, Include Clock and Prescale Setting
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INIT INIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSRC CNTMODE CNTOIE CNTOF CLKPSC

CLKSRC : Clock Source Selection
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

#00 : 00

No clock selected. This in effect disables the PWM counter.

#01 : 01

System clock

#10 : 10

Fixed frequency clock

#11 : 11

External clock

End of enumeration elements list.

CNTMODE : PWM Counter Mode Select
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM counter operates in Up Counting mode.

#1 : 1

PWM counter operates in Up-Down Counting mode.

End of enumeration elements list.

CNTOIE : PWM Counter Overflow Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable CNTOF interrupts. Use software polling.

#1 : 1

Enable CNTOF interrupts. An interrupt is generated when CNTOF equals one.

End of enumeration elements list.

CNTOF : PWM Counter Overflow Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM counter has not overflowed.

#1 : 1

PWM counter has overflowed.

End of enumeration elements list.

CLKPSC : Prescale Factor Selection
bits : 8 - 23 (16 bit)
access : read-write


CH0SCR

Channel (n) Status And Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0SCR CH0SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ELSR0 ELSR1 MSR0 MSR1 CHIE CHIF

ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write

ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write

MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write

MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write

CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable channel interrupts. Use software polling.

#1 : 1

Enable channel interrupts.

End of enumeration elements list.

CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.


CH0V

Channel (n) Value
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0V CH0V read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHCVAL

CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write


CH1SCR

Channel (n) Status And Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1SCR CH1SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ELSR0 ELSR1 MSR0 MSR1 CHIE CHIF

ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write

ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write

MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write

MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write

CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable channel interrupts. Use software polling.

#1 : 1

Enable channel interrupts.

End of enumeration elements list.

CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.


CH1V

Channel (n) Value
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1V CH1V read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHCVAL

CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write


CNT

PWM Counter Current Count Value
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Current Counter Value
bits : 0 - 15 (16 bit)
access : read-write


CH2SCR

Channel (n) Status And Control Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2SCR CH2SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ELSR0 ELSR1 MSR0 MSR1 CHIE CHIF

ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write

ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write

MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write

MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write

CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable channel interrupts. Use software polling.

#1 : 1

Enable channel interrupts.

End of enumeration elements list.

CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.


CNTIN

Counter Initial Value
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTIN CNTIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTINIT

CNTINIT : no description available
bits : 0 - 15 (16 bit)
access : read-write


STR

Status Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STR STR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0SF CH1SF CH2SF CH3SF CH4SF CH5SF

CH0SF : Channel 0 Status Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.

CH1SF : Channel 1 Status Flag
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.

CH2SF : Channel 2 Status Flag
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.

CH3SF : Channel 3 Status Flag
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.

CH4SF : Channel 4 Status Flag
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.

CH5SF : Channel 5 Status Flag
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.


FUNCSEL

PWM Features(Functions) Mode Selection Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FUNCSEL FUNCSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMEN2 INIT WPDIS PWMSYNC CAPTEST FAULTMODE FAULTIE

PWMEN2 : PWM Enhance function Enable
bits : 0 - 0 (1 bit)
access : read-write

INIT : Initialize The Channels Output
bits : 1 - 1 (1 bit)
access : read-write

WPDIS : Write Protection Enable Register
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Write protection is enabled.

#1 : 1

Write protection is disabled.

End of enumeration elements list.

PWMSYNC : PWM Synchronization Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and PWM counter synchronization.

#1 : 1

Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and PWM counter synchronization.

End of enumeration elements list.

CAPTEST : Capture Test Mode Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Capture test mode is disabled.

#1 : 1

Capture test mode is enabled.

End of enumeration elements list.

FAULTMODE : Fault Control Mode
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#00 : 00

Fault control is disabled for all channels.

#01 : 01

Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.

#10 : 10

Fault control is enabled for all channels, and the selected mode is the manual fault clearing.

#11 : 11

Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.

End of enumeration elements list.

FAULTIE : Fault Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fault control interrupt is disabled.

#1 : 1

Fault control interrupt is enabled.

End of enumeration elements list.


CH2V

Channel (n) Value
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2V CH2V read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHCVAL

CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write


SYNC

Synchronization
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNC SYNC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINSYNCP MAXSYNCP REINIT OMSYNCP ACMPTRIG PWM0TRIG SWTRIG SWSYNC

MINSYNCP : Minimum Loading Point Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The minimum loading point is disabled.

#1 : 1

The minimum loading point is enabled.

End of enumeration elements list.

MAXSYNCP : Maximum Loading Point Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The maximum loading point is disabled.

#1 : 1

The maximum loading point is enabled.

End of enumeration elements list.

REINIT : PWM Counter Reinitialization By Synchronization (PWM counter synchronization)
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM counter continues to count normally.

#1 : 1

PWM counter is updated with its initial value when the selected trigger is detected.

End of enumeration elements list.

OMSYNCP : Output Mask Synchronization Point
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.

#1 : 1

OUTMASK register is updated with the value of its buffer only by the PWM synchronization.

End of enumeration elements list.

ACMPTRIG : PWM Synchronization Hardware Trigger 0
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Trigger is disabled.

#1 : 1

Trigger is enabled.

End of enumeration elements list.

PWM0TRIG : PWM Synchronization Hardware Trigger 1
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Trigger is disabled.

#1 : 1

Trigger is enabled.

End of enumeration elements list.

SWTRIG : PWM Synchronization Hardware Trigger 2
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Trigger is disabled.

#1 : 1

Trigger is enabled.

End of enumeration elements list.

SWSYNC : PWM Synchronization Software Trigger
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Software trigger is not selected.

#1 : 1

Software trigger is selected.

End of enumeration elements list.


OUTINIT

Initial Value For Channels Output
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTINIT OUTINIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0OIV CH1OIV CH2OIV CH3OIV CH4OIV CH5OIV

CH0OIV : Channel 0 Output Initialization Value
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The initialization value is 0.

#1 : 1

The initialization value is 1.

End of enumeration elements list.

CH1OIV : Channel 1 Output Initialization Value
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The initialization value is 0.

#1 : 1

The initialization value is 1.

End of enumeration elements list.

CH2OIV : Channel 2 Output Initialization Value
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The initialization value is 0.

#1 : 1

The initialization value is 1.

End of enumeration elements list.

CH3OIV : Channel 3 Output Initialization Value
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The initialization value is 0.

#1 : 1

The initialization value is 1.

End of enumeration elements list.

CH4OIV : Channel 4 Output Initialization Value
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The initialization value is 0.

#1 : 1

The initialization value is 1.

End of enumeration elements list.

CH5OIV : Channel 5 Output Initialization Value
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The initialization value is 0.

#1 : 1

The initialization value is 1.

End of enumeration elements list.


OMCR

Output Mask Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OMCR OMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0OMEN CH1OMEN CH2OMEN CH3OMEN CH4OMEN CH5OMEN

CH0OMEN : Channel 0 Output Mask
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel output is not masked. It continues to operate normally.

#1 : 1

Channel output is masked. It is forced to its inactive state.

End of enumeration elements list.

CH1OMEN : Channel 1 Output Mask
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel output is not masked. It continues to operate normally.

#1 : 1

Channel output is masked. It is forced to its inactive state.

End of enumeration elements list.

CH2OMEN : Channel 2 Output Mask
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel output is not masked. It continues to operate normally.

#1 : 1

Channel output is masked. It is forced to its inactive state.

End of enumeration elements list.

CH3OMEN : Channel 3 Output Mask
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel output is not masked. It continues to operate normally.

#1 : 1

Channel output is masked. It is forced to its inactive state.

End of enumeration elements list.

CH4OMEN : Channel 4 Output Mask
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel output is not masked. It continues to operate normally.

#1 : 1

Channel output is masked. It is forced to its inactive state.

End of enumeration elements list.

CH5OMEN : Channel 5 Output Mask
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel output is not masked. It continues to operate normally.

#1 : 1

Channel output is masked. It is forced to its inactive state.

End of enumeration elements list.


MODESEL

PWM Function Mode Selection
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODESEL MODESEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAIR0COMBINEN PAIR0COMPEN PAIR0DECAPEN PAIR0DECAP PAIR0DTEN PAIR0SYNCEN PAIR0FAULTEN PAIR1COMBINEN PAIR1COMPEN PAIR1DECAPEN PAIR1DECAP PAIR1DTEN PAIR1SYNCEN PAIR1FAULTEN PAIR2COMBINEN PAIR2COMPEN PAIR2DECAPEN PAIR2DECAP PAIR2DTEN PAIR2SYNCEN PAIR2FAULTEN

PAIR0COMBINEN : Combine Channels For Pair0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channels 0 and 1 are independent.

#1 : 1

Channels 0 and 1 are combined.

End of enumeration elements list.

PAIR0COMPEN : Complement Channels for Pair0
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel 1 output is the same as the channel 0 output.

#1 : 1

The channel 1 output is the complement of the channel 0 output.

End of enumeration elements list.

PAIR0DECAPEN : Dual Edge Capture Mode Enable for Pair0
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The Dual Edge Capture mode in this pair of channels is disabled.

#1 : 1

The Dual Edge Capture mode in this pair of channels is enabled.

End of enumeration elements list.

PAIR0DECAP : Dual Edge Capture Mode Captures for Pair0
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The dual edge captures are inactive.

#1 : 1

The dual edge captures are active.

End of enumeration elements list.

PAIR0DTEN : Deadtime Enable for Pair0
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The deadtime insertion in this pair of channels is disabled.

#1 : 1

The deadtime insertion in this pair of channels is enabled.

End of enumeration elements list.

PAIR0SYNCEN : Synchronization Enable for Pair0
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The PWM synchronization in this pair of channels is disabled.

#1 : 1

The PWM synchronization in this pair of channels is enabled.

End of enumeration elements list.

PAIR0FAULTEN : Fault Control Enable for Pair0
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

The fault control in this pair of channels is disabled.

#1 : 1

The fault control in this pair of channels is enabled.

End of enumeration elements list.

PAIR1COMBINEN : Combine Channels For Pair1
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channels 2 and 3 are independent.

#1 : 1

Channels 2 and 3 are combined.

End of enumeration elements list.

PAIR1COMPEN : Complement Of Channel (n) For Pair1
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel 3 output is the same as the channel 2 output.

#1 : 1

The channel 3 output is the complement of the channel 2 output.

End of enumeration elements list.

PAIR1DECAPEN : Dual Edge Capture Mode Enable For Pair1
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The Dual Edge Capture mode in this pair of channels is disabled.

#1 : 1

The Dual Edge Capture mode in this pair of channels is enabled.

End of enumeration elements list.

PAIR1DECAP : Dual Edge Capture Mode Captures For Pair1
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The dual edge captures are inactive.

#1 : 1

The dual edge captures are active.

End of enumeration elements list.

PAIR1DTEN : Deadtime Enable For Pair1
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The deadtime insertion in this pair of channels is disabled.

#1 : 1

The deadtime insertion in this pair of channels is enabled.

End of enumeration elements list.

PAIR1SYNCEN : Synchronization Enable For Pair1
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

The PWM synchronization in this pair of channels is disabled.

#1 : 1

The PWM synchronization in this pair of channels is enabled.

End of enumeration elements list.

PAIR1FAULTEN : Fault Control Enable For Pair1
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

The fault control in this pair of channels is disabled.

#1 : 1

The fault control in this pair of channels is enabled.

End of enumeration elements list.

PAIR2COMBINEN : Combine Channels For Pair2
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channels 4 and 5 are independent.

#1 : 1

Channels 4 and 5 are combined.

End of enumeration elements list.

PAIR2COMPEN : Complement Of Channel (n) For Pair2
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel 5 output is the same as the channel 4 output.

#1 : 1

The channel 5 output is the complement of the channel 4 output.

End of enumeration elements list.

PAIR2DECAPEN : Dual Edge Capture Mode Enable For Pair2
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

The Dual Edge Capture mode in this pair of channels is disabled.

#1 : 1

The Dual Edge Capture mode in this pair of channels is enabled.

End of enumeration elements list.

PAIR2DECAP : Dual Edge Capture Mode Captures For Pair2
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

The dual edge captures are inactive.

#1 : 1

The dual edge captures are active.

End of enumeration elements list.

PAIR2DTEN : Deadtime Enable For Pair2
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

The deadtime insertion in this pair of channels is disabled.

#1 : 1

The deadtime insertion in this pair of channels is enabled.

End of enumeration elements list.

PAIR2SYNCEN : Synchronization Enable For Pair2
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

The PWM synchronization in this pair of channels is disabled.

#1 : 1

The PWM synchronization in this pair of channels is enabled.

End of enumeration elements list.

PAIR2FAULTEN : Fault Control Enable For Pair2
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

The fault control in this pair of channels is disabled.

#1 : 1

The fault control in this pair of channels is enabled.

End of enumeration elements list.


DTSET

Deadtime Paramenters Setting Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTSET DTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTVAL DTPSC

DTVAL : Deadtime Value
bits : 0 - 5 (6 bit)
access : read-write

DTPSC : Deadtime Prescaler Control Value
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#0x : 0x

Divide the system clock by 1.

#10 : 10

Divide the system clock by 4.

#11 : 11

Divide the system clock by 16.

End of enumeration elements list.


CH3SCR

Channel (n) Status And Control Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3SCR CH3SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ELSR0 ELSR1 MSR0 MSR1 CHIE CHIF

ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write

ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write

MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write

MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write

CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable channel interrupts. Use software polling.

#1 : 1

Enable channel interrupts.

End of enumeration elements list.

CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.


EXTTRIG

PWM External Trigger
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTTRIG EXTTRIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH2TRIG CH3TRIG CH4TRIG CH5TRIG CH0TRIG CH1TRIG INITTRIGEN TRIGF

CH2TRIG : Channel 2 Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The generation of the channel trigger is disabled.

#1 : 1

The generation of the channel trigger is enabled.

End of enumeration elements list.

CH3TRIG : Channel 3 Trigger Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The generation of the channel trigger is disabled.

#1 : 1

The generation of the channel trigger is enabled.

End of enumeration elements list.

CH4TRIG : Channel 4 Trigger Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The generation of the channel trigger is disabled.

#1 : 1

The generation of the channel trigger is enabled.

End of enumeration elements list.

CH5TRIG : Channel 5 Trigger Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The generation of the channel trigger is disabled.

#1 : 1

The generation of the channel trigger is enabled.

End of enumeration elements list.

CH0TRIG : Channel 0 Trigger Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The generation of the channel trigger is disabled.

#1 : 1

The generation of the channel trigger is enabled.

End of enumeration elements list.

CH1TRIG : Channel 1 Trigger Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The generation of the channel trigger is disabled.

#1 : 1

The generation of the channel trigger is enabled.

End of enumeration elements list.

INITTRIGEN : Initialization Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

The generation of initialization trigger is disabled.

#1 : 1

The generation of initialization trigger is enabled.

End of enumeration elements list.

TRIGF : Channel Trigger Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

No channel trigger was generated.

#1 : 1

A channel trigger was generated.

End of enumeration elements list.


CHOPOLCR

Channels Output Polarity Control Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHOPOLCR CHOPOLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0POL CH1POL CH2POL CH3POL CH4POL CH5POL

CH0POL : Channel 0 Polarity
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel polarity is active high.

#1 : 1

The channel polarity is active low.

End of enumeration elements list.

CH1POL : Channel 1 Polarity
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel polarity is active high.

#1 : 1

The channel polarity is active low.

End of enumeration elements list.

CH2POL : Channel 2 Polarity
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel polarity is active high.

#1 : 1

The channel polarity is active low.

End of enumeration elements list.

CH3POL : Channel 3 Polarity
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel polarity is active high.

#1 : 1

The channel polarity is active low.

End of enumeration elements list.

CH4POL : Channel 4 Polarity
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel polarity is active high.

#1 : 1

The channel polarity is active low.

End of enumeration elements list.

CH5POL : Channel 5 Polarity
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel polarity is active high.

#1 : 1

The channel polarity is active low.

End of enumeration elements list.


FDSR

Fault Detect Status Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDSR FDSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAULTDF0 FAULTDF1 FAULTDF2 FAULTDF3 FAULTIN WPEN FAULTDF

FAULTDF0 : Fault Detection Flag 0
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

No fault condition was detected at the fault input.

#1 : 1

A fault condition was detected at the fault input.

End of enumeration elements list.

FAULTDF1 : Fault Detection Flag 1
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

No fault condition was detected at the fault input.

#1 : 1

A fault condition was detected at the fault input.

End of enumeration elements list.

FAULTDF2 : Fault Detection Flag 2
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

No fault condition was detected at the fault input.

#1 : 1

A fault condition was detected at the fault input.

End of enumeration elements list.

FAULTDF3 : Fault Detection Flag 3
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

No fault condition was detected at the fault input.

#1 : 1

A fault condition was detected at the fault input.

End of enumeration elements list.

FAULTIN : Fault Inputs
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

The logic OR of the enabled fault inputs is 0.

#1 : 1

The logic OR of the enabled fault inputs is 1.

End of enumeration elements list.

WPEN : Write Protection Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Write protection is disabled. Write protected bits can be written.

#1 : 1

Write protection is enabled. Write protected bits cannot be written.

End of enumeration elements list.

FAULTDF : Fault Detection Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

No fault condition was detected.

#1 : 1

A fault condition was detected.

End of enumeration elements list.


CAPFILTER

Input Capture Filter Control
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPFILTER CAPFILTER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0CAPFVAL CH1CAPFVAL CH2CAPFVAL CH3CAPFVAL

CH0CAPFVAL : Channel 0 Input Filter
bits : 0 - 4 (5 bit)
access : read-write

CH1CAPFVAL : Channel 1 Input Filter
bits : 5 - 9 (5 bit)
access : read-write

CH2CAPFVAL : Channel 2 Input Filter
bits : 10 - 14 (5 bit)
access : read-write

CH3CAPFVAL : Channel 3 Input Filter
bits : 15 - 19 (5 bit)
access : read-write


FFAFER

Fault Filter and Fault Enable Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FFAFER FFAFER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FER0EN FER1EN FER2EN FER3EN FF0EN FF1EN FF2EN FF3EN FFVAL

FER0EN : Fault Input 0 Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fault input is disabled.

#1 : 1

Fault input is enabled.

End of enumeration elements list.

FER1EN : Fault Input 1 Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fault input is disabled.

#1 : 1

Fault input is enabled.

End of enumeration elements list.

FER2EN : Fault Input 2 Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fault input is disabled.

#1 : 1

Fault input is enabled.

End of enumeration elements list.

FER3EN : Fault Input 3 Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fault input is disabled.

#1 : 1

Fault input is enabled.

End of enumeration elements list.

FF0EN : Fault Input 0 Filter Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fault input filter is disabled.

#1 : 1

Fault input filter is enabled.

End of enumeration elements list.

FF1EN : Fault Input 1 Filter Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fault input filter is disabled.

#1 : 1

Fault input filter is enabled.

End of enumeration elements list.

FF2EN : Fault Input 2 Filter Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fault input filter is disabled.

#1 : 1

Fault input filter is enabled.

End of enumeration elements list.

FF3EN : Fault Input 3 Filter Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fault input filter is disabled.

#1 : 1

Fault input filter is enabled.

End of enumeration elements list.

FFVAL : Fault Input Filter
bits : 8 - 11 (4 bit)
access : read-write


MCVR

PWM Counter Max Count Value Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCVR MCVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCVR

MCVR : no description available
bits : 0 - 15 (16 bit)
access : read-write


CH3V

Channel (n) Value
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3V CH3V read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHCVAL

CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write


QEI

Quadrature Encoder/Decoder Interface Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QEI QEI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QEIEN TOFDIR QUADIR QUADMODE PHBPOL PHAPOL PHBFLTREN PHAFLTREN

QEIEN : Quadrature Decoder Mode Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Quadrature Decoder is Disable

#1 : 1

Quadrature Decoder is Enable

End of enumeration elements list.

TOFDIR : Timer Overflow Direction in Quadrature Decoder Mode
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

TOF bit was set on the bottom of counting

#1 : 1

TOF bit was set on the top of counting

End of enumeration elements list.

QUADIR : Quadrature Decoder Mode Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Quadrature Decoder is Disable

#1 : 1

Quadrature Decoder is Enable

End of enumeration elements list.

QUADMODE : Quadrature Decoder Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Phase A and phase B encoding mode.

#1 : 1

Count and direction encoding mode

End of enumeration elements list.

PHBPOL : Phase B Input Polarity
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal polarity

#1 : 1

Inverted polarity

End of enumeration elements list.

PHAPOL : Phase A Input Polarity
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal polarity

#1 : 1

Inverted polarity

End of enumeration elements list.

PHBFLTREN : Phase B Input Filter Enable Register
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Phase B input filter is disabled

#1 : 1

Phase B input filter is enabled

End of enumeration elements list.

PHAFLTREN : Phase A Input Filter Enable Register
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Phase A input filter is disabled

#1 : 1

Phase A input filter is enabled

End of enumeration elements list.


CONF

Configuration
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONF CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTOFNUM BDMMODE GTBEEN GTBEOUT EVENTPSC

CNTOFNUM : Count Overflow Flag Number
bits : 0 - 6 (7 bit)
access : read-write

BDMMODE : Debug Mode
bits : 7 - 8 (2 bit)
access : read-write

GTBEEN : Global Time Base Enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Use of an external global time base is disabled.

#1 : 1

Use of an external global time base is enabled.

End of enumeration elements list.

GTBEOUT : Global Time Base Output
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

A global time base signal generation is disabled.

#1 : 1

A global time base signal generation is enabled.

End of enumeration elements list.

EVENTPSC : PWM Channel Input Event Prescale Setting
bits : 16 - 27 (12 bit)
access : read-write


FLTPOL

PWM Fault Input Polarity
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLTPOL FLTPOL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLT0POL FLT1POL FLT2POL FLT3POL

FLT0POL : Fault Input 0 Polarity
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The fault input polarity is active high. A 1 at the fault input indicates a fault.

#1 : 1

The fault input polarity is active low. A 0 at the fault input indicates a fault.

End of enumeration elements list.

FLT1POL : Fault Input 1 Polarity
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The fault input polarity is active high. A 1 at the fault input indicates a fault.

#1 : 1

The fault input polarity is active low. A 0 at the fault input indicates a fault.

End of enumeration elements list.

FLT2POL : Fault Input 2 Polarity
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The fault input polarity is active high. A 1 at the fault input indicates a fault.

#1 : 1

The fault input polarity is active low. A 0 at the fault input indicates a fault.

End of enumeration elements list.

FLT3POL : Fault Input 3 Polarity
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The fault input polarity is active high. A 1 at the fault input indicates a fault.

#1 : 1

The fault input polarity is active low. A 0 at the fault input indicates a fault.

End of enumeration elements list.


SYNCONF

Synchronization Configuration
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNCONF SYNCONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HWTRIGMODESEL CNTINC INVC SWOC SYNCMODE CNTVSWSYNC PWMSVSWSYNC OMVSWSYNC INVSWSYNC SWVSWSYNC CNTVHWSYNC PWMSVHWSYNC OMVHWSYNC INVHWSYNC SWVHWSYNC SWPOL HWPOL

HWTRIGMODESEL : Hardware Trigger Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.

#1 : 1

PWM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.

End of enumeration elements list.

CNTINC : CNTIN Register Synchronization
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

CNTIN register is updated with its buffer value at all rising edges of system clock.

#1 : 1

CNTIN register is updated with its buffer value by the PWM synchronization.

End of enumeration elements list.

INVC : INVCTRL Register Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

INVCTRL register is updated with its buffer value at all rising edges of system clock.

#1 : 1

INVCTRL register is updated with its buffer value by the PWM synchronization.

End of enumeration elements list.

SWOC : SWOCTRL Register Synchronization
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

SWOCTRL register is updated with its buffer value at all rising edges of system clock.

#1 : 1

SWOCTRL register is updated with its buffer value by the PWM synchronization.

End of enumeration elements list.

SYNCMODE : Synchronization Mode
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Legacy PWM synchronization is selected.

#1 : 1

Enhanced PWM synchronization is selected.

End of enumeration elements list.

CNTVSWSYNC : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The software trigger does not activate the PWM counter synchronization.

#1 : 1

The software trigger activates the PWM counter synchronization.

End of enumeration elements list.

PWMSVSWSYNC : no description available
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The software trigger does not activate MOD, CNTIN, and CV registers synchronization.

#1 : 1

The software trigger activates MOD, CNTIN, and CV registers synchronization.

End of enumeration elements list.

OMVSWSYNC : no description available
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The software trigger does not activate the OUTMASK register synchronization.

#1 : 1

The software trigger activates the OUTMASK register synchronization.

End of enumeration elements list.

INVSWSYNC : no description available
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The software trigger does not activate the INVCTRL register synchronization.

#1 : 1

The software trigger activates the INVCTRL register synchronization.

End of enumeration elements list.

SWVSWSYNC : no description available
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The software trigger does not activate the SWOCTRL register synchronization.

#1 : 1

The software trigger activates the SWOCTRL register synchronization.

End of enumeration elements list.

CNTVHWSYNC : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

A hardware trigger does not activate the PWM counter synchronization.

#1 : 1

A hardware trigger activates the PWM counter synchronization.

End of enumeration elements list.

PWMSVHWSYNC : no description available
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.

#1 : 1

A hardware trigger activates MOD, CNTIN, and CV registers synchronization.

End of enumeration elements list.

OMVHWSYNC : no description available
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

A hardware trigger does not activate the OUTMASK register synchronization.

#1 : 1

A hardware trigger activates the OUTMASK register synchronization.

End of enumeration elements list.

INVHWSYNC : no description available
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

A hardware trigger does not activate the INVCTRL register synchronization.

#1 : 1

A hardware trigger activates the INVCTRL register synchronization.

End of enumeration elements list.

SWVHWSYNC : no description available
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

A hardware trigger does not activate the SWOCTRL register synchronization.

#1 : 1

A hardware trigger activates the SWOCTRL register synchronization.

End of enumeration elements list.

SWPOL : Channel POL synchronization is activeated by a softwaretrigger
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

The software trigger does not activate the POL register synchronization.

#1 : 1

The software trigger activates POL register synchronization.

End of enumeration elements list.

HWPOL : Channel POL synchronization is activeated by a hardwaretrigger
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

The hardware trigger does not activate the POL register synchronization.

#1 : 1

>The hardware trigger activates POL register synchronization.

End of enumeration elements list.


INVCR

PWM Inverse Control Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INVCR INVCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAIR0INVEN PAIR1INVEN PAIR2INVEN

PAIR0INVEN : Pair Channels 0 Inverting Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inverting is disabled.

#1 : 1

Inverting is enabled.

End of enumeration elements list.

PAIR1INVEN : Pair Channels 1 Inverting Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inverting is disabled.

#1 : 1

Inverting is enabled.

End of enumeration elements list.

PAIR2INVEN : Pair Channels 2 Inverting Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inverting is disabled.

#1 : 1

Inverting is enabled.

End of enumeration elements list.


CHOSWCR

PWM CHannel Software Output Control Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHOSWCR CHOSWCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0SWEN CH1SWEN CH2SWEN CH3SWEN CH4SWEN CH5SWEN CH0SWCV CH1SWCV CH2SWCV CH3SWCV CH4SWCV CH5SWCV

CH0SWEN : Channel 0 Software Output Control Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel output is not affected by software output control.

#1 : 1

The channel output is affected by software output control.

End of enumeration elements list.

CH1SWEN : Channel 1 Software Output Control Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel output is not affected by software output control.

#1 : 1

The channel output is affected by software output control.

End of enumeration elements list.

CH2SWEN : Channel 2 Software Output Control Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel output is not affected by software output control.

#1 : 1

The channel output is affected by software output control.

End of enumeration elements list.

CH3SWEN : Channel 3 Software Output Control Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel output is not affected by software output control.

#1 : 1

The channel output is affected by software output control.

End of enumeration elements list.

CH4SWEN : Channel 4 Software Output Control Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel output is not affected by software output control.

#1 : 1

The channel output is affected by software output control.

End of enumeration elements list.

CH5SWEN : Channel 5 Software Output Control Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The channel output is not affected by software output control.

#1 : 1

The channel output is affected by software output control.

End of enumeration elements list.

CH0SWCV : Channel 0 Software Output Control Value
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The software output control forces 0 to the channel output.

#1 : 1

The software output control forces 1 to the channel output.

End of enumeration elements list.

CH1SWCV : Channel 1 Software Output Control Value
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The software output control forces 0 to the channel output.

#1 : 1

The software output control forces 1 to the channel output.

End of enumeration elements list.

CH2SWCV : Channel 2 Software Output Control Value
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The software output control forces 0 to the channel output.

#1 : 1

The software output control forces 1 to the channel output.

End of enumeration elements list.

CH3SWCV : Channel 3 Software Output Control Value
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The software output control forces 0 to the channel output.

#1 : 1

The software output control forces 1 to the channel output.

End of enumeration elements list.

CH4SWCV : Channel 4 Software Output Control Value
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The software output control forces 0 to the channel output.

#1 : 1

The software output control forces 1 to the channel output.

End of enumeration elements list.

CH5SWCV : Channel 5 Software Output Control Value
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

The software output control forces 0 to the channel output.

#1 : 1

The software output control forces 1 to the channel output.

End of enumeration elements list.


CH4SCR

Channel (n) Status And Control Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4SCR CH4SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ELSR0 ELSR1 MSR0 MSR1 CHIE CHIF

ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write

ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write

MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write

MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write

CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable channel interrupts. Use software polling.

#1 : 1

Enable channel interrupts.

End of enumeration elements list.

CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.


CH4V

Channel (n) Value
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4V CH4V read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHCVAL

CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write


CH5SCR

Channel (n) Status And Control Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5SCR CH5SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ELSR0 ELSR1 MSR0 MSR1 CHIE CHIF

ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write

ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write

MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write

MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write

CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable channel interrupts. Use software polling.

#1 : 1

Enable channel interrupts.

End of enumeration elements list.

CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.


CH5V

Channel (n) Value
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5V CH5V read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHCVAL

CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write



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