Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
CTU Configuration Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTRG : ACMP Trigger PWM2 Selection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP0 Output Trigger PWM
#1 : 1
ACMP1 Output Trigger PWM
End of enumeration elements list.
RXDFE : UART1 RxD filter Selection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
RXD1 input signal is connected to UART1 modulate directly
#01 : 01
RXD1 input signal is filtered by ACMP0, then injected to UART1
#10 : 10
RXD1 input signal is filtered by ACMP1, then injected to UART1
#11 : 11
Not Defined
End of enumeration elements list.
RTCC : Real-Time Counter Capture
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC Overflow is not connected to PWM1 Channel 1
#1 : 1
RTC overflow is connected to PWM1 Channel 1
End of enumeration elements list.
ACIC : Analog Comparator to Input Capture Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP0 Output is not connected to PWM1 Channel0
#1 : 1
ACMP1 Output is connected to PWM1 Channel0
End of enumeration elements list.
RXDCE : UART0_RX Capture Selection
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1_RX input connect to UART1 Only
#1 : 1
UART1_RX input connected to PWM0 Channel 1
End of enumeration elements list.
PWMSYNC : PWM SW Synchronization Selection
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Synchronization triggered
#1 : 1
Generate PWM Synchronization to trigger PWM Modules
End of enumeration elements list.
TXDME : UART1 TX Modulation Selection
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1_TX is connected to PIN out directly
#1 : 1
UART1_TX is modulated by PWM0 Channel 0
End of enumeration elements list.
CLK : BUS Clock Output Selection
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
BUS Clock
#001 : 001
Bus Divided by 2
#010 : 010
Bus Divided by 4
#011 : 011
Bus Divided by 8
#100 : 100
Bus Divided by 16
#101 : 101
Bus Divided by 32
#110 : 110
Bus Divided by 64
#111 : 111
Bus Divided by 128
End of enumeration elements list.
ADHWT1 : ADC Hardware Trigger Source for regular group
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 000
RTC Overflow as ADC hardware Trigger
#001 : 001
PWM0 as ADC Hardware Trigger
#010 : 010
PWM2 Init Trigger with 8-bit programmable counter delay
#011 : 011
PWM2 Match Trigger with 8-bit programmable counter delay
#100 : 100
Timer Channel0 overflow as ADC Hardware Trigger
#101 : 101
Timer Channel1 overflow as ADC hardware Trigger
#110 : 110
ACMP0 Out as ADC Hardware Trigger
#111 : 111
ACMP1 Out as ADC Hardware Trigger
End of enumeration elements list.
DLYACT : Trigger Delay Active
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Delay is inactive
#1 : 1
Delay is active
End of enumeration elements list.
DELAY : Trigger Delay Counter
bits : 24 - 31 (8 bit)
access : read-write
CTU Configuration Register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACPWTS : PWDT ACMP_OUT Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP1_OUT is Connected to PWDT_IN3
#1 : 1
ACMP0_OUT is Connected to PWDT_IN3
End of enumeration elements list.
UARTPWDTS : PWDT UART RX Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
UART0 RX is connected to PWDT_IN3
#01 : 01
UART1 RX is connected to PWDT_IN3
#10 : 10
UART2 RX is connected to PWDT_IN3
#11 : 11
ACMP_OUT is Connected to PWTIN3
End of enumeration elements list.
ADHWT2 : ADC Hardware Trigger Source for injection group
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
#000 : 000
RTC Overflow as the ADC hardware trigger
#001 : 001
PWM0 as the ADC hardware trigger
#010 : 010
PWM2 init trigger with 8-bit programmable count delay as ADC hardware trigger
#011 : 011
PWM2 match trigger with 8-bit programmable count delay as ADC hardware trigger
#100 : 100
Timer Channel0 overflow as the ADC hardware trigger
#101 : 101
Timer Channel1 overflow as the ADC hardware trigger
#110 : 110
ACMP0 output as the ADC hardware trigger
#111 : 111
ACMP1 output as the ADC hardware trigger
End of enumeration elements list.
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