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UART2

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RBR

LCR1

FCR

EFR

IER

LSR0

LSR1

SMP_CNT

GUARD

SLEEP

DIV_L

DMA

DIV_FRAC

RS485CR

SLADDR

CNTR

MULCOMCR

DIV_H

LCR0


RBR

RX/TX Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RBR RBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBR_THR

RBR_THR : RX/TX Data Register
bits : 0 - 7 (8 bit)
access : read-write


LCR1

uart control register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCR1 LCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXEN TXEN LOOP WLS2 INVRX INVTX

RXEN : uart receiver enable
bits : 0 - 0 (1 bit)
access : read-write

TXEN : uart Transmitter enable
bits : 1 - 1 (1 bit)
access : read-write

LOOP : uart loop back mode enable
bits : 4 - 4 (1 bit)
access : read-write

WLS2 : uart 9 bit data mode enable/disable bit
bits : 5 - 5 (1 bit)
access : read-write

INVRX : uart rx input inverse enable/disable bit
bits : 6 - 6 (1 bit)
access : read-write

INVTX : uart tx output inverse enable/disable bit
bits : 7 - 7 (1 bit)
access : read-write


FCR

FIFO Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCR FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOE

FIFOE : RX and TX FIFO enable/disable bit
bits : 0 - 0 (1 bit)
access : read-write


EFR

hardware flow control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EFR EFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTS RTS

CTS : hardware transmiison flow control enable/disable bit
bits : 6 - 6 (1 bit)
access : read-write

RTS : hardware reception flow control enable/disable bit
bits : 7 - 7 (1 bit)
access : read-write


IER

Interrupt Enable register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERXEN ETXE ETC EPE EFE ENE EOEBI EDCTS

ERXEN : receiving data not empty interrupt enable bit
bits : 0 - 0 (1 bit)
access : read-write

ETXE : transmitting data empty interrupt enable bit
bits : 1 - 1 (1 bit)
access : read-write

ETC : transmitting completed interrupt enable bit
bits : 2 - 2 (1 bit)
access : read-write

EPE : parity error interrupt enable bit
bits : 3 - 3 (1 bit)
access : read-write

EFE : overflow or frame error interrupt enable bit
bits : 4 - 4 (1 bit)
access : read-write

ENE : noise error interrupt enable bit
bits : 5 - 5 (1 bit)
access : read-write

EOEBI : overflow error or break error interrupt enable bit
bits : 6 - 6 (1 bit)
access : read-write

EDCTS : CTS_n changing interrupt enable bit
bits : 7 - 7 (1 bit)
access : read-write


LSR0

Line Status Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LSR0 LSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR OE PE FE BI THRE TC NE

DR : Data ready flag
bits : 0 - 0 (1 bit)
access : read-write

OE : overrun error flag
bits : 1 - 1 (1 bit)
access : read-write

PE : parity error flag
bits : 2 - 2 (1 bit)
access : read-write

FE : frame error flag
bits : 3 - 3 (1 bit)
access : read-write

BI : break error flag
bits : 4 - 4 (1 bit)
access : read-write

THRE : the empty flag of TX holding register or TX FIFO
bits : 5 - 5 (1 bit)
access : read-write

TC : Transmitting finished flag
bits : 6 - 6 (1 bit)
access : read-write

NE : noise error flag
bits : 7 - 7 (1 bit)
access : read-write


LSR1

Line Status Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LSR1 LSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDLE FBRK DCTS UART_IDLE CTS RTS

IDLE : IDLE flag
bits : 0 - 0 (1 bit)
access : read-write

FBRK : LIN break occurrer flag
bits : 2 - 2 (1 bit)
access : read-write

DCTS : flag of pin CTS_n signal changing
bits : 3 - 3 (1 bit)
access : read-write

UART_IDLE : UART IDLE
bits : 5 - 5 (1 bit)
access : read-write

CTS : Hardware flow status - CTS
bits : 6 - 6 (1 bit)
access : read-write

RTS : Hardware flow status - RTS
bits : 7 - 7 (1 bit)
access : read-write


SMP_CNT

uart sample counter register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMP_CNT SMP_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP_CNT

SMP_CNT : uart sample counter
bits : 0 - 1 (2 bit)
access : read-write


GUARD

uart guard time register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GUARD GUARD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GUARD_CNT GUARD_EN

GUARD_CNT : Guard interval count value
bits : 0 - 3 (4 bit)
access : read-write

GUARD_EN : Guard interval time added enabling signal
bits : 4 - 4 (1 bit)
access : read-write


SLEEP

uart sleep enable register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLEEP SLEEP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLEEP_EN

SLEEP_EN : uart sleep function enable bit
bits : 0 - 0 (1 bit)
access : read-write


DIV_L

Divisor low 8 bits register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV_L DIV_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_L

DIV_L : uart baud rate divisor low 8 bits
bits : 0 - 7 (8 bit)
access : read-write


DMA

uart DMA enable register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDMAEN TXDMAEN

RXDMAEN : uart RX DMA enable bit
bits : 0 - 0 (1 bit)
access : read-write

TXDMAEN : uart TX DMA enable bit
bits : 1 - 1 (1 bit)
access : read-write


DIV_FRAC

Uart Fractional Divider Address
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV_FRAC DIV_FRAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_FRAC

DIV_FRAC : uart fractional divider
bits : 0 - 7 (8 bit)
access : read-write


RS485CR

Uart RS485 control register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RS485CR RS485CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLYEN INVPOL RS485EN

DLYEN : Delay insert between the last stop bit and rts_n or dtr_n de-assertion
bits : 4 - 4 (1 bit)
access : read-write

INVPOL : inverse the polarity of rts_n
bits : 5 - 5 (1 bit)
access : read-write

RS485EN : RS485 mode enable bit
bits : 7 - 7 (1 bit)
access : read-write


SLADDR

Uart address for wake up
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLADDR SLADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLADDR

SLADDR : slave address for RS485
bits : 0 - 7 (8 bit)
access : read-write


CNTR

Uart Counter time delay in RS485 mode
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR CNTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTR

CNTR : Uart Counter time delay in RS485 mode
bits : 0 - 7 (8 bit)
access : read-write


MULCOMCR

Uart multiprocessor communication control register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MULCOMCR MULCOMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDLEIE RWUCRT WAKESEL MULCOMEN

IDLEIE : IDLE interrupt enable bit
bits : 4 - 4 (1 bit)
access : read-write

RWUCRT : Receiver wakeup control
bits : 5 - 5 (1 bit)
access : read-write

WAKESEL : Wakeup method select
bits : 6 - 6 (1 bit)
access : read-write

MULCOMEN : Multi communication enable bit
bits : 7 - 7 (1 bit)
access : read-write


DIV_H

Divisor high 8 bits register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV_H DIV_H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_H

DIV_H : uart baud rate divisor high 8 bits
bits : 0 - 7 (8 bit)
access : read-write


LCR0

uart control register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCR0 LCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLS STB PEN EPS SP SUB

WLS : uart data mode select bits
bits : 0 - 1 (2 bit)
access : read-write

STB : Number of STOP bits
bits : 2 - 2 (1 bit)
access : read-write

PEN : uart parity enable/disable bit
bits : 3 - 3 (1 bit)
access : read-write

EPS : odd/eveen number select bit
bits : 4 - 4 (1 bit)
access : read-write

SP : stick parity
bits : 5 - 5 (1 bit)
access : read-write

SUB : Sets up break
bits : 6 - 6 (1 bit)
access : read-write



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