\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
configuration and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSOFF : BUS off status
bits : 0 - 0 (1 bit)
access : read-write
TACTIVE : Transmission Active
bits : 1 - 1 (1 bit)
access : read-write
RACTIVE : Reception Active
bits : 2 - 2 (1 bit)
access : read-write
TSSS : Transmission Secondary single shot mode for STB
bits : 3 - 3 (1 bit)
access : read-write
TPSS : Transmission Primary single shot mode for PTB
bits : 4 - 4 (1 bit)
access : read-write
LBMI : Loop back mode internal
bits : 5 - 5 (1 bit)
access : read-write
LBME : Loop back mode, external
bits : 6 - 6 (1 bit)
access : read-write
RESET : reset request bit
bits : 7 - 7 (1 bit)
access : read-write
TSA : Transmit Secondary Abort
bits : 8 - 8 (1 bit)
access : read-write
TSALL : Transmit Secondary All frames
bits : 9 - 9 (1 bit)
access : read-write
TSONE : Transmit Secondary one Frame
bits : 10 - 10 (1 bit)
access : read-write
TPA : Transmit Primary Abort
bits : 11 - 11 (1 bit)
access : read-write
TPE : Transmit Primary Enable
bits : 12 - 12 (1 bit)
access : read-write
STBY : Transceiver Standby mode
bits : 13 - 13 (1 bit)
access : read-write
LOM : Listen Only mode
bits : 14 - 14 (1 bit)
access : read-write
TBSEL : Transmit Buffer Select
bits : 15 - 15 (1 bit)
access : read-write
TSSTAT : Transmit Secondary status bits
bits : 16 - 17 (2 bit)
access : read-write
TTTBM : TTCAN Transmit Buffer Mode
bits : 20 - 20 (1 bit)
access : read-write
TSMODE : Transmit buffer Secondary operation Mode
bits : 21 - 21 (1 bit)
access : read-write
TSNEXT : Transmit Buffer Secondary next
bits : 22 - 22 (1 bit)
access : read-write
RSTAT : Receive Buffer status bits
bits : 24 - 25 (2 bit)
access : read-only
RREL : Receive Buffer Release
bits : 28 - 28 (1 bit)
access : read-write
ROV : Receive Buffer Overflow
bits : 29 - 29 (1 bit)
access : read-write
ROM : Receive Buffer Overflow Mode
bits : 30 - 30 (1 bit)
access : read-write
Error and Arbitration Lost Capture Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALC : Arbitration Lost Capture
bits : 0 - 4 (5 bit)
access : read-only
KOER : Kind of Error
bits : 5 - 7 (3 bit)
access : read-only
RECNT : Receive Error Count
bits : 16 - 23 (8 bit)
access : read-only
TECNT : Transmit Error Count
bits : 24 - 31 (8 bit)
access : read-only
Acceptance Filter Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACFADR : Acceptance filter address
bits : 0 - 3 (4 bit)
access : read-write
SELMASK : Select Acceptance MASK
bits : 5 - 5 (1 bit)
access : read-write
AE0 : Acceptance Filter Enable
bits : 16 - 16 (1 bit)
access : read-write
AE1 : Acceptance Filter Enable
bits : 17 - 17 (1 bit)
access : read-write
AE2 : Acceptance Filter Enable
bits : 18 - 18 (1 bit)
access : read-write
AE3 : Acceptance Filter Enable
bits : 19 - 19 (1 bit)
access : read-write
AE4 : Acceptance Filter Enable
bits : 20 - 20 (1 bit)
access : read-write
AE5 : Acceptance Filter Enable
bits : 21 - 21 (1 bit)
access : read-write
AE6 : Acceptance Filter Enable
bits : 22 - 22 (1 bit)
access : read-write
AE7 : Acceptance Filter Enable
bits : 23 - 23 (1 bit)
access : read-write
AE8 : Acceptance Filter Enable
bits : 24 - 24 (1 bit)
access : read-write
AE9 : Acceptance Filter Enable
bits : 25 - 25 (1 bit)
access : read-write
AE10 : Acceptance Filter Enable
bits : 26 - 26 (1 bit)
access : read-write
AE11 : Acceptance Filter Enable
bits : 27 - 27 (1 bit)
access : read-write
AE12 : Acceptance Filter Enable
bits : 28 - 28 (1 bit)
access : read-write
AE13 : Acceptance Filter Enable
bits : 29 - 29 (1 bit)
access : read-write
AE14 : Acceptance Filter Enable
bits : 30 - 30 (1 bit)
access : read-write
AE15 : Acceptance Filter Enable
bits : 31 - 31 (1 bit)
access : read-write
Acceptance Code Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACODE : Acceptance Code
bits : 0 - 28 (29 bit)
access : read-write
AIDE : Acceptance Mask IDE Bit value
bits : 29 - 29 (1 bit)
access : read-write
AIDEE : Acceptance Mask IDE bit check enable
bits : 30 - 30 (1 bit)
access : read-write
Version Information Register 0
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VER : Version of CAN-CTRL
bits : 0 - 15 (16 bit)
access : read-write
TBPTR : pointer to a TB message slot
bits : 16 - 21 (6 bit)
access : read-write
TBF : set TB slot to "Filled"
bits : 22 - 22 (1 bit)
access : read-write
TBE : set TB slot to "Empty"
bits : 23 - 23 (1 bit)
access : read-write
TTEN : Timer Trigger Enable
bits : 24 - 24 (1 bit)
access : read-write
PRESC : TTCAN Timer Prescaler
bits : 25 - 26 (2 bit)
access : read-write
TTIF : Timer Trigger Interrupt Flag
bits : 27 - 27 (1 bit)
access : read-write
TTIE : Timer Trigger Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write
TEIF : Trigger Error Interrupt Flag
bits : 29 - 29 (1 bit)
access : read-write
WTIF : Watch Trigger Interrupt Flag
bits : 30 - 30 (1 bit)
access : read-write
WTIE : Watch Trigger Interrupt Enable
bits : 31 - 31 (1 bit)
access : read-write
TTCAN: Reference Message
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Reference Message
bits : 0 - 28 (29 bit)
access : read-write
IDE : Reference Message IDE Bit
bits : 31 - 31 (1 bit)
access : read-write
TTCAN:Trigger Configuration
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TTPTR : Transmit Trigger TB Slot Pointer
bits : 0 - 5 (6 bit)
access : read-write
TTYPE : trigger type
bits : 8 - 10 (3 bit)
access : read-write
TEW : Transmit enable window
bits : 12 - 15 (4 bit)
access : read-write
TRIG : trigger time
bits : 16 - 31 (16 bit)
access : read-write
TTCAN: Watch Trigger Tim
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WTRIG : watch trigger time
bits : 0 - 15 (16 bit)
access : read-write
Receive and Transmit Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSFF : Transmit Secondary Buffer full flag
bits : 0 - 0 (1 bit)
access : read-write
EIE : Error Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
TSIE : Transmit Secondary Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
TPIE : Transmit Primary Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
RAFIE : RB Almost Full Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
RFIE : RB Full Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
ROIE : RB Overflow Interrupt enable
bits : 6 - 6 (1 bit)
access : read-write
RIE : Receive Interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
AIF : Abort Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write
EIF : Error Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-write
TSIF : Transmission Secondary Interrupt Flag
bits : 10 - 10 (1 bit)
access : read-write
TPIF : Transmission Primary Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-write
RAFIF : RB Almost Full Interrupt flag
bits : 12 - 12 (1 bit)
access : read-write
RFIF : RB Full Interrupt flag
bits : 13 - 13 (1 bit)
access : read-write
ROIF : RB Overflow Interrupt flag
bits : 14 - 14 (1 bit)
access : read-write
RIF : Receive Interrupt flag
bits : 15 - 15 (1 bit)
access : read-write
BEIF : Bus Error Interrupt flag
bits : 16 - 16 (1 bit)
access : read-write
BEIE : Bus Error Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
ALIF : Arbitration Lost Interrupt Flag
bits : 18 - 18 (1 bit)
access : read-write
ALIE : Arbitration Lost Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write
EPIF : Error Passive Interrupt Flag
bits : 20 - 20 (1 bit)
access : read-write
EPIE : Error Passive Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
EPASS : Error Passive Mode Active enable bit
bits : 22 - 22 (1 bit)
access : read-write
EWARN : Error Warning Limit Reached
bits : 23 - 23 (1 bit)
access : read-write
EWL : Programmable Error Warnig Limit
bits : 24 - 27 (4 bit)
access : read-write
AFWL : Receive Buffer Almost Full Warning Limit
bits : 28 - 31 (4 bit)
access : read-write
Bit Timing Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S_Seg_1 : Bit Timing Segment 1
bits : 0 - 7 (8 bit)
access : read-write
S_Seg_2 : Bit Timing Segment 2
bits : 8 - 14 (7 bit)
access : read-write
S_SJW : Synchronization Jump Width
bits : 16 - 22 (7 bit)
access : read-write
S_PRESC : Prescaler
bits : 24 - 31 (8 bit)
access : read-write
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