\n

LIN0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x84 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SYS

STS

IFCR2

ESTS

IFCR3

TO1

TO2

IFCR4

IBR

IFCR5

FBR

IFCR6

CS

FRM

IFCR7

BDLR

IFCR8

BDHR

IFEN

IFCR9

IFMR

CTRL1

IFMI

IFCR10

IFCR11

IFCR12

IFCR13

IFCR14

IFCR15

CTRL2

IFCR0

IEN

IFCR1


SYS

LIN System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS SYS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LM

LM : LIN Mode Select
bits : 0 - 1 (2 bit)
access : read-write


STS

LIN Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STS STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTRF DTF DRF WUF PS RTIP RRIP STS

HTRF : Header Transmission/Reception Flag
bits : 0 - 0 (1 bit)
access : write-clear

DTF : Data Transmission Completed Flag
bits : 1 - 1 (1 bit)
access : write-clear

DRF : Data Reception Completed Flag
bits : 2 - 2 (1 bit)
access : write-clear

WUF : Wake-up Flag
bits : 3 - 3 (1 bit)
access : write-clear

PS : LIN receive pin state
bits : 4 - 4 (1 bit)
access : read-only

RTIP : Response TX in Progress
bits : 5 - 5 (1 bit)
access : read-only

RRIP : Response RX in Progress
bits : 6 - 6 (1 bit)
access : read-only

STS : LIN mode status
bits : 8 - 11 (4 bit)
access : read-only


IFCR2

LIN ID filter control register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR2 IFCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


ESTS

LIN Error Status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ESTS ESTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NF BOF FEF IPEF BDEF SFEF CEF BEF TOEF LZEF

NF : Noise Flag
bits : 0 - 0 (1 bit)
access : write-clear

BOF : Buffer Overrun Flag
bits : 1 - 1 (1 bit)
access : write-clear

FEF : Framing Error Flag
bits : 2 - 2 (1 bit)
access : write-clear

IPEF : Identifier Parity Error Flag
bits : 3 - 3 (1 bit)
access : write-clear

BDEF : Break Delimiter Error Flag
bits : 4 - 4 (1 bit)
access : write-clear

SFEF : Synch Field Error Flag
bits : 5 - 5 (1 bit)
access : write-clear

CEF : Checksum Error Flag
bits : 6 - 6 (1 bit)
access : write-clear

BEF : Bit Error Flag
bits : 7 - 7 (1 bit)
access : write-clear

TOEF : Time Out Error Flag
bits : 8 - 8 (1 bit)
access : write-clear

LZEF : Long Zero Error Flag
bits : 9 - 9 (1 bit)
access : write-clear


IFCR3

LIN ID filter control register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR3 IFCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


TO1

LIN Time out control register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TO1 TO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTO

HTO : Header timeout value
bits : 0 - 5 (6 bit)
access : read-write


TO2

LIN Time out control register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TO2 TO2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOEN

TOEN : Header timeout enable
bits : 0 - 0 (1 bit)
access : read-write


IFCR4

LIN ID filter control register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR4 IFCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


IBR

LIN integer baud rate register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IBR IBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IBR

IBR : Integer baud rate divide value
bits : 0 - 11 (12 bit)
access : read-write


IFCR5

LIN ID filter control register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR5 IFCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


FBR

LIN fractional baud rate register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FBR FBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBR

FBR : Fractional baud rate divide value
bits : 0 - 3 (4 bit)
access : read-write


IFCR6

LIN ID filter control register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR6 IFCR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


CS

LIN Checksum field register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS CS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CS

CS : LIN Checksum field value
bits : 0 - 7 (8 bit)
access : read-write


FRM

LIN Frame Control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRM FRM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data field length
bits : 11 - 12 (2 bit)
access : read-write


IFCR7

LIN ID filter control register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR7 IFCR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


BDLR

Buffer data low register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDLR BDLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA0 DATA1 DATA2 DATA3

DATA0 : Data 0
bits : 0 - 7 (8 bit)
access : read-write

DATA1 : Data 1
bits : 8 - 15 (8 bit)
access : read-write

DATA2 : Data 2
bits : 16 - 23 (8 bit)
access : read-write

DATA3 : Data 3
bits : 24 - 31 (8 bit)
access : read-write


IFCR8

LIN ID filter control register
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR8 IFCR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


BDHR

Buffer data High register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDHR BDHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA4 DATA5 DATA6 DATA7

DATA4 : Data 4
bits : 0 - 7 (8 bit)
access : read-write

DATA5 : Data 5
bits : 8 - 15 (8 bit)
access : read-write

DATA6 : Data 6
bits : 16 - 23 (8 bit)
access : read-write

DATA7 : Data 7
bits : 24 - 31 (8 bit)
access : read-write


IFEN

LIN ID Filter enable register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFEN IFEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Filter Number Enable
bits : 0 - 15 (16 bit)
access : read-write


IFCR9

LIN ID filter control register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR9 IFCR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


IFMR

LIN ID Filter mode register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFMR IFMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFM

IFM : ID Filter Mode
bits : 0 - 7 (8 bit)
access : read-write


CTRL1

LIN Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM LBM STM SCM BLT BTL ATWU RSE MCS BDL HIL RSL RIL DIOB

SM : LIN Slave Mode enable bit
bits : 0 - 0 (1 bit)
access : read-write

LBM : LIN Loop back Mode enable bit
bits : 1 - 1 (1 bit)
access : read-write

STM : LIN Self Test Mode enable bit
bits : 2 - 2 (1 bit)
access : read-write

SCM : LIN software control Mode enable bit
bits : 3 - 3 (1 bit)
access : read-write

BLT : LIN Break Length threshold select
bits : 4 - 4 (1 bit)
access : read-write

BTL : LIN Break field transmit length in master mode
bits : 8 - 11 (4 bit)
access : read-write

ATWU : Control the behavior of the LIN hardware during sleep mode
bits : 12 - 12 (1 bit)
access : read-write

RSE : LIN Slave Automatic Resynchronization Enable
bits : 13 - 13 (1 bit)
access : read-write

MCS : Disable the hardware checksum calculation
bits : 14 - 14 (1 bit)
access : read-write

BDL : Break delimiter length
bits : 15 - 15 (1 bit)
access : read-write

HIL : Header inter-byte length between sync field and PID filed in master mode
bits : 16 - 17 (2 bit)
access : read-write

RSL : Response inter space length, only for master mode
bits : 18 - 19 (2 bit)
access : read-write

RIL : Response inter byte length between response data
bits : 20 - 21 (2 bit)
access : read-write

DIOB : LIN State machine goes to IDLE on bit error detection
bits : 23 - 23 (1 bit)
access : read-write


IFMI

LIN ID Filter match index register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFMI IFMI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFMI

IFMI : ID Filter match index
bits : 0 - 4 (5 bit)
access : read-write


IFCR10

LIN ID filter control register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR10 IFCR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


IFCR11

LIN ID filter control register
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR11 IFCR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


IFCR12

LIN ID filter control register
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR12 IFCR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


IFCR13

LIN ID filter control register
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR13 IFCR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


IFCR14

LIN ID filter control register
address_offset : 0x5E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR14 IFCR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


IFCR15

LIN ID filter control register
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR15 IFCR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


CTRL2

LIN Control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTR RTR RDR WUTR

HTR : Header Transmission Requeset
bits : 0 - 0 (1 bit)
access : read-write

RTR : Data Transmission Request
bits : 2 - 2 (1 bit)
access : read-write

RDR : Response Discard Request
bits : 3 - 3 (1 bit)
access : read-write

WUTR : Wakeup TX Request
bits : 4 - 4 (1 bit)
access : read-write


IFCR0

LIN ID filter control register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR0 IFCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write


IEN

LIN Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTRIE RTIE RRIE WUIE FEIE BOIE HEIE CEIE BEIE TOIE LZIE

HTRIE : Header Received Interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

RTIE : Response Transmitted Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

RRIE : Response Reception Complete Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

WUIE : Wakeup Interrupt enable
bits : 5 - 5 (1 bit)
access : read-write

FEIE : Framing Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

BOIE : Buffer Overrun Interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

HEIE : Header Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

CEIE : Checksum error Interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

BEIE : Bit Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

TOIE : Timeout Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

LZIE : Long Zero Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write


IFCR1

LIN ID filter control register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR1 IFCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID CST DIR DFL

ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write

CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write

DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write

DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.