\n
address_offset : 0x0 Bytes (0x0)
size : 0x84 byte (0x0)
mem_usage : registers
protection : not protected
LIN System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LM : LIN Mode Select
bits : 0 - 1 (2 bit)
access : read-write
LIN Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTRF : Header Transmission/Reception Flag
bits : 0 - 0 (1 bit)
access : write-clear
DTF : Data Transmission Completed Flag
bits : 1 - 1 (1 bit)
access : write-clear
DRF : Data Reception Completed Flag
bits : 2 - 2 (1 bit)
access : write-clear
WUF : Wake-up Flag
bits : 3 - 3 (1 bit)
access : write-clear
PS : LIN receive pin state
bits : 4 - 4 (1 bit)
access : read-only
RTIP : Response TX in Progress
bits : 5 - 5 (1 bit)
access : read-only
RRIP : Response RX in Progress
bits : 6 - 6 (1 bit)
access : read-only
STS : LIN mode status
bits : 8 - 11 (4 bit)
access : read-only
LIN ID filter control register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
LIN Error Status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NF : Noise Flag
bits : 0 - 0 (1 bit)
access : write-clear
BOF : Buffer Overrun Flag
bits : 1 - 1 (1 bit)
access : write-clear
FEF : Framing Error Flag
bits : 2 - 2 (1 bit)
access : write-clear
IPEF : Identifier Parity Error Flag
bits : 3 - 3 (1 bit)
access : write-clear
BDEF : Break Delimiter Error Flag
bits : 4 - 4 (1 bit)
access : write-clear
SFEF : Synch Field Error Flag
bits : 5 - 5 (1 bit)
access : write-clear
CEF : Checksum Error Flag
bits : 6 - 6 (1 bit)
access : write-clear
BEF : Bit Error Flag
bits : 7 - 7 (1 bit)
access : write-clear
TOEF : Time Out Error Flag
bits : 8 - 8 (1 bit)
access : write-clear
LZEF : Long Zero Error Flag
bits : 9 - 9 (1 bit)
access : write-clear
LIN ID filter control register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
LIN Time out control register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTO : Header timeout value
bits : 0 - 5 (6 bit)
access : read-write
LIN Time out control register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOEN : Header timeout enable
bits : 0 - 0 (1 bit)
access : read-write
LIN ID filter control register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
LIN integer baud rate register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IBR : Integer baud rate divide value
bits : 0 - 11 (12 bit)
access : read-write
LIN ID filter control register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
LIN fractional baud rate register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBR : Fractional baud rate divide value
bits : 0 - 3 (4 bit)
access : read-write
LIN ID filter control register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
LIN Checksum field register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS : LIN Checksum field value
bits : 0 - 7 (8 bit)
access : read-write
LIN Frame Control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data field length
bits : 11 - 12 (2 bit)
access : read-write
LIN ID filter control register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
Buffer data low register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Data 0
bits : 0 - 7 (8 bit)
access : read-write
DATA1 : Data 1
bits : 8 - 15 (8 bit)
access : read-write
DATA2 : Data 2
bits : 16 - 23 (8 bit)
access : read-write
DATA3 : Data 3
bits : 24 - 31 (8 bit)
access : read-write
LIN ID filter control register
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
Buffer data High register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Data 4
bits : 0 - 7 (8 bit)
access : read-write
DATA5 : Data 5
bits : 8 - 15 (8 bit)
access : read-write
DATA6 : Data 6
bits : 16 - 23 (8 bit)
access : read-write
DATA7 : Data 7
bits : 24 - 31 (8 bit)
access : read-write
LIN ID Filter enable register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Filter Number Enable
bits : 0 - 15 (16 bit)
access : read-write
LIN ID filter control register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
LIN ID Filter mode register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFM : ID Filter Mode
bits : 0 - 7 (8 bit)
access : read-write
LIN Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SM : LIN Slave Mode enable bit
bits : 0 - 0 (1 bit)
access : read-write
LBM : LIN Loop back Mode enable bit
bits : 1 - 1 (1 bit)
access : read-write
STM : LIN Self Test Mode enable bit
bits : 2 - 2 (1 bit)
access : read-write
SCM : LIN software control Mode enable bit
bits : 3 - 3 (1 bit)
access : read-write
BLT : LIN Break Length threshold select
bits : 4 - 4 (1 bit)
access : read-write
BTL : LIN Break field transmit length in master mode
bits : 8 - 11 (4 bit)
access : read-write
ATWU : Control the behavior of the LIN hardware during sleep mode
bits : 12 - 12 (1 bit)
access : read-write
RSE : LIN Slave Automatic Resynchronization Enable
bits : 13 - 13 (1 bit)
access : read-write
MCS : Disable the hardware checksum calculation
bits : 14 - 14 (1 bit)
access : read-write
BDL : Break delimiter length
bits : 15 - 15 (1 bit)
access : read-write
HIL : Header inter-byte length between sync field and PID filed in master mode
bits : 16 - 17 (2 bit)
access : read-write
RSL : Response inter space length, only for master mode
bits : 18 - 19 (2 bit)
access : read-write
RIL : Response inter byte length between response data
bits : 20 - 21 (2 bit)
access : read-write
DIOB : LIN State machine goes to IDLE on bit error detection
bits : 23 - 23 (1 bit)
access : read-write
LIN ID Filter match index register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFMI : ID Filter match index
bits : 0 - 4 (5 bit)
access : read-write
LIN ID filter control register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
LIN ID filter control register
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
LIN ID filter control register
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
LIN ID filter control register
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
LIN ID filter control register
address_offset : 0x5E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
LIN ID filter control register
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
LIN Control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTR : Header Transmission Requeset
bits : 0 - 0 (1 bit)
access : read-write
RTR : Data Transmission Request
bits : 2 - 2 (1 bit)
access : read-write
RDR : Response Discard Request
bits : 3 - 3 (1 bit)
access : read-write
WUTR : Wakeup TX Request
bits : 4 - 4 (1 bit)
access : read-write
LIN ID filter control register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
LIN Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTRIE : Header Received Interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
RTIE : Response Transmitted Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
RRIE : Response Reception Complete Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
WUIE : Wakeup Interrupt enable
bits : 5 - 5 (1 bit)
access : read-write
FEIE : Framing Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
BOIE : Buffer Overrun Interrupt enable
bits : 9 - 9 (1 bit)
access : read-write
HEIE : Header Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
CEIE : Checksum error Interrupt enable
bits : 12 - 12 (1 bit)
access : read-write
BEIE : Bit Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
TOIE : Timeout Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
LZIE : Long Zero Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write
LIN ID filter control register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Identifier
bits : 0 - 5 (6 bit)
access : read-write
CST : Checksum type
bits : 8 - 8 (1 bit)
access : read-write
DIR : Direction
bits : 9 - 9 (1 bit)
access : read-write
DFL : Data Field Length
bits : 10 - 12 (3 bit)
access : read-write
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