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EXBUS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x200 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x300 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MODE0

MODE4

SDMODE

REFTIM

PWRDWN

SDTIM

SDCMD

MODE5

MODE6

MODE7

TIM0

MEMCERR

TIM1

TIM2

TIM3

TIM4

DCLKR

EST

WEAD

ESCLR

AMODE

TIM5

TIM6

TIM7

MODE1

AREA0

AREA1

AREA2

AREA3

AREA4

AREA5

AREA6

AREA7

ATIM0

ATIM1

ATIM2

ATIM3

ATIM4

ATIM5

ATIM6

ATIM7

MODE2

MODE3


MODE0

Mode Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 MODE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTH RBMON WEOFF NAND PAGE RDY SHRTDOUT MPXMODE ALEINV MPXDOFF MPXCSOF MOEXEUP

WDTH : specify Data Width
bits : 0 - 0 (1 bit)
access : read-write

RBMON : Read Byte Mask ON
bits : 2 - 1 (0 bit)
access : read-write

WEOFF : disable the write enable signal (MWEX) operation
bits : 3 - 2 (0 bit)
access : read-write

NAND : NAND Flash memory mode
bits : 4 - 3 (0 bit)
access : read-write

PAGE : NOR Flash memory page access mode
bits : 5 - 4 (0 bit)
access : read-write

RDY : control the external RDY function
bits : 6 - 5 (0 bit)
access : read-write

SHRTDOUT : select to which idle cycle the write data output is extended
bits : 7 - 6 (0 bit)
access : read-write

MPXMODE : select operation bus mode
bits : 8 - 7 (0 bit)
access : read-write

ALEINV : set up the polarity of the ALE signal
bits : 9 - 8 (0 bit)
access : read-write

MPXDOFF : select whether or not the address is output to the data lines in multiplex mode
bits : 11 - 10 (0 bit)
access : read-write

MPXCSOF : select a CS assertion from the start of accessing to the end of address output
bits : 12 - 11 (0 bit)
access : read-write

MOEXEUP : select how to set the MOEX width
bits : 13 - 12 (0 bit)
access : read-write


MODE4

Mode Register 4
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE4 MODE4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMODE

SDRAM Mode Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMODE SDMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDON PDON ROFF CASEL RASEL BASEL MSDCLKOFF

SDON : SDRAM ON
bits : 0 - -1 (0 bit)
access : read-write

PDON : Power Down ON
bits : 1 - 0 (0 bit)
access : read-write

ROFF : Refresh OFF
bits : 2 - 1 (0 bit)
access : read-write

CASEL : Column Address Select
bits : 4 - 4 (1 bit)
access : read-write

RASEL : Row Address Select
bits : 8 - 10 (3 bit)
access : read-write

BASEL : Bank Address Select
bits : 12 - 14 (3 bit)
access : read-write

MSDCLKOFF : MSDCLK OFF
bits : 16 - 15 (0 bit)
access : read-write


REFTIM

Refresh Timer Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REFTIM REFTIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFC NREF PREF

REFC : Refresh Count
bits : 0 - 14 (15 bit)
access : read-write

NREF : Number of Refresh
bits : 16 - 22 (7 bit)
access : read-write

PREF : Pre-Refresh
bits : 24 - 23 (0 bit)
access : read-write


PWRDWN

Power Down Count Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRDWN PWRDWN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDC

PDC : Power Down Count
bits : 0 - 14 (15 bit)
access : read-write


SDTIM

SDRAM Timing Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDTIM SDTIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL TRC TRP TRCD TRAS TREFC TDPL BOFF

CL : CAS Latency
bits : 0 - 0 (1 bit)
access : read-write

TRC : RAS Cycle time
bits : 4 - 6 (3 bit)
access : read-write

TRP : RAS Precharge time
bits : 8 - 10 (3 bit)
access : read-write

TRCD : RAS-CAS Delay
bits : 12 - 14 (3 bit)
access : read-write

TRAS : RAS active time
bits : 16 - 18 (3 bit)
access : read-write

TREFC : Refresh Cycle time
bits : 20 - 22 (3 bit)
access : read-write

TDPL : Data-in to Precharge Lead Time
bits : 24 - 24 (1 bit)
access : read-write

BOFF : Buffer readout bit
bits : 31 - 30 (0 bit)
access : read-write


SDCMD

SDRAM Command Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCMD SDCMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDAD SDWE SDCAS SDRAS SDCS SDCKE PEND

SDAD : SDRAM ADress
bits : 0 - 14 (15 bit)
access : read-write

SDWE : SDRAM Write Enable
bits : 16 - 15 (0 bit)
access : read-write

SDCAS : SDRAM CAS
bits : 17 - 16 (0 bit)
access : read-write

SDRAS : SDRAM RAS
bits : 18 - 17 (0 bit)
access : read-write

SDCS : SDRAM Chip Select
bits : 19 - 18 (0 bit)
access : read-write

SDCKE : SDRAM CKE
bits : 20 - 19 (0 bit)
access : read-write

PEND : Pend
bits : 31 - 30 (0 bit)
access : read-only


MODE5

Mode Register 5
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE5 MODE5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE6

Mode Register 6
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE6 MODE6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE7

Mode Register 7
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE7 MODE7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM0

Timing Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM0 TIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RACC RADC FRADC RIDLC WACC WADC WWEC WIDLC

RACC : Read Access Cycle
bits : 0 - 2 (3 bit)
access : read-write

RADC : Read Address Setup cycle
bits : 4 - 6 (3 bit)
access : read-write

FRADC : First Read Address Cycle
bits : 8 - 10 (3 bit)
access : read-write

RIDLC : Read Idle Cycle
bits : 12 - 14 (3 bit)
access : read-write

WACC : Write Access Cycle
bits : 16 - 18 (3 bit)
access : read-write

WADC : Write Address Setup cycle
bits : 20 - 22 (3 bit)
access : read-write

WWEC : Write Enable Cycle
bits : 24 - 26 (3 bit)
access : read-write

WIDLC : Write Idle Cycle
bits : 28 - 30 (3 bit)
access : read-write


MEMCERR

Memory Controller Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMCERR MEMCERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFER SDER SFION SDION

SFER : SRAM/Flash Error
bits : 0 - -1 (0 bit)
access : read-write

SDER : SDRAM Error
bits : 1 - 0 (0 bit)
access : read-write

SFION : SRAM/Flash error Interrupt ON
bits : 2 - 1 (0 bit)
access : read-write

SDION : SDRAM error Interrupt ON
bits : 3 - 2 (0 bit)
access : read-write


TIM1

Timing Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1 TIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM2

Timing Register 2
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM2 TIM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM3

Timing Register 3
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM3 TIM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM4

Timing Register 4
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4 TIM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DCLKR

Division Clock Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCLKR DCLKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDIV MCLKON

MDIV : MCLK Division Ratio Setup
bits : 0 - 2 (3 bit)
access : read-write

MCLKON : MCLK ON
bits : 4 - 3 (0 bit)
access : read-write


EST

Error Status Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EST EST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WERR

WERR : WERR
bits : 0 - -1 (0 bit)
access : read-only


WEAD

Write Error Address Register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WEAD WEAD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : ADDR
bits : 0 - 30 (31 bit)
access : read-only


ESCLR

Error Status Clear Register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ESCLR ESCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WERRCLR

WERRCLR : Write Error Clear
bits : 0 - -1 (0 bit)
access : write-only


AMODE

Access Mode Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMODE AMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAEN

WAEN : WAEN
bits : 0 - -1 (0 bit)
access : read-write


TIM5

Timing Register 5
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM5 TIM5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM6

Timing Register 6
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM6 TIM6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM7

Timing Register 7
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM7 TIM7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE1

Mode Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 MODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AREA0

Area Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREA0 AREA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR MASK

ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write

MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write


AREA1

Area Register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREA1 AREA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR MASK

ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write

MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write


AREA2

Area Register 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREA2 AREA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR MASK

ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write

MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write


AREA3

Area Register 3
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREA3 AREA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR MASK

ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write

MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write


AREA4

Area Register 4
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREA4 AREA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR MASK

ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write

MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write


AREA5

Area Register 5
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREA5 AREA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR MASK

ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write

MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write


AREA6

Area Register 6
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREA6 AREA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR MASK

ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write

MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write


AREA7

Area Register 7
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREA7 AREA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR MASK

ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write

MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write


ATIM0

ALE Timing Register 0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATIM0 ATIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALC ALES ALEW

ALC : Address Latch Cycle
bits : 0 - 2 (3 bit)
access : read-write

ALES : Address Latch Enable Setup cycle
bits : 4 - 6 (3 bit)
access : read-write

ALEW : Address Latch Enable Width
bits : 8 - 10 (3 bit)
access : read-write


ATIM1

ALE Timing Register 1
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATIM1 ATIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ATIM2

ALE Timing Register 2
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATIM2 ATIM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ATIM3

ALE Timing Register 3
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATIM3 ATIM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ATIM4

ALE Timing Register 4
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATIM4 ATIM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ATIM5

ALE Timing Register 5
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATIM5 ATIM5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ATIM6

ALE Timing Register 6
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATIM6 ATIM6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ATIM7

ALE Timing Register 7
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATIM7 ATIM7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE2

Mode Register 2
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 MODE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE3

Mode Register 3
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE3 MODE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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