\n
address_offset : 0x0 Bytes (0x0)
size : 0xB0 byte (0x0)
mem_usage : registers
protection : not protected
Descriptor top address Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request enable Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request enable Register 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request enable Register 2
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request enable Register 3
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request enable Register 4
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request enable Register 5
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request enable Register 6
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request enable Register 7
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt Register 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt Register 1
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt Register 2
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt Register 3
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware DES pointer Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : CHANNEL
bits : 0 - 6 (7 bit)
access : read-write
HWDESP : HWDESP
bits : 16 - 28 (13 bit)
access : read-write
Hardware transfer interrupt Register 4
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt Register 5
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt Register 6
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt Register 7
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt clear Register 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt clear Register 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt clear Register 2
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt clear Register 3
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt clear Register 4
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt clear Register 5
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt clear Register 6
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Hardware transfer interrupt clear Register 7
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask Register 0
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask Register 1
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask Register 2
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask Register 3
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Command Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask Register 4
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask Register 5
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask Register 6
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask Register 7
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration Register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWINTE : Software interrupt enable
bits : 0 - -1 (0 bit)
access : read-write
ERINTE : Error interrupt enable
bits : 1 - 0 (0 bit)
access : read-write
RBDIS : Read skip buffer disable
bits : 2 - 1 (0 bit)
access : read-write
ESTE : Error stop enable
bits : 3 - 2 (0 bit)
access : read-write
SWPR : Software transfer priority
bits : 4 - 5 (2 bit)
access : read-write
DMA request mask clear Register 0
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask clear Register 1
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask clear Register 2
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask clear Register 3
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Software trigger Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWDESP : Software DES pointer
bits : 0 - 12 (13 bit)
access : read-write
SWREQ : Software request
bits : 14 - 13 (0 bit)
access : read-only
SWST : Software status
bits : 15 - 14 (0 bit)
access : read-only
DMA request mask clear Register 4
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask clear Register 5
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask clear Register 6
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA request mask clear Register 7
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MONERS Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EST : Error status
bits : 0 - 1 (2 bit)
access : read-only
DER : Double error
bits : 3 - 2 (0 bit)
access : read-only
ESTOP : Error stop
bits : 4 - 3 (0 bit)
access : read-only
EHS : Error hardware software
bits : 6 - 5 (0 bit)
access : read-only
ECH : Error hardware channel
bits : 8 - 14 (7 bit)
access : read-only
EDESP : Error DES pointer
bits : 16 - 28 (13 bit)
access : read-only
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