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BT0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWM_PCSR

PPG_PRLL

RT_PCSR

PWM_STC

PPG_STC

RT_STC

PWC_STC

PWM_TMCR2

PPG_TMCR2

RT_TMCR2

PWC_TMCR2

PWM_PDUT

PPG_PRLH

PWC_DTBF

PWM_TMR

PPG_TMR

RT_TMR

PWM_TMCR

PPG_TMCR

RT_TMCR

PWC_TMCR


PWM_PCSR

PWM Cycle Set Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0

PWM_PCSR PWM_PCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PPG_PRLL

LOW Width Reload Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0

PPG_PRLL PPG_PRLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RT_PCSR

PWM Cycle Set Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0

RT_PCSR RT_PCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_STC

Status Control Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0

PWM_STC PWM_STC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UDIR DTIR TGIR UDIE DTIE TGIE

UDIR : Underflow interrupt request bit
bits : 0 - -1 (0 bit)
access : read-write

DTIR : Duty match interrupt request bit
bits : 1 - 0 (0 bit)
access : read-write

TGIR : Trigger interrupt request bit
bits : 2 - 1 (0 bit)
access : read-write

UDIE : Underflow interrupt request enable bit
bits : 4 - 3 (0 bit)
access : read-write

DTIE : Duty match interrupt request enable bit
bits : 5 - 4 (0 bit)
access : read-write

TGIE : Trigger interrupt request enable bit
bits : 6 - 5 (0 bit)
access : read-write


PPG_STC

Status Control Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0

PPG_STC PPG_STC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UDIR TGIR UDIE TGIE

UDIR : Underflow interrupt request bit
bits : 0 - -1 (0 bit)
access : read-write

TGIR : Trigger interrupt request bit
bits : 2 - 1 (0 bit)
access : read-write

UDIE : Underflow interrupt request enable bit
bits : 4 - 3 (0 bit)
access : read-write

TGIE : Trigger interrupt request enable bit
bits : 6 - 5 (0 bit)
access : read-write


RT_STC

Status Control Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0

RT_STC RT_STC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UDIR TGIR UDIE TGIE

UDIR : Underflow interrupt request bit
bits : 0 - -1 (0 bit)
access : read-write

TGIR : Trigger interrupt request bit
bits : 2 - 1 (0 bit)
access : read-write

UDIE : Underflow interrupt request enable bit
bits : 4 - 3 (0 bit)
access : read-write

TGIE : Trigger interrupt request enable bit
bits : 6 - 5 (0 bit)
access : read-write


PWC_STC

Status Control Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PWC
reset_Mask : 0x0

PWC_STC PWC_STC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVIR EDIR OVIE EDIE ERR

OVIR : Overflow interrupt request bit
bits : 0 - -1 (0 bit)
access : read-write

EDIR : Measurement completion interrupt request bit
bits : 2 - 1 (0 bit)
access : read-only

OVIE : Overflow interrupt request enable bit
bits : 4 - 3 (0 bit)
access : read-write

EDIE : Measurement completion interrupt request enable bit
bits : 6 - 5 (0 bit)
access : read-write

ERR : Error flag bit
bits : 7 - 6 (0 bit)
access : read-only


PWM_TMCR2

Timer Control Register 2
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0

PWM_TMCR2 PWM_TMCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKS3

CKS3 : Count clock selection bit
bits : 0 - -1 (0 bit)
access : read-write


PPG_TMCR2

Timer Control Register 2
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0

PPG_TMCR2 PPG_TMCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKS3

CKS3 : Count clock selection bit
bits : 0 - -1 (0 bit)
access : read-write


RT_TMCR2

Timer Control Register 2
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0

RT_TMCR2 RT_TMCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKS3 GATE

CKS3 : Count clock selection bit
bits : 0 - -1 (0 bit)
access : read-write

GATE : Gate Input Enable bit
bits : 7 - 6 (0 bit)
access : read-write


PWC_TMCR2

Timer Control Register 2
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PWC
reset_Mask : 0x0

PWC_TMCR2 PWC_TMCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKS3

CKS3 : Count clock selection bit
bits : 0 - -1 (0 bit)
access : read-write


PWM_PDUT

PWM Duty Set Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0

PWM_PDUT PWM_PDUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PPG_PRLH

HIGH Width Reload Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0

PPG_PRLH PPG_PRLH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWC_DTBF

Data Buffer Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : PWC
reset_Mask : 0x0

PWC_DTBF PWC_DTBF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_TMR

Timer Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0

PWM_TMR PWM_TMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PPG_TMR

Timer Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0

PPG_TMR PPG_TMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RT_TMR

Timer Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0

RT_TMR RT_TMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_TMCR

Timer Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0

PWM_TMCR PWM_TMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRG CTEN MDSE OSEL FMD EGS PMSK RTGEN CKS2_0

STRG : Software trigger bit
bits : 0 - -1 (0 bit)
access : read-write

CTEN : Count operation enable bit
bits : 1 - 0 (0 bit)
access : read-write

MDSE : Mode selection bit
bits : 2 - 1 (0 bit)
access : read-write

OSEL : Output polarity specification bit
bits : 3 - 2 (0 bit)
access : read-write

FMD : Timer function selection bits
bits : 4 - 5 (2 bit)
access : read-write

EGS : Trigger input edge selection bits
bits : 8 - 8 (1 bit)
access : read-write

PMSK : Pulse output mask bit
bits : 10 - 9 (0 bit)
access : read-write

RTGEN : Restart enable bit
bits : 11 - 10 (0 bit)
access : read-write

CKS2_0 : Count clock selection bit
bits : 12 - 13 (2 bit)
access : read-write


PPG_TMCR

Timer Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0

PPG_TMCR PPG_TMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRG CTEN MDSE OSEL FMD EGS PMSK RTGEN CKS2_0

STRG : Software trigger bit
bits : 0 - -1 (0 bit)
access : read-write

CTEN : Count operation enable bit
bits : 1 - 0 (0 bit)
access : read-write

MDSE : Mode selection bit
bits : 2 - 1 (0 bit)
access : read-write

OSEL : Output polarity specification bit
bits : 3 - 2 (0 bit)
access : read-write

FMD : Timer function selection bits
bits : 4 - 5 (2 bit)
access : read-write

EGS : Trigger input edge selection bits
bits : 8 - 8 (1 bit)
access : read-write

PMSK : Pulse output mask bit
bits : 10 - 9 (0 bit)
access : read-write

RTGEN : Restart enable bit
bits : 11 - 10 (0 bit)
access : read-write

CKS2_0 : Count clock selection bit
bits : 12 - 13 (2 bit)
access : read-write


RT_TMCR

Timer Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0

RT_TMCR RT_TMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRG CTEN MDSE OSEL FMD T32 EGS CKS2_0

STRG : Software trigger bit
bits : 0 - -1 (0 bit)
access : read-write

CTEN : Timer enable bit
bits : 1 - 0 (0 bit)
access : read-write

MDSE : Mode selection bit
bits : 2 - 1 (0 bit)
access : read-write

OSEL : Output polarity specification bit
bits : 3 - 2 (0 bit)
access : read-write

FMD : Timer function selection bits
bits : 4 - 5 (2 bit)
access : read-write

T32 : 32-bit timer selection bit
bits : 7 - 6 (0 bit)
access : read-write

EGS : Trigger input edge selection bits
bits : 8 - 8 (1 bit)
access : read-write

CKS2_0 : Count clock selection bit
bits : 12 - 13 (2 bit)
access : read-write


PWC_TMCR

Timer Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PWC
reset_Mask : 0x0

PWC_TMCR PWC_TMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTEN MDSE FMD T32 EGS CKS2_0

CTEN : Timer enable bit
bits : 1 - 0 (0 bit)
access : read-write

MDSE : Mode selection bit
bits : 2 - 1 (0 bit)
access : read-write

FMD : Timer function selection bits
bits : 4 - 5 (2 bit)
access : read-write

T32 : 32-bit timer selection bit
bits : 7 - 6 (0 bit)
access : read-write

EGS : Measurement edge selection bits
bits : 8 - 9 (2 bit)
access : read-write

CKS2_0 : Count clock selection bit
bits : 12 - 13 (2 bit)
access : read-write



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