HDMICEC0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x44 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x54 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x58 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x49 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x5C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x61 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x64 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

Registers

add a new register to this peripheral

TXCTRL

TXDATA

RCST

RCCR

RCDAHW

RCSHW

RCDBHW

RCADR2

RCADR1

RCDTHL

RCDTHH

RCDTLL

RCDTLH

RCCKD

RCRHW

RCRC

RCLE

RCLESW

RCLELW

TXSTS

SFREE


TXCTRL

Transmission Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCTRL TXCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TXEN START EOM ITSTEN IBREN

TXEN : Transmission operation enable bit
bits : 0 - -1 (0 bit)
access : read-write

START : START setting bit
bits : 2 - 1 (0 bit)
access : read-write

EOM : EOM setting bit
bits : 3 - 2 (0 bit)
access : read-write

ITSTEN : transmission status interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write

IBREN : Bus error detection interrupt enable bit
bits : 5 - 4 (0 bit)
access : read-write


TXDATA

Transmission Data Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXDATA TXDATA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TXDATA

TXDATA : Transmission Data
bits : 0 - 6 (7 bit)
access : read-write


RCST

Reception Interrupt Control Register
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCST RCST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF EOM ACK ST OVFSEL OVFIE ACKIE STIE

OVF : Counter overflow detection bit
bits : 0 - -1 (0 bit)
access : read-write

EOM : EOM detection bit
bits : 1 - 0 (0 bit)
access : read-write

ACK : ACK: ACK detection bit
bits : 2 - 1 (0 bit)
access : read-write

ST : Start bit detection bit
bits : 3 - 2 (0 bit)
access : read-write

OVFSEL : Counter overflow detection condition setting bit
bits : 4 - 3 (0 bit)
access : read-write

OVFIE : Counter overflow interrupt enable bit
bits : 5 - 4 (0 bit)
access : read-write

ACKIE : ACK interrupt enable bit
bits : 6 - 5 (0 bit)
access : read-write

STIE : Start bit interrupt enable bit
bits : 7 - 6 (0 bit)
access : read-write


RCCR

Reception Control Register
address_offset : 0x41 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCCR RCCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EN MOD ADRCE THSEL

EN : Operation enable bit
bits : 0 - -1 (0 bit)
access : read-write

MOD : Operation mode setting bits
bits : 1 - 1 (1 bit)
access : read-write

ADRCE : Address comparison enable bit
bits : 3 - 2 (0 bit)
access : read-write

THSEL : Threshold selection bit
bits : 7 - 6 (0 bit)
access : read-write


RCDAHW

H Width Setting Register A
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCDAHW RCDAHW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCDAHW

RCDAHW : H Width Setting A
bits : 0 - 6 (7 bit)
access : read-write


RCSHW

Start Bit H Width Setting Register
address_offset : 0x45 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCSHW RCSHW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCSHW

RCSHW : Start Bit H Width Setting
bits : 0 - 6 (7 bit)
access : read-write


RCDBHW

H Width Setting Register B
address_offset : 0x49 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCDBHW RCDBHW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCDBHW

RCDBHW : H Width Setting B
bits : 0 - 6 (7 bit)
access : read-write


RCADR2

Device Address Setting Register 2
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCADR2 RCADR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCADR2

RCADR2 : Device Address 2
bits : 0 - 3 (4 bit)
access : read-write


RCADR1

Device Address Setting Register 1
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCADR1 RCADR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCADR1

RCADR1 : Device Address 1
bits : 0 - 3 (4 bit)
access : read-write


RCDTHL

Data Save Register (High-Low)
address_offset : 0x50 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCDTHL RCDTHL read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCDTHL

RCDTHL : RCDTHL
bits : 0 - 6 (7 bit)
access : read-only


RCDTHH

Data Save Register (High-High)
address_offset : 0x51 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCDTHH RCDTHH read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCDTHH

RCDTHH : RCDTHH
bits : 0 - 6 (7 bit)
access : read-only


RCDTLL

Data Save Register (Low-Low)
address_offset : 0x54 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCDTLL RCDTLL read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCDTLL

RCDTLL : RCDTLL
bits : 0 - 6 (7 bit)
access : read-only


RCDTLH

Data Save Register (Low-High)
address_offset : 0x55 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCDTLH RCDTLH read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCDTLH

RCDTLH : RCDTLH
bits : 0 - 6 (7 bit)
access : read-only


RCCKD

Clock Division Setting Register
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCCKD RCCKD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKDIV CKSEL

CKDIV : Operating clock division setting bits
bits : 0 - 10 (11 bit)
access : read-write

CKSEL : Operating clock selection bit
bits : 12 - 11 (0 bit)
access : read-write


RCRHW

Repeat Code H Width Setting Register
address_offset : 0x5C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCRHW RCRHW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCRHW

RCRHW : Repeat code H width setting bits
bits : 0 - 6 (7 bit)
access : read-write


RCRC

Repeat Code Interrupt Control Register
address_offset : 0x5D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCRC RCRC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RC RCIE

RC : Repeat code detection flag bit
bits : 0 - -1 (0 bit)
access : read-write

RCIE : Repeat Code Interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write


RCLE

Data Bit Width Violation Control Register
address_offset : 0x61 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCLE RCLE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LES LEL EPE LESE LELE LESIE LELIE

LES : Minimum data bit width violation detection flag bit
bits : 0 - -1 (0 bit)
access : read-write

LEL : Maximum data bit width violation detection flag bit
bits : 1 - 0 (0 bit)
access : read-write

EPE : Error pulse output enable bit
bits : 3 - 2 (0 bit)
access : read-write

LESE : Minimum data bit width violation detection enable bit
bits : 4 - 3 (0 bit)
access : read-write

LELE : Maximum data bit width violation detection enable bit
bits : 5 - 4 (0 bit)
access : read-write

LESIE : Minimum data bit width violation interrupt enable bit
bits : 6 - 5 (0 bit)
access : read-write

LELIE : Maximum data bit width violation interrupt enable bit
bits : 7 - 6 (0 bit)
access : read-write


RCLESW

Minimum Data Bit Width Setting Register
address_offset : 0x64 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCLESW RCLESW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCLESW

RCLESW : Minimum data bit width setting bits
bits : 0 - 6 (7 bit)
access : read-write


RCLELW

Maximum Data Bit Width Setting Register
address_offset : 0x65 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCLELW RCLELW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCLELW

RCLELW : Maximum data bit width setting bits
bits : 0 - 6 (7 bit)
access : read-write


TXSTS

Transmission Status Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXSTS TXSTS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACKSV ITST IBR

ACKSV : ACK cycle value bit
bits : 0 - -1 (0 bit)
access : read-write

ITST : Transmission status interrupt request bit
bits : 4 - 3 (0 bit)
access : read-write

IBR : Bus error detection interrupt request bit
bits : 5 - 4 (0 bit)
access : read-write


SFREE

Signal Free Time Setting Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFREE SFREE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SFREE

SFREE : Signal free time setting bits
bits : 0 - 2 (3 bit)
access : read-write



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