\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x38 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3E Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x44 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x35 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x39 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3A Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3B Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x90 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xDC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xE0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xE4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xF0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xF4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xF8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Core Release Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DAY : Time Stamp Day
bits : 0 - 6 (7 bit)
access : read-only
MON : Time Stamp Month
bits : 8 - 14 (7 bit)
access : read-only
YEAR : Time Stamp Year
bits : 16 - 18 (3 bit)
access : read-only
SUBSTEP : Sub-step of Core Release
bits : 20 - 22 (3 bit)
access : read-only
STEP : Step of Core Release
bits : 24 - 26 (3 bit)
access : read-only
REL : Core Release
bits : 28 - 30 (3 bit)
access : read-only
Test Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBCK : Loop Back Mode
bits : 4 - 3 (0 bit)
access : read-write
TX : Control of Transmit Pin
bits : 5 - 5 (1 bit)
access : read-write
RX : Receive Pin
bits : 7 - 6 (0 bit)
access : read-write
TDCV : Transceiver Delay Compensation Value
bits : 8 - 12 (5 bit)
access : read-only
RAM Watchdog
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDC : Watchdog Configuration
bits : 0 - 6 (7 bit)
access : read-write
WDV : Watchdog Value
bits : 8 - 14 (7 bit)
access : read-only
CC Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initialization
bits : 0 - -1 (0 bit)
access : read-write
CCE : Configuration Change Enable
bits : 1 - 0 (0 bit)
access : read-write
ASM : Restricted Operation Mode
bits : 2 - 1 (0 bit)
access : read-write
CSA : Clock Stop Acknowledge
bits : 3 - 2 (0 bit)
access : read-only
CSR : Clock Stop Request
bits : 4 - 3 (0 bit)
access : read-write
MON : Bus Monitoring Mode
bits : 5 - 4 (0 bit)
access : read-write
DAR : Disable Automatic Retransmission
bits : 6 - 5 (0 bit)
access : read-write
TEST : Test Mode Enable
bits : 7 - 6 (0 bit)
access : read-write
CME : CAN Mode Enable
bits : 8 - 8 (1 bit)
access : read-write
CMR : CAN Mode Request
bits : 10 - 10 (1 bit)
access : read-write
FDO : CAN FD Operation
bits : 12 - 11 (0 bit)
access : read-only
FDBS : CAN FD Bit Rate Switching
bits : 13 - 12 (0 bit)
access : read-only
TXP : Transmit Pause
bits : 14 - 13 (0 bit)
access : read-write
Bit Timing and Prescaler Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SJW : (Re) Synchronization Jump Width
bits : 0 - 2 (3 bit)
access : read-write
TSEG2 : Time segment after sample point
bits : 4 - 6 (3 bit)
access : read-write
TSEG1 : Time segment before sample point
bits : 8 - 12 (5 bit)
access : read-write
BRP : Baud Rate Prescaler
bits : 16 - 24 (9 bit)
access : read-write
Timestamp Counter Configuration
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSS : Timestamp Select
bits : 0 - 0 (1 bit)
access : read-write
TCP : Timestamp Counter Prescaler
bits : 16 - 18 (3 bit)
access : read-write
CAN FD ECC Error Control Register
address_offset : 0x200 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEIE : Single-bit error factor interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write
DEIE : Double-bit error factor interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write
CEREN : ECC error response enable bit
bits : 2 - 1 (0 bit)
access : read-write
CEIV : ECC check disable bit
bits : 3 - 2 (0 bit)
access : read-write
CAN FD ECC Error Status Register
address_offset : 0x201 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEI : Single-bit error occurrence bit
bits : 0 - -1 (0 bit)
access : read-only
DEI : Double-bit error occurrence bit
bits : 1 - 0 (0 bit)
access : read-only
CAN FD ECC Single-bit Error Address Register
address_offset : 0x202 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRA : Single-bit error Message RAM address bits
bits : 0 - 14 (15 bit)
access : read-only
CAN FD ECC Error Status Clear Register
address_offset : 0x205 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEIC : Sngle-bit error clear bit
bits : 0 - -1 (0 bit)
access : write-only
DEIC : Double-bit error clear bit
bits : 1 - 0 (0 bit)
access : write-only
CAN FD ECC Double-bit Error Address Register
address_offset : 0x206 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DRA : Double-bit error Message RAM address bits
bits : 0 - 14 (15 bit)
access : read-only
Time Stamp Control Register
address_offset : 0x210 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CCLR : Counter clear bit
bits : 0 - -1 (0 bit)
access : write-only
Time Stamp Mode Register
address_offset : 0x212 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN : Counter enable bit
bits : 0 - -1 (0 bit)
access : read-write
Time Stamp Divider Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDIV : Counter clock division ratio setting bit
bits : 0 - 14 (15 bit)
access : read-write
Time Stamp Counter Data Register
address_offset : 0x218 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter value bits
bits : 0 - 14 (15 bit)
access : read-only
Time Stamp Compare Clear Register
address_offset : 0x21A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : Compare clear setting bits
bits : 0 - 14 (15 bit)
access : read-write
Timestamp Counter Value
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSC : Timestamp Counter
bits : 0 - 14 (15 bit)
access : read-write
Timeout Counter Configuration
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETOC : Enable Timeout Counter
bits : 0 - -1 (0 bit)
access : read-write
TOS : Timeout Select
bits : 1 - 1 (1 bit)
access : read-write
TOP : Timeout Period
bits : 16 - 30 (15 bit)
access : read-write
Timeout Counter Value
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC : Timeout Counter
bits : 0 - 14 (15 bit)
access : read-write
Endian Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ETV : Endianness Test Value
bits : 0 - 30 (31 bit)
access : read-only
Error Counter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEC : Transmit Error Counter
bits : 0 - 6 (7 bit)
access : read-only
REC : Receive Error Counter
bits : 8 - 13 (6 bit)
access : read-only
RP : Receive Error Passive
bits : 15 - 14 (0 bit)
access : read-only
CEL : CAN Error Logging
bits : 16 - 22 (7 bit)
access : read-only
Protocol Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LEC : Last Error Code
bits : 0 - 1 (2 bit)
access : read-only
ACT : Activity
bits : 3 - 3 (1 bit)
access : read-only
EP : Error Passive
bits : 5 - 4 (0 bit)
access : read-only
EW : Warning Status
bits : 6 - 5 (0 bit)
access : read-only
BO : Bus_Off Status
bits : 7 - 6 (0 bit)
access : read-only
FLEC : Fast Last Error Code
bits : 8 - 9 (2 bit)
access : read-only
RESI : ESI flag of last received CAN FD Message
bits : 11 - 10 (0 bit)
access : read-only
RBRS : BRS flag of last received CAN FD Message
bits : 12 - 11 (0 bit)
access : read-only
REDL : Received a CAN FD Message
bits : 13 - 12 (0 bit)
access : read-only
Interrupt Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0N : Rx FIFO 0 New Message
bits : 0 - -1 (0 bit)
access : read-write
RF0W : Rx FIFO 0 Watermark Reached
bits : 1 - 0 (0 bit)
access : read-write
RF0F : Rx FIFO 0 Full
bits : 2 - 1 (0 bit)
access : read-write
RF0L : Rx FIFO 0 Message Lost
bits : 3 - 2 (0 bit)
access : read-write
RF1N : Rx FIFO 1 New Message
bits : 4 - 3 (0 bit)
access : read-write
RF1W : Rx FIFO 1 Watermark Reached
bits : 5 - 4 (0 bit)
access : read-write
RF1F : Rx FIFO 1 Full
bits : 6 - 5 (0 bit)
access : read-write
RF1L : Rx FIFO 1 Message Lost
bits : 7 - 6 (0 bit)
access : read-write
HPM : High Priority Message
bits : 8 - 7 (0 bit)
access : read-write
TC : Transmission Completed
bits : 9 - 8 (0 bit)
access : read-write
TCF : Transmission Cancellation Finished
bits : 10 - 9 (0 bit)
access : read-write
TFE : Tx FIFO Empty
bits : 11 - 10 (0 bit)
access : read-write
TEFN : Tx Event FIFO New Entry
bits : 12 - 11 (0 bit)
access : read-write
TEFW : Tx Event FIFO Watermark Reached
bits : 13 - 12 (0 bit)
access : read-write
TEFF : Tx Event FIFO Full
bits : 14 - 13 (0 bit)
access : read-write
TEFL : Tx Event FIFO Element Lost
bits : 15 - 14 (0 bit)
access : read-write
TSW : Timestamp Wraparound
bits : 16 - 15 (0 bit)
access : read-write
MRAF : Message RAM Access Failure
bits : 17 - 16 (0 bit)
access : read-write
TOO : Timeout Occurred
bits : 18 - 17 (0 bit)
access : read-write
DRX : Message stored to Dedicated Rx Buffer
bits : 19 - 18 (0 bit)
access : read-write
BEC : Bit Error Corrected
bits : 20 - 19 (0 bit)
access : read-write
BEU : Bit Error Uncorrected
bits : 21 - 20 (0 bit)
access : read-write
ELO : Error Logging Overflow
bits : 22 - 21 (0 bit)
access : read-write
EP : Error Passive
bits : 23 - 22 (0 bit)
access : read-write
EW : Warning Status
bits : 24 - 23 (0 bit)
access : read-write
BO : Bus_Off Status
bits : 25 - 24 (0 bit)
access : read-write
WDI : Watchdog Interrupt
bits : 26 - 25 (0 bit)
access : read-write
CRCE : CRC Error
bits : 27 - 26 (0 bit)
access : read-write
BE : Bit Error
bits : 28 - 27 (0 bit)
access : read-write
ACKE : Acknowledge Error
bits : 29 - 28 (0 bit)
access : read-write
FOE : Format Error
bits : 30 - 29 (0 bit)
access : read-write
STE : Stuff Error
bits : 31 - 30 (0 bit)
access : read-write
Interrupt Enable
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NE : Rx FIFO 0 New Message Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
RF0WE : Rx FIFO 0 Watermark Reached Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
RF0FE : Rx FIFO 0 Full Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
RF0LE : Rx FIFO 0 Message Lost Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
RF1NE : Rx FIFO 1 New Message Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
RF1WE : Rx FIFO 1 Watermark Reached Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
RF1FE : Rx FIFO 1 Full Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
RF1LE : Rx FIFO 1 Message Lost Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
HPME : High Priority Message Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
TCE : Transmission Completed Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
TCFE : Transmission Cancellation Finished Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
TFEE : Tx FIFO Empty Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
TEFNE : Tx Event FIFO New Entry Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
TEFWE : Tx Event FIFO Watermark Reached Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write
TEFFE : Tx Event FIFO Full Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
TEFLE : Tx Event FIFO Element Lost Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
TSWE : Timestamp Wraparound Interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
MRAFE : Message RAM Access Failure Interrupt Enable
bits : 17 - 16 (0 bit)
access : read-write
TOOE : Timeout Occurred Interrupt Enable
bits : 18 - 17 (0 bit)
access : read-write
DRXE : Message stored to Dedicated Rx Buffer Interrupt Enable
bits : 19 - 18 (0 bit)
access : read-write
BECE : Bit Error Corrected Interrupt Enable
bits : 20 - 19 (0 bit)
access : read-write
BEUE : Bit Error Uncorrected Interrupt Enable
bits : 21 - 20 (0 bit)
access : read-write
ELOE : Error Logging Overflow Interrupt Enable
bits : 22 - 21 (0 bit)
access : read-write
EPE : Error Passive Interrupt Enable
bits : 23 - 22 (0 bit)
access : read-write
EWE : Warning Status Interrupt Enable
bits : 24 - 23 (0 bit)
access : read-write
BOE : Bus_Off Status Interrupt Enable
bits : 25 - 24 (0 bit)
access : read-write
WDIE : Watchdog Interrupt Interrupt Enable
bits : 26 - 25 (0 bit)
access : read-write
CRCEE : CRC Error Interrupt Enable
bits : 27 - 26 (0 bit)
access : read-write
BEE : Bit Error Interrupt Enable
bits : 28 - 27 (0 bit)
access : read-write
ACKEE : Acknowledge Error Interrupt Enable
bits : 29 - 28 (0 bit)
access : read-write
FOEE : Format Error Interrupt Enable
bits : 30 - 29 (0 bit)
access : read-write
STEE : Stuff Error Interrupt Enable
bits : 31 - 30 (0 bit)
access : read-write
Interrupt Line Select
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NL : Rx FIFO 0 New Message Interrupt Line
bits : 0 - -1 (0 bit)
access : read-write
RF0WL : Rx FIFO 0 Watermark Reached Interrupt Line
bits : 1 - 0 (0 bit)
access : read-write
RF0FL : Rx FIFO 0 Full Interrupt Line
bits : 2 - 1 (0 bit)
access : read-write
RF0LL : Rx FIFO 0 Message Lost Interrupt Line
bits : 3 - 2 (0 bit)
access : read-write
RF1NL : Rx FIFO 1 New Message Interrupt Line
bits : 4 - 3 (0 bit)
access : read-write
RF1WL : Rx FIFO 1 Watermark Reached Interrupt Line
bits : 5 - 4 (0 bit)
access : read-write
RF1FL : Rx FIFO 1 Full Interrupt Line
bits : 6 - 5 (0 bit)
access : read-write
RF1LL : Rx FIFO 1 Message Lost Interrupt Line
bits : 7 - 6 (0 bit)
access : read-write
HPML : High Priority Message Interrupt Line
bits : 8 - 7 (0 bit)
access : read-write
TCL : Transmission Completed Interrupt Line
bits : 9 - 8 (0 bit)
access : read-write
TCFL : Transmission Cancellation Finished Interrupt Line
bits : 10 - 9 (0 bit)
access : read-write
TFEL : Tx FIFO Empty Interrupt Line
bits : 11 - 10 (0 bit)
access : read-write
TEFNL : Tx Event FIFO New Entry Interrupt Line
bits : 12 - 11 (0 bit)
access : read-write
TEFWL : Tx Event FIFO Watermark Reached Interrupt Line
bits : 13 - 12 (0 bit)
access : read-write
TEFFL : Tx Event FIFO Full Interrupt Line
bits : 14 - 13 (0 bit)
access : read-write
TEFLL : Tx Event FIFO Element Lost Interrupt Line
bits : 15 - 14 (0 bit)
access : read-write
TSWL : Timestamp Wraparound Interrupt Line
bits : 16 - 15 (0 bit)
access : read-write
MRAFL : Message RAM Access Failure Interrupt Line
bits : 17 - 16 (0 bit)
access : read-write
TOOL : Timeout Occurred Interrupt Line
bits : 18 - 17 (0 bit)
access : read-write
DRXL : Message stored to Dedicated Rx Buffer Interrupt Line
bits : 19 - 18 (0 bit)
access : read-write
BECL : Bit Error Corrected Interrupt Line
bits : 20 - 19 (0 bit)
access : read-write
BEUL : Bit Error Uncorrected Interrupt Line
bits : 21 - 20 (0 bit)
access : read-write
ELOL : Error Logging Overflow Interrupt Line
bits : 22 - 21 (0 bit)
access : read-write
EPL : Error Passive Interrupt Line
bits : 23 - 22 (0 bit)
access : read-write
EWL : Warning Status Interrupt Line
bits : 24 - 23 (0 bit)
access : read-write
BOL : Bus_Off Status Interrupt Line
bits : 25 - 24 (0 bit)
access : read-write
WDIL : Watchdog Interrupt Interrupt Line
bits : 26 - 25 (0 bit)
access : read-write
CRCEL : CRC Error Interrupt Line
bits : 27 - 26 (0 bit)
access : read-write
BEL : Bit Error Interrupt Line
bits : 28 - 27 (0 bit)
access : read-write
ACKEL : Acknowledge Error Interrupt Line
bits : 29 - 28 (0 bit)
access : read-write
FOEL : Format Error Interrupt Line
bits : 30 - 29 (0 bit)
access : read-write
STEL : Stuff Error Interrupt Line
bits : 31 - 30 (0 bit)
access : read-write
Interrupt Line Enable
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EINT0 : Enable Interrupt Line 0
bits : 0 - -1 (0 bit)
access : read-write
EINT1 : Enable Interrupt Line 1
bits : 1 - 0 (0 bit)
access : read-write
Global Filter Configuration
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRFE : Reject Remote Frames Extended
bits : 0 - -1 (0 bit)
access : read-write
RRFS : Reject Remote Frames Standard
bits : 1 - 0 (0 bit)
access : read-write
ANFE : Accept Non-matching Frames Extended
bits : 2 - 2 (1 bit)
access : read-write
ANFS : Accept Non-matching Frames Standard
bits : 4 - 4 (1 bit)
access : read-write
Standard ID Filter Configuration
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLSSA : Filter List Standard Start Address
bits : 2 - 14 (13 bit)
access : read-write
LSS : List Size Standard
bits : 16 - 22 (7 bit)
access : read-write
Extended ID Filter Configuration
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLESA : Filter List Extended Start Address
bits : 2 - 14 (13 bit)
access : read-write
LSE : List Size Extended
bits : 16 - 21 (6 bit)
access : read-write
Extended ID AND Mask
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIDM : Extended ID Mask
bits : 0 - 27 (28 bit)
access : read-write
High Priority Message Status
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIDX : Buffer Index
bits : 0 - 4 (5 bit)
access : read-only
MSI : Message Storage Indicator
bits : 6 - 6 (1 bit)
access : read-only
FIDX : Filter Index
bits : 8 - 13 (6 bit)
access : read-only
FLST : Filter List
bits : 15 - 14 (0 bit)
access : read-only
New Data 1
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ND0 : New Data flag of Rx Buffer 0
bits : 0 - -1 (0 bit)
access : read-write
ND1 : New Data flag of Rx Buffer 1
bits : 1 - 0 (0 bit)
access : read-write
ND2 : New Data flag of Rx Buffer 2
bits : 2 - 1 (0 bit)
access : read-write
ND3 : New Data flag of Rx Buffer 3
bits : 3 - 2 (0 bit)
access : read-write
ND4 : New Data flag of Rx Buffer 4
bits : 4 - 3 (0 bit)
access : read-write
ND5 : New Data flag of Rx Buffer 5
bits : 5 - 4 (0 bit)
access : read-write
ND6 : New Data flag of Rx Buffer 6
bits : 6 - 5 (0 bit)
access : read-write
ND7 : New Data flag of Rx Buffer 7
bits : 7 - 6 (0 bit)
access : read-write
ND8 : New Data flag of Rx Buffer 8
bits : 8 - 7 (0 bit)
access : read-write
ND9 : New Data flag of Rx Buffer 9
bits : 9 - 8 (0 bit)
access : read-write
ND10 : New Data flag of Rx Buffer 10
bits : 10 - 9 (0 bit)
access : read-write
ND11 : New Data flag of Rx Buffer 11
bits : 11 - 10 (0 bit)
access : read-write
ND12 : New Data flag of Rx Buffer 12
bits : 12 - 11 (0 bit)
access : read-write
ND13 : New Data flag of Rx Buffer 13
bits : 13 - 12 (0 bit)
access : read-write
ND14 : New Data flag of Rx Buffer 14
bits : 14 - 13 (0 bit)
access : read-write
ND15 : New Data flag of Rx Buffer 15
bits : 15 - 14 (0 bit)
access : read-write
ND16 : New Data flag of Rx Buffer 16
bits : 16 - 15 (0 bit)
access : read-write
ND17 : New Data flag of Rx Buffer 17
bits : 17 - 16 (0 bit)
access : read-write
ND18 : New Data flag of Rx Buffer 18
bits : 18 - 17 (0 bit)
access : read-write
ND19 : New Data flag of Rx Buffer 19
bits : 19 - 18 (0 bit)
access : read-write
ND20 : New Data flag of Rx Buffer 20
bits : 20 - 19 (0 bit)
access : read-write
ND21 : New Data flag of Rx Buffer 21
bits : 21 - 20 (0 bit)
access : read-write
ND22 : New Data flag of Rx Buffer 22
bits : 22 - 21 (0 bit)
access : read-write
ND23 : New Data flag of Rx Buffer 23
bits : 23 - 22 (0 bit)
access : read-write
ND24 : New Data flag of Rx Buffer 24
bits : 24 - 23 (0 bit)
access : read-write
ND25 : New Data flag of Rx Buffer 25
bits : 25 - 24 (0 bit)
access : read-write
ND26 : New Data flag of Rx Buffer 26
bits : 26 - 25 (0 bit)
access : read-write
ND27 : New Data flag of Rx Buffer 27
bits : 27 - 26 (0 bit)
access : read-write
ND28 : New Data flag of Rx Buffer 28
bits : 28 - 27 (0 bit)
access : read-write
ND29 : New Data flag of Rx Buffer 29
bits : 29 - 28 (0 bit)
access : read-write
ND30 : New Data flag of Rx Buffer 30
bits : 30 - 29 (0 bit)
access : read-write
ND31 : New Data flag of Rx Buffer 31
bits : 31 - 30 (0 bit)
access : read-write
New Data 2
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ND32 : New Data flag of Rx Buffer 32
bits : 0 - -1 (0 bit)
access : read-write
ND33 : New Data flag of Rx Buffer 33
bits : 1 - 0 (0 bit)
access : read-write
ND34 : New Data flag of Rx Buffer 34
bits : 2 - 1 (0 bit)
access : read-write
ND35 : New Data flag of Rx Buffer 35
bits : 3 - 2 (0 bit)
access : read-write
ND36 : New Data flag of Rx Buffer 36
bits : 4 - 3 (0 bit)
access : read-write
ND37 : New Data flag of Rx Buffer 37
bits : 5 - 4 (0 bit)
access : read-write
ND38 : New Data flag of Rx Buffer 38
bits : 6 - 5 (0 bit)
access : read-write
ND39 : New Data flag of Rx Buffer 39
bits : 7 - 6 (0 bit)
access : read-write
ND40 : New Data flag of Rx Buffer 40
bits : 8 - 7 (0 bit)
access : read-write
ND41 : New Data flag of Rx Buffer 41
bits : 9 - 8 (0 bit)
access : read-write
ND42 : New Data flag of Rx Buffer 42
bits : 10 - 9 (0 bit)
access : read-write
ND43 : New Data flag of Rx Buffer 43
bits : 11 - 10 (0 bit)
access : read-write
ND44 : New Data flag of Rx Buffer 44
bits : 12 - 11 (0 bit)
access : read-write
ND45 : New Data flag of Rx Buffer 45
bits : 13 - 12 (0 bit)
access : read-write
ND46 : New Data flag of Rx Buffer 46
bits : 14 - 13 (0 bit)
access : read-write
ND47 : New Data flag of Rx Buffer 47
bits : 15 - 14 (0 bit)
access : read-write
ND48 : New Data flag of Rx Buffer 48
bits : 16 - 15 (0 bit)
access : read-write
ND49 : New Data flag of Rx Buffer 49
bits : 17 - 16 (0 bit)
access : read-write
ND50 : New Data flag of Rx Buffer 50
bits : 18 - 17 (0 bit)
access : read-write
ND51 : New Data flag of Rx Buffer 51
bits : 19 - 18 (0 bit)
access : read-write
ND52 : New Data flag of Rx Buffer 52
bits : 20 - 19 (0 bit)
access : read-write
ND53 : New Data flag of Rx Buffer 53
bits : 21 - 20 (0 bit)
access : read-write
ND54 : New Data flag of Rx Buffer 54
bits : 22 - 21 (0 bit)
access : read-write
ND55 : New Data flag of Rx Buffer 55
bits : 23 - 22 (0 bit)
access : read-write
ND56 : New Data flag of Rx Buffer 56
bits : 24 - 23 (0 bit)
access : read-write
ND57 : New Data flag of Rx Buffer 57
bits : 25 - 24 (0 bit)
access : read-write
ND58 : New Data flag of Rx Buffer 58
bits : 26 - 25 (0 bit)
access : read-write
ND59 : New Data flag of Rx Buffer 59
bits : 27 - 26 (0 bit)
access : read-write
ND60 : New Data flag of Rx Buffer 60
bits : 28 - 27 (0 bit)
access : read-write
ND61 : New Data flag of Rx Buffer 61
bits : 29 - 28 (0 bit)
access : read-write
ND62 : New Data flag of Rx Buffer 62
bits : 30 - 29 (0 bit)
access : read-write
ND63 : New Data flag of Rx Buffer 63
bits : 31 - 30 (0 bit)
access : read-write
Rx FIFO 0 Configuration
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0SA : Rx FIFO 0 Start Address
bits : 2 - 14 (13 bit)
access : read-write
F0S : Rx FIFO 0 Size
bits : 16 - 21 (6 bit)
access : read-write
F0WM : Rx FIFO 0 Watermark
bits : 24 - 29 (6 bit)
access : read-write
F0OM : FIFO 0 Operation Mode
bits : 31 - 30 (0 bit)
access : read-write
Rx FIFO 0 Status
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F0FL : Rx FIFO 0 Fill Level
bits : 0 - 5 (6 bit)
access : read-only
F0GI : Rx FIFO 0 Get Index
bits : 8 - 12 (5 bit)
access : read-only
F0PI : Rx FIFO 0 Put Index
bits : 16 - 20 (5 bit)
access : read-only
F0F : Rx FIFO 0 Full
bits : 24 - 23 (0 bit)
access : read-only
RF0L : Rx FIFO 0 Message Lost
bits : 25 - 24 (0 bit)
access : read-only
Rx FIFO 0 Acknowledge
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0AI : Rx FIFO 0 Acknowledge Index
bits : 0 - 4 (5 bit)
access : read-write
Rx Buffer Configuration
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBSA : 2
bits : 2 - 14 (13 bit)
access : read-write
Rx FIFO 1 Configuration
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1SA : Rx FIFO 1 Start Address
bits : 2 - 14 (13 bit)
access : read-write
F1S : Rx FIFO 1 Size
bits : 16 - 21 (6 bit)
access : read-write
F1WM : Rx FIFO 1 Watermark
bits : 24 - 29 (6 bit)
access : read-write
F1OM : FIFO 1 Operation Mode
bits : 31 - 30 (0 bit)
access : read-write
Rx FIFO 1 Status
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F1FL : Rx FIFO 1 Fill Level
bits : 0 - 5 (6 bit)
access : read-only
F1GI : Rx FIFO 1 Get Index
bits : 8 - 12 (5 bit)
access : read-only
F1PI : Rx FIFO 1 Put Index
bits : 16 - 20 (5 bit)
access : read-only
F1F : Rx FIFO 1 Full
bits : 24 - 23 (0 bit)
access : read-only
RF1L : FIFO 1 Message Lost
bits : 25 - 24 (0 bit)
access : read-only
DMS : Debug Message Status
bits : 30 - 30 (1 bit)
access : read-only
Rx FIFO 1 Acknowledge
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1AI : Rx FIFO 1 Acknowledge Index
bits : 0 - 4 (5 bit)
access : read-write
Rx Buffer/FIFO Element Size Configuration
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DS : Rx FIFO 0 Data Field Size
bits : 0 - 1 (2 bit)
access : read-write
F1DS : Rx FIFO 1 Data Field Size
bits : 4 - 5 (2 bit)
access : read-write
RBDS : Rx Buffer Data Field Size
bits : 8 - 9 (2 bit)
access : read-write
Fast Bit Timing and Prescaler Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSJW : Fast (Re) Synchronization Jump Width
bits : 0 - 0 (1 bit)
access : read-write
FTSEG2 : Fast time segment after sample point
bits : 4 - 5 (2 bit)
access : read-write
FTSEG1 : Fast time segment before sample point
bits : 8 - 10 (3 bit)
access : read-write
FBRP : Fast Baud Rate Prescaler
bits : 16 - 19 (4 bit)
access : read-write
TDC : Transceiver Delay Compensation
bits : 23 - 22 (0 bit)
access : read-write
TDCO : Transceiver Delay Compensation Offset
bits : 24 - 27 (4 bit)
access : read-write
Tx Buffer Configuration
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBSA : Tx Buffers Start Address
bits : 2 - 14 (13 bit)
access : read-write
NDTB : Number of Dedicated Transmit Buffers
bits : 16 - 20 (5 bit)
access : read-write
TFQS : Transmit FIFO/Queue Size
bits : 24 - 28 (5 bit)
access : read-write
TFQM : Tx FIFO/Queue Mode
bits : 30 - 29 (0 bit)
access : read-write
Tx FIFO/Queue Status
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFFL : Tx FIFO Free Level
bits : 0 - 4 (5 bit)
access : read-only
TFGI : Tx FIFO Get Index
bits : 8 - 11 (4 bit)
access : read-only
TFQPI : Tx FIFO/Queue Put Index
bits : 16 - 19 (4 bit)
access : read-only
TFQF : Tx FIFO/Queue Full
bits : 21 - 20 (0 bit)
access : read-only
Tx Buffer Element Size Configuration
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TBDS : Tx Buffer Data Field Size
bits : 0 - 1 (2 bit)
access : read-write
Tx Buffer Request Pending
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TRP0 : Transmission Request Pending of Tx Buffer 0
bits : 0 - -1 (0 bit)
access : read-only
TRP1 : Transmission Request Pending of Tx Buffer 1
bits : 1 - 0 (0 bit)
access : read-only
TRP2 : Transmission Request Pending of Tx Buffer 2
bits : 2 - 1 (0 bit)
access : read-only
TRP3 : Transmission Request Pending of Tx Buffer 3
bits : 3 - 2 (0 bit)
access : read-only
TRP4 : Transmission Request Pending of Tx Buffer 4
bits : 4 - 3 (0 bit)
access : read-only
TRP5 : Transmission Request Pending of Tx Buffer 5
bits : 5 - 4 (0 bit)
access : read-only
TRP6 : Transmission Request Pending of Tx Buffer 6
bits : 6 - 5 (0 bit)
access : read-only
TRP7 : Transmission Request Pending of Tx Buffer 7
bits : 7 - 6 (0 bit)
access : read-only
TRP8 : Transmission Request Pending of Tx Buffer 8
bits : 8 - 7 (0 bit)
access : read-only
TRP9 : Transmission Request Pending of Tx Buffer 9
bits : 9 - 8 (0 bit)
access : read-only
TRP10 : Transmission Request Pending of Tx Buffer 10
bits : 10 - 9 (0 bit)
access : read-only
TRP11 : Transmission Request Pending of Tx Buffer 11
bits : 11 - 10 (0 bit)
access : read-only
TRP12 : Transmission Request Pending of Tx Buffer 12
bits : 12 - 11 (0 bit)
access : read-only
TRP13 : Transmission Request Pending of Tx Buffer 13
bits : 13 - 12 (0 bit)
access : read-only
TRP14 : Transmission Request Pending of Tx Buffer 14
bits : 14 - 13 (0 bit)
access : read-only
TRP15 : Transmission Request Pending of Tx Buffer 15
bits : 15 - 14 (0 bit)
access : read-only
TRP16 : Transmission Request Pending of Tx Buffer 16
bits : 16 - 15 (0 bit)
access : read-only
TRP17 : Transmission Request Pending of Tx Buffer 17
bits : 17 - 16 (0 bit)
access : read-only
TRP18 : Transmission Request Pending of Tx Buffer 18
bits : 18 - 17 (0 bit)
access : read-only
TRP19 : Transmission Request Pending of Tx Buffer 19
bits : 19 - 18 (0 bit)
access : read-only
TRP20 : Transmission Request Pending of Tx Buffer 20
bits : 20 - 19 (0 bit)
access : read-only
TRP21 : Transmission Request Pending of Tx Buffer 21
bits : 21 - 20 (0 bit)
access : read-only
TRP22 : Transmission Request Pending of Tx Buffer 22
bits : 22 - 21 (0 bit)
access : read-only
TRP23 : Transmission Request Pending of Tx Buffer 23
bits : 23 - 22 (0 bit)
access : read-only
TRP24 : Transmission Request Pending of Tx Buffer 24
bits : 24 - 23 (0 bit)
access : read-only
TRP25 : Transmission Request Pending of Tx Buffer 25
bits : 25 - 24 (0 bit)
access : read-only
TRP26 : Transmission Request Pending of Tx Buffer 26
bits : 26 - 25 (0 bit)
access : read-only
TRP27 : Transmission Request Pending of Tx Buffer 27
bits : 27 - 26 (0 bit)
access : read-only
TRP28 : Transmission Request Pending of Tx Buffer 28
bits : 28 - 27 (0 bit)
access : read-only
TRP29 : Transmission Request Pending of Tx Buffer 29
bits : 29 - 28 (0 bit)
access : read-only
TRP30 : Transmission Request Pending of Tx Buffer 30
bits : 30 - 29 (0 bit)
access : read-only
TRP31 : Transmission Request Pending of Tx Buffer 31
bits : 31 - 30 (0 bit)
access : read-only
Tx Buffer Add Request
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AR0 : Add Request of Tx Buffer 0
bits : 0 - -1 (0 bit)
access : read-write
AR1 : Add Request of Tx Buffer 1
bits : 1 - 0 (0 bit)
access : read-write
AR2 : Add Request of Tx Buffer 2
bits : 2 - 1 (0 bit)
access : read-write
AR3 : Add Request of Tx Buffer 3
bits : 3 - 2 (0 bit)
access : read-write
AR4 : Add Request of Tx Buffer 4
bits : 4 - 3 (0 bit)
access : read-write
AR5 : Add Request of Tx Buffer 5
bits : 5 - 4 (0 bit)
access : read-write
AR6 : Add Request of Tx Buffer 6
bits : 6 - 5 (0 bit)
access : read-write
AR7 : Add Request of Tx Buffer 7
bits : 7 - 6 (0 bit)
access : read-write
AR8 : Add Request of Tx Buffer 8
bits : 8 - 7 (0 bit)
access : read-write
AR9 : Add Request of Tx Buffer 9
bits : 9 - 8 (0 bit)
access : read-write
AR10 : Add Request of Tx Buffer 10
bits : 10 - 9 (0 bit)
access : read-write
AR11 : Add Request of Tx Buffer 11
bits : 11 - 10 (0 bit)
access : read-write
AR12 : Add Request of Tx Buffer 12
bits : 12 - 11 (0 bit)
access : read-write
AR13 : Add Request of Tx Buffer 13
bits : 13 - 12 (0 bit)
access : read-write
AR14 : Add Request of Tx Buffer 14
bits : 14 - 13 (0 bit)
access : read-write
AR15 : Add Request of Tx Buffer 15
bits : 15 - 14 (0 bit)
access : read-write
AR16 : Add Request of Tx Buffer 16
bits : 16 - 15 (0 bit)
access : read-write
AR17 : Add Request of Tx Buffer 17
bits : 17 - 16 (0 bit)
access : read-write
AR18 : Add Request of Tx Buffer 18
bits : 18 - 17 (0 bit)
access : read-write
AR19 : Add Request of Tx Buffer 19
bits : 19 - 18 (0 bit)
access : read-write
AR20 : Add Request of Tx Buffer 20
bits : 20 - 19 (0 bit)
access : read-write
AR21 : Add Request of Tx Buffer 21
bits : 21 - 20 (0 bit)
access : read-write
AR22 : Add Request of Tx Buffer 22
bits : 22 - 21 (0 bit)
access : read-write
AR23 : Add Request of Tx Buffer 23
bits : 23 - 22 (0 bit)
access : read-write
AR24 : Add Request of Tx Buffer 24
bits : 24 - 23 (0 bit)
access : read-write
AR25 : Add Request of Tx Buffer 25
bits : 25 - 24 (0 bit)
access : read-write
AR26 : Add Request of Tx Buffer 26
bits : 26 - 25 (0 bit)
access : read-write
AR27 : Add Request of Tx Buffer 27
bits : 27 - 26 (0 bit)
access : read-write
AR28 : Add Request of Tx Buffer 28
bits : 28 - 27 (0 bit)
access : read-write
AR29 : Add Request of Tx Buffer 29
bits : 29 - 28 (0 bit)
access : read-write
AR30 : Add Request of Tx Buffer 30
bits : 30 - 29 (0 bit)
access : read-write
AR31 : Add Request of Tx Buffer 31
bits : 31 - 30 (0 bit)
access : read-write
Tx Buffer Cancellation Request
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CR0 : Cancellation Request of Tx Buffer 0
bits : 0 - -1 (0 bit)
access : read-write
CR1 : Cancellation Request of Tx Buffer 1
bits : 1 - 0 (0 bit)
access : read-write
CR2 : Cancellation Request of Tx Buffer 2
bits : 2 - 1 (0 bit)
access : read-write
CR3 : Cancellation Request of Tx Buffer 3
bits : 3 - 2 (0 bit)
access : read-write
CR4 : Cancellation Request of Tx Buffer 4
bits : 4 - 3 (0 bit)
access : read-write
CR5 : Cancellation Request of Tx Buffer 5
bits : 5 - 4 (0 bit)
access : read-write
CR6 : Cancellation Request of Tx Buffer 6
bits : 6 - 5 (0 bit)
access : read-write
CR7 : Cancellation Request of Tx Buffer 7
bits : 7 - 6 (0 bit)
access : read-write
CR8 : Cancellation Request of Tx Buffer 8
bits : 8 - 7 (0 bit)
access : read-write
CR9 : Cancellation Request of Tx Buffer 9
bits : 9 - 8 (0 bit)
access : read-write
CR10 : Cancellation Request of Tx Buffer 10
bits : 10 - 9 (0 bit)
access : read-write
CR11 : Cancellation Request of Tx Buffer 11
bits : 11 - 10 (0 bit)
access : read-write
CR12 : Cancellation Request of Tx Buffer 12
bits : 12 - 11 (0 bit)
access : read-write
CR13 : Cancellation Request of Tx Buffer 13
bits : 13 - 12 (0 bit)
access : read-write
CR14 : Cancellation Request of Tx Buffer 14
bits : 14 - 13 (0 bit)
access : read-write
CR15 : Cancellation Request of Tx Buffer 15
bits : 15 - 14 (0 bit)
access : read-write
CR16 : Cancellation Request of Tx Buffer 16
bits : 16 - 15 (0 bit)
access : read-write
CR17 : Cancellation Request of Tx Buffer 17
bits : 17 - 16 (0 bit)
access : read-write
CR18 : Cancellation Request of Tx Buffer 18
bits : 18 - 17 (0 bit)
access : read-write
CR19 : Cancellation Request of Tx Buffer 19
bits : 19 - 18 (0 bit)
access : read-write
CR20 : Cancellation Request of Tx Buffer 20
bits : 20 - 19 (0 bit)
access : read-write
CR21 : Cancellation Request of Tx Buffer 21
bits : 21 - 20 (0 bit)
access : read-write
CR22 : Cancellation Request of Tx Buffer 22
bits : 22 - 21 (0 bit)
access : read-write
CR23 : Cancellation Request of Tx Buffer 23
bits : 23 - 22 (0 bit)
access : read-write
CR24 : Cancellation Request of Tx Buffer 24
bits : 24 - 23 (0 bit)
access : read-write
CR25 : Cancellation Request of Tx Buffer 25
bits : 25 - 24 (0 bit)
access : read-write
CR26 : Cancellation Request of Tx Buffer 26
bits : 26 - 25 (0 bit)
access : read-write
CR27 : Cancellation Request of Tx Buffer 27
bits : 27 - 26 (0 bit)
access : read-write
CR28 : Cancellation Request of Tx Buffer 28
bits : 28 - 27 (0 bit)
access : read-write
CR29 : Cancellation Request of Tx Buffer 29
bits : 29 - 28 (0 bit)
access : read-write
CR30 : Cancellation Request of Tx Buffer 30
bits : 30 - 29 (0 bit)
access : read-write
CR31 : Cancellation Request of Tx Buffer 31
bits : 31 - 30 (0 bit)
access : read-write
Tx Buffer Transmission Occurred
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TO0 : Transmission Occurred of Tx Buffer 0
bits : 0 - -1 (0 bit)
access : read-only
TO1 : Transmission Occurred of Tx Buffer 1
bits : 1 - 0 (0 bit)
access : read-only
TO2 : Transmission Occurred of Tx Buffer 2
bits : 2 - 1 (0 bit)
access : read-only
TO3 : Transmission Occurred of Tx Buffer 3
bits : 3 - 2 (0 bit)
access : read-only
TO4 : Transmission Occurred of Tx Buffer 4
bits : 4 - 3 (0 bit)
access : read-only
TO5 : Transmission Occurred of Tx Buffer 5
bits : 5 - 4 (0 bit)
access : read-only
TO6 : Transmission Occurred of Tx Buffer 6
bits : 6 - 5 (0 bit)
access : read-only
TO7 : Transmission Occurred of Tx Buffer 7
bits : 7 - 6 (0 bit)
access : read-only
TO8 : Transmission Occurred of Tx Buffer 8
bits : 8 - 7 (0 bit)
access : read-only
TO9 : Transmission Occurred of Tx Buffer 9
bits : 9 - 8 (0 bit)
access : read-only
TO10 : Transmission Occurred of Tx Buffer 10
bits : 10 - 9 (0 bit)
access : read-only
TO11 : Transmission Occurred of Tx Buffer 11
bits : 11 - 10 (0 bit)
access : read-only
TO12 : Transmission Occurred of Tx Buffer 12
bits : 12 - 11 (0 bit)
access : read-only
TO13 : Transmission Occurred of Tx Buffer 13
bits : 13 - 12 (0 bit)
access : read-only
TO14 : Transmission Occurred of Tx Buffer 14
bits : 14 - 13 (0 bit)
access : read-only
TO15 : Transmission Occurred of Tx Buffer 15
bits : 15 - 14 (0 bit)
access : read-only
TO16 : Transmission Occurred of Tx Buffer 16
bits : 16 - 15 (0 bit)
access : read-only
TO17 : Transmission Occurred of Tx Buffer 17
bits : 17 - 16 (0 bit)
access : read-only
TO18 : Transmission Occurred of Tx Buffer 18
bits : 18 - 17 (0 bit)
access : read-only
TO19 : Transmission Occurred of Tx Buffer 19
bits : 19 - 18 (0 bit)
access : read-only
TO20 : Transmission Occurred of Tx Buffer 20
bits : 20 - 19 (0 bit)
access : read-only
TO21 : Transmission Occurred of Tx Buffer 21
bits : 21 - 20 (0 bit)
access : read-only
TO22 : Transmission Occurred of Tx Buffer 22
bits : 22 - 21 (0 bit)
access : read-only
TO23 : Transmission Occurred of Tx Buffer 23
bits : 23 - 22 (0 bit)
access : read-only
TO24 : Transmission Occurred of Tx Buffer 24
bits : 24 - 23 (0 bit)
access : read-only
TO25 : Transmission Occurred of Tx Buffer 25
bits : 25 - 24 (0 bit)
access : read-only
TO26 : Transmission Occurred of Tx Buffer 26
bits : 26 - 25 (0 bit)
access : read-only
TO27 : Transmission Occurred of Tx Buffer 27
bits : 27 - 26 (0 bit)
access : read-only
TO28 : Transmission Occurred of Tx Buffer 28
bits : 28 - 27 (0 bit)
access : read-only
TO29 : Transmission Occurred of Tx Buffer 29
bits : 29 - 28 (0 bit)
access : read-only
TO30 : Transmission Occurred of Tx Buffer 30
bits : 30 - 29 (0 bit)
access : read-only
TO31 : Transmission Occurred of Tx Buffer 31
bits : 31 - 30 (0 bit)
access : read-only
Tx Buffer Cancellation Finished
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CF0 : Cancellation Finished of Tx Buffer 0
bits : 0 - -1 (0 bit)
access : read-only
CF1 : Cancellation Finished of Tx Buffer 1
bits : 1 - 0 (0 bit)
access : read-only
CF2 : Cancellation Finished of Tx Buffer 2
bits : 2 - 1 (0 bit)
access : read-only
CF3 : Cancellation Finished of Tx Buffer 3
bits : 3 - 2 (0 bit)
access : read-only
CF4 : Cancellation Finished of Tx Buffer 4
bits : 4 - 3 (0 bit)
access : read-only
CF5 : Cancellation Finished of Tx Buffer 5
bits : 5 - 4 (0 bit)
access : read-only
CF6 : Cancellation Finished of Tx Buffer 6
bits : 6 - 5 (0 bit)
access : read-only
CF7 : Cancellation Finished of Tx Buffer 7
bits : 7 - 6 (0 bit)
access : read-only
CF8 : Cancellation Finished of Tx Buffer 8
bits : 8 - 7 (0 bit)
access : read-only
CF9 : Cancellation Finished of Tx Buffer 9
bits : 9 - 8 (0 bit)
access : read-only
CF10 : Cancellation Finished of Tx Buffer 10
bits : 10 - 9 (0 bit)
access : read-only
CF11 : Cancellation Finished of Tx Buffer 11
bits : 11 - 10 (0 bit)
access : read-only
CF12 : Cancellation Finished of Tx Buffer 12
bits : 12 - 11 (0 bit)
access : read-only
CF13 : Cancellation Finished of Tx Buffer 13
bits : 13 - 12 (0 bit)
access : read-only
CF14 : Cancellation Finished of Tx Buffer 14
bits : 14 - 13 (0 bit)
access : read-only
CF15 : Cancellation Finished of Tx Buffer 15
bits : 15 - 14 (0 bit)
access : read-only
CF16 : Cancellation Finished of Tx Buffer 16
bits : 16 - 15 (0 bit)
access : read-only
CF17 : Cancellation Finished of Tx Buffer 17
bits : 17 - 16 (0 bit)
access : read-only
CF18 : Cancellation Finished of Tx Buffer 18
bits : 18 - 17 (0 bit)
access : read-only
CF19 : Cancellation Finished of Tx Buffer 19
bits : 19 - 18 (0 bit)
access : read-only
CF20 : Cancellation Finished of Tx Buffer 20
bits : 20 - 19 (0 bit)
access : read-only
CF21 : Cancellation Finished of Tx Buffer 21
bits : 21 - 20 (0 bit)
access : read-only
CF22 : Cancellation Finished of Tx Buffer 22
bits : 22 - 21 (0 bit)
access : read-only
CF23 : Cancellation Finished of Tx Buffer 23
bits : 23 - 22 (0 bit)
access : read-only
CF24 : Cancellation Finished of Tx Buffer 24
bits : 24 - 23 (0 bit)
access : read-only
CF25 : Cancellation Finished of Tx Buffer 25
bits : 25 - 24 (0 bit)
access : read-only
CF26 : Cancellation Finished of Tx Buffer 26
bits : 26 - 25 (0 bit)
access : read-only
CF27 : Cancellation Finished of Tx Buffer 27
bits : 27 - 26 (0 bit)
access : read-only
CF28 : Cancellation Finished of Tx Buffer 28
bits : 28 - 27 (0 bit)
access : read-only
CF29 : Cancellation Finished of Tx Buffer 29
bits : 29 - 28 (0 bit)
access : read-only
CF30 : Cancellation Finished of Tx Buffer 30
bits : 30 - 29 (0 bit)
access : read-only
CF31 : Cancellation Finished of Tx Buffer 31
bits : 31 - 30 (0 bit)
access : read-only
Tx Buffer Transmission Interrupt Enable
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIE0 : Transmission Interrupt Enable of Tx Buffer 0
bits : 0 - -1 (0 bit)
access : read-write
TIE1 : Transmission Interrupt Enable of Tx Buffer 1
bits : 1 - 0 (0 bit)
access : read-write
TIE2 : Transmission Interrupt Enable of Tx Buffer 2
bits : 2 - 1 (0 bit)
access : read-write
TIE3 : Transmission Interrupt Enable of Tx Buffer 3
bits : 3 - 2 (0 bit)
access : read-write
TIE4 : Transmission Interrupt Enable of Tx Buffer 4
bits : 4 - 3 (0 bit)
access : read-write
TIE5 : Transmission Interrupt Enable of Tx Buffer 5
bits : 5 - 4 (0 bit)
access : read-write
TIE6 : Transmission Interrupt Enable of Tx Buffer 6
bits : 6 - 5 (0 bit)
access : read-write
TIE7 : Transmission Interrupt Enable of Tx Buffer 7
bits : 7 - 6 (0 bit)
access : read-write
TIE8 : Transmission Interrupt Enable of Tx Buffer 8
bits : 8 - 7 (0 bit)
access : read-write
TIE9 : Transmission Interrupt Enable of Tx Buffer 9
bits : 9 - 8 (0 bit)
access : read-write
TIE10 : Transmission Interrupt Enable of Tx Buffer 10
bits : 10 - 9 (0 bit)
access : read-write
TIE11 : Transmission Interrupt Enable of Tx Buffer 11
bits : 11 - 10 (0 bit)
access : read-write
TIE12 : Transmission Interrupt Enable of Tx Buffer 12
bits : 12 - 11 (0 bit)
access : read-write
TIE13 : Transmission Interrupt Enable of Tx Buffer 13
bits : 13 - 12 (0 bit)
access : read-write
TIE14 : Transmission Interrupt Enable of Tx Buffer 14
bits : 14 - 13 (0 bit)
access : read-write
TIE15 : Transmission Interrupt Enable of Tx Buffer 15
bits : 15 - 14 (0 bit)
access : read-write
TIE16 : Transmission Interrupt Enable of Tx Buffer 16
bits : 16 - 15 (0 bit)
access : read-write
TIE17 : Transmission Interrupt Enable of Tx Buffer 17
bits : 17 - 16 (0 bit)
access : read-write
TIE18 : Transmission Interrupt Enable of Tx Buffer 18
bits : 18 - 17 (0 bit)
access : read-write
TIE19 : Transmission Interrupt Enable of Tx Buffer 19
bits : 19 - 18 (0 bit)
access : read-write
TIE20 : Transmission Interrupt Enable of Tx Buffer 20
bits : 20 - 19 (0 bit)
access : read-write
TIE21 : Transmission Interrupt Enable of Tx Buffer 21
bits : 21 - 20 (0 bit)
access : read-write
TIE22 : Transmission Interrupt Enable of Tx Buffer 22
bits : 22 - 21 (0 bit)
access : read-write
TIE23 : Transmission Interrupt Enable of Tx Buffer 23
bits : 23 - 22 (0 bit)
access : read-write
TIE24 : Transmission Interrupt Enable of Tx Buffer 24
bits : 24 - 23 (0 bit)
access : read-write
TIE25 : Transmission Interrupt Enable of Tx Buffer 25
bits : 25 - 24 (0 bit)
access : read-write
TIE26 : Transmission Interrupt Enable of Tx Buffer 26
bits : 26 - 25 (0 bit)
access : read-write
TIE27 : Transmission Interrupt Enable of Tx Buffer 27
bits : 27 - 26 (0 bit)
access : read-write
TIE28 : Transmission Interrupt Enable of Tx Buffer 28
bits : 28 - 27 (0 bit)
access : read-write
TIE29 : Transmission Interrupt Enable of Tx Buffer 29
bits : 29 - 28 (0 bit)
access : read-write
TIE30 : Transmission Interrupt Enable of Tx Buffer 30
bits : 30 - 29 (0 bit)
access : read-write
TIE31 : Transmission Interrupt Enable of Tx Buffer 31
bits : 31 - 30 (0 bit)
access : read-write
Tx Buffer Cancellation Finished Interrupt Enable
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFIE0 : Cancellation Finished Interrupt Enable of Tx Buffer 0
bits : 0 - -1 (0 bit)
access : read-write
CFIE1 : Cancellation Finished Interrupt Enable of Tx Buffer 1
bits : 1 - 0 (0 bit)
access : read-write
CFIE2 : Cancellation Finished Interrupt Enable of Tx Buffer 2
bits : 2 - 1 (0 bit)
access : read-write
CFIE3 : Cancellation Finished Interrupt Enable of Tx Buffer 3
bits : 3 - 2 (0 bit)
access : read-write
CFIE4 : Cancellation Finished Interrupt Enable of Tx Buffer 4
bits : 4 - 3 (0 bit)
access : read-write
CFIE5 : Cancellation Finished Interrupt Enable of Tx Buffer 5
bits : 5 - 4 (0 bit)
access : read-write
CFIE6 : Cancellation Finished Interrupt Enable of Tx Buffer 6
bits : 6 - 5 (0 bit)
access : read-write
CFIE7 : Cancellation Finished Interrupt Enable of Tx Buffer 7
bits : 7 - 6 (0 bit)
access : read-write
CFIE8 : Cancellation Finished Interrupt Enable of Tx Buffer 8
bits : 8 - 7 (0 bit)
access : read-write
CFIE9 : Cancellation Finished Interrupt Enable of Tx Buffer 9
bits : 9 - 8 (0 bit)
access : read-write
CFIE10 : Cancellation Finished Interrupt Enable of Tx Buffer 10
bits : 10 - 9 (0 bit)
access : read-write
CFIE11 : Cancellation Finished Interrupt Enable of Tx Buffer 11
bits : 11 - 10 (0 bit)
access : read-write
CFIE12 : Cancellation Finished Interrupt Enable of Tx Buffer 12
bits : 12 - 11 (0 bit)
access : read-write
CFIE13 : Cancellation Finished Interrupt Enable of Tx Buffer 13
bits : 13 - 12 (0 bit)
access : read-write
CFIE14 : Cancellation Finished Interrupt Enable of Tx Buffer 14
bits : 14 - 13 (0 bit)
access : read-write
CFIE15 : Cancellation Finished Interrupt Enable of Tx Buffer 15
bits : 15 - 14 (0 bit)
access : read-write
CFIE16 : Cancellation Finished Interrupt Enable of Tx Buffer 16
bits : 16 - 15 (0 bit)
access : read-write
CFIE17 : Cancellation Finished Interrupt Enable of Tx Buffer 17
bits : 17 - 16 (0 bit)
access : read-write
CFIE18 : Cancellation Finished Interrupt Enable of Tx Buffer 18
bits : 18 - 17 (0 bit)
access : read-write
CFIE19 : Cancellation Finished Interrupt Enable of Tx Buffer 19
bits : 19 - 18 (0 bit)
access : read-write
CFIE20 : Cancellation Finished Interrupt Enable of Tx Buffer 20
bits : 20 - 19 (0 bit)
access : read-write
CFIE21 : Cancellation Finished Interrupt Enable of Tx Buffer 21
bits : 21 - 20 (0 bit)
access : read-write
CFIE22 : Cancellation Finished Interrupt Enable of Tx Buffer 22
bits : 22 - 21 (0 bit)
access : read-write
CFIE23 : Cancellation Finished Interrupt Enable of Tx Buffer 23
bits : 23 - 22 (0 bit)
access : read-write
CFIE24 : Cancellation Finished Interrupt Enable of Tx Buffer 24
bits : 24 - 23 (0 bit)
access : read-write
CFIE25 : Cancellation Finished Interrupt Enable of Tx Buffer 25
bits : 25 - 24 (0 bit)
access : read-write
CFIE26 : Cancellation Finished Interrupt Enable of Tx Buffer 26
bits : 26 - 25 (0 bit)
access : read-write
CFIE27 : Cancellation Finished Interrupt Enable of Tx Buffer 27
bits : 27 - 26 (0 bit)
access : read-write
CFIE28 : Cancellation Finished Interrupt Enable of Tx Buffer 28
bits : 28 - 27 (0 bit)
access : read-write
CFIE29 : Cancellation Finished Interrupt Enable of Tx Buffer 29
bits : 29 - 28 (0 bit)
access : read-write
CFIE30 : Cancellation Finished Interrupt Enable of Tx Buffer 30
bits : 30 - 29 (0 bit)
access : read-write
CFIE31 : Cancellation Finished Interrupt Enable of Tx Buffer 31
bits : 31 - 30 (0 bit)
access : read-write
Tx Event FIFO Configuration
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFSA : Event FIFO Start Address
bits : 2 - 14 (13 bit)
access : read-write
EFS : Event FIFO Size
bits : 16 - 20 (5 bit)
access : read-write
EFWM : Event FIFO Watermark
bits : 24 - 28 (5 bit)
access : read-write
Tx Event FIFO Status
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EFFL : Event FIFO Fill Level
bits : 0 - 4 (5 bit)
access : read-only
EFGI : Event FIFO Get Index
bits : 8 - 11 (4 bit)
access : read-only
EFPI : Event FIFO Put Index
bits : 16 - 19 (4 bit)
access : read-only
EFF : Event FIFO Full
bits : 24 - 23 (0 bit)
access : read-only
TEFL : Tx Event FIFO Element Lost
bits : 25 - 24 (0 bit)
access : read-only
Tx Event FIFO Acknowledge
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFAI : Event FIFO Acknowledge Index
bits : 0 - 3 (4 bit)
access : read-write
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