\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
I2S Clock Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2SEN : I2S clock output enable bit
bits : 0 - -1 (0 bit)
access : read-write
ICSEL : I2S clock selection bit
bits : 1 - 0 (0 bit)
access : read-write
I2S-PLL Control Register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPLLN : Frequency division ratio (N) setting bits of the I2S-PLL clock
bits : 0 - 5 (6 bit)
access : read-write
I2S-PLL Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPRDY : I2S-PLL oscillation stabilization bit
bits : 0 - -1 (0 bit)
access : read-only
I2S-PLL Interrupt Factor Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPCSE : I2S-PLL oscillation stabilization wait complete interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write
I2S-PLL Interrupt Factor Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IPCSC : I2S-PLL interrupt factor status bit
bits : 0 - -1 (0 bit)
access : write-only
I2S-PLL Interrupt Factor Clear Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPCSI : I2S-PLL oscillation stabilization interrupt factor clear bit
bits : 0 - -1 (0 bit)
access : read-only
I2S-PLL Control Register 5
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPLLM : Frequency division ratio (M) setting bits of the I2S-PLL clock
bits : 0 - 5 (6 bit)
access : read-write
I2S Clock Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2SEN1 : I2S clock output enable bit
bits : 0 - -1 (0 bit)
access : read-write
ICSEL1 : I2S clock selection bit
bits : 1 - 0 (0 bit)
access : read-write
I2S-PLL Control Register 5
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPLLM1 : Frequency division ratio (M) setting bits of the I2S-PLL clock
bits : 0 - 5 (6 bit)
access : read-write
I2S-PLL Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPLLEN : I2S-PLL oscillation enable bit
bits : 0 - -1 (0 bit)
access : read-write
I2S-PLL Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPOWT : I2S-PLL oscillation stabilization wait time setting bits
bits : 0 - 1 (2 bit)
access : read-write
I2S-PLL Control Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPLLK : Frequency division ratio (K) setting bits of the I2S-PLL clock
bits : 0 - 3 (4 bit)
access : read-write
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