\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
GSS Clock Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GSSEN : GSS clock output enable/disable setting bit
bits : 0 - -1 (0 bit)
access : read-write
GSS PLL Control Register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPLLN : PLL feedback frequency division rasio seting bits
bits : 0 - 5 (6 bit)
access : read-write
GSS PLL Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPRDY : GDC PLL status bit
bits : 0 - -1 (0 bit)
access : read-only
GSS PLL Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPCSE : PLL oscillation stabilization wait completion interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write
GSS PLL Interrupt Clear Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPCSC : GDC PLL oscillation stabilization wait completion interrupt clear bit
bits : 0 - -1 (0 bit)
access : read-write
GSS PLL Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPCSI : GDC PLL oscillation stabilization wait completion interrupt status bit
bits : 0 - -1 (0 bit)
access : read-only
GSS Clock Select Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASEL : Reference clock for the GDC clock selection bits
bits : 0 - 0 (1 bit)
access : read-write
ACG : Clock gating for Reference clock for GDC clock setting bit
bits : 4 - 3 (0 bit)
access : read-write
PSEL : Peripheral clock for the GDC Sub system selection bit
bits : 8 - 7 (0 bit)
access : read-write
PCG : HCLK Clock gating for Reference clock for Peripherals setting bit
bits : 12 - 11 (0 bit)
access : read-write
GSS Reset Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTEN : Software reset for the GDC Sub system setting bit
bits : 0 - -1 (0 bit)
access : read-write
GSS Mode Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEN : PLL oscillation under case of TIMER mode control bit
bits : 0 - -1 (0 bit)
access : read-write
GSS PLL Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPLLEN : GDC PLL enable/disable setting bit
bits : 0 - -1 (0 bit)
access : read-write
GPINC : GDC PLL input clock selection bit
bits : 1 - 0 (0 bit)
access : read-write
GSS PLL Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPOWT : PLL clock stabilization wait time set up bits
bits : 0 - 1 (2 bit)
access : read-write
GSS PLL Control Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPLLK : PLL input clock frequency division ratio setting bits
bits : 0 - 3 (4 bit)
access : read-write
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