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CRG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x78 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SCM_CTL

BSC_PSR

APBC0_PSR

APBC1_PSR

APBC2_PSR

SWC_PSR

TTC_PSR

CSW_TMR

PSW_TMR

PLL_CTL1

PLL_CTL2

SCM_STR

CSV_CTL

CSV_STR

FCSWH_CTL

FCSWL_CTL

FCSWD_CTL

DBWDT_CTL

INT_ENR

INT_STR

INT_CLR

PLLCG_CTL

STB_CTL

RST_STR


SCM_CTL

System Clock Mode Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCM_CTL SCM_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCE SOSCE PLLE RCS

MOSCE : Main clock oscillation enable bit
bits : 1 - 0 (0 bit)
access : read-write

SOSCE : Sub clock oscillation enable bit
bits : 3 - 2 (0 bit)
access : read-write

PLLE : PLL oscillation enable bit
bits : 4 - 3 (0 bit)
access : read-write

RCS : Master clock switch control bits
bits : 5 - 6 (2 bit)
access : read-write


BSC_PSR

Base Clock Prescaler Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BSC_PSR BSC_PSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSR0 BSR1 BSR2

BSR0 : Base clock frequency division ratio setting bit
bits : 0 - -1 (0 bit)
access : read-write

BSR1 : Base clock frequency division ratio setting bit
bits : 1 - 0 (0 bit)
access : read-write

BSR2 : Base clock frequency division ratio setting bit
bits : 2 - 1 (0 bit)
access : read-write


APBC0_PSR

APB0 Prescaler Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBC0_PSR APBC0_PSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APBC00 APBC01

APBC00 : APB0 bus clock frequency division ratio setting bit 0
bits : 0 - -1 (0 bit)
access : read-write

APBC01 : APB0 bus clock frequency division ratio setting bit 1
bits : 1 - 0 (0 bit)
access : read-write


APBC1_PSR

APB1 Prescaler Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBC1_PSR APBC1_PSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APBC10 APBC11 APBC1RST APBC1EN

APBC10 : APB1 bus clock frequency division ratio setting bit 0
bits : 0 - -1 (0 bit)
access : read-write

APBC11 : APB1 bus clock frequency division ratio setting bit 1
bits : 1 - 0 (0 bit)
access : read-write

APBC1RST : APB1 bus reset control bit
bits : 4 - 3 (0 bit)
access : read-write

APBC1EN : APB1 clock enable bit
bits : 7 - 6 (0 bit)
access : read-write


APBC2_PSR

APB2 Prescaler Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBC2_PSR APBC2_PSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APBC20 APBC21 APBC2RST APBC2EN

APBC20 : APB2 bus clock frequency division ratio setting bit 0
bits : 0 - -1 (0 bit)
access : read-write

APBC21 : APB2 bus clock frequency division ratio setting bit 1
bits : 1 - 0 (0 bit)
access : read-write

APBC2RST : APB2 bus reset control bit
bits : 4 - 3 (0 bit)
access : read-write

APBC2EN : APB2 clock enable bit
bits : 7 - 6 (0 bit)
access : read-write


SWC_PSR

Software Watchdog Clock Prescaler Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWC_PSR SWC_PSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWDS0 SWDS1

SWDS0 : Software watchdog clock frequency division ratio setting bit 0
bits : 0 - -1 (0 bit)
access : read-write

SWDS1 : Software watchdog clock frequency division ratio setting bit 1
bits : 1 - 0 (0 bit)
access : read-write


TTC_PSR

Trace Clock Prescaler Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TTC_PSR TTC_PSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TTC

TTC : Trace clock frequency division ratio setting bit
bits : 0 - 0 (1 bit)
access : read-write


CSW_TMR

Clock Stabilization Wait Time Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSW_TMR CSW_TMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOWT0 MOWT1 MOWT2 MOWT3 SOWT0 SOWT1 SOWT2 SOWT3

MOWT0 : Main clock stabilization wait time setup bit 0
bits : 0 - -1 (0 bit)
access : read-write

MOWT1 : Main clock stabilization wait time setup bit 1
bits : 1 - 0 (0 bit)
access : read-write

MOWT2 : Main clock stabilization wait time setup bit 2
bits : 2 - 1 (0 bit)
access : read-write

MOWT3 : Main clock stabilization wait time setup bit 3
bits : 3 - 2 (0 bit)
access : read-write

SOWT0 : Sub clock stabilization wait time setup bit 0
bits : 4 - 3 (0 bit)
access : read-write

SOWT1 : Sub clock stabilization wait time setup bit 1
bits : 5 - 4 (0 bit)
access : read-write

SOWT2 : Sub clock stabilization wait time setup bit 2
bits : 6 - 5 (0 bit)
access : read-write

SOWT3 : Sub clock stabilization wait time setup bit 3
bits : 7 - 6 (0 bit)
access : read-write


PSW_TMR

PLL Clock Stabilization Wait Time Setup Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSW_TMR PSW_TMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POWT0 POWT1 POWT2 PINC

POWT0 : PLL clock stabilization wait time setup bit 0
bits : 0 - -1 (0 bit)
access : read-write

POWT1 : PLL clock stabilization wait time setup bit 1
bits : 1 - 0 (0 bit)
access : read-write

POWT2 : PLL clock stabilization wait time setup bit 2
bits : 2 - 1 (0 bit)
access : read-write

PINC : PLL input clock select bit
bits : 4 - 3 (0 bit)
access : read-write


PLL_CTL1

PLL Control Register 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL_CTL1 PLL_CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLM0 PLLM1 PLLM2 PLLM3 PLLK0 PLLK1 PLLK2 PLLK3

PLLM0 : PLL VCO clock frequency division ratio setting bit 0
bits : 0 - -1 (0 bit)
access : read-write

PLLM1 : PLL VCO clock frequency division ratio setting bit 1
bits : 1 - 0 (0 bit)
access : read-write

PLLM2 : PLL VCO clock frequency division ratio setting bit 2
bits : 2 - 1 (0 bit)
access : read-write

PLLM3 : PLL VCO clock frequency division ratio setting bit 3
bits : 3 - 2 (0 bit)
access : read-write

PLLK0 : PLL input clock frequency division ratio setting bit 0
bits : 4 - 3 (0 bit)
access : read-write

PLLK1 : PLL input clock frequency division ratio setting bit 1
bits : 5 - 4 (0 bit)
access : read-write

PLLK2 : PLL input clock frequency division ratio setting bit 2
bits : 6 - 5 (0 bit)
access : read-write

PLLK3 : PLL input clock frequency division ratio setting bit 3
bits : 7 - 6 (0 bit)
access : read-write


PLL_CTL2

PLL Control Register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL_CTL2 PLL_CTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLN0 PLLN1 PLLN2 PLLN3 PLLN4 PLLN5

PLLN0 : PLL feedback frequency division ratio setting bit 0
bits : 0 - -1 (0 bit)
access : read-write

PLLN1 : PLL feedback frequency division ratio setting bit 1
bits : 1 - 0 (0 bit)
access : read-write

PLLN2 : PLL feedback frequency division ratio setting bit 2
bits : 2 - 1 (0 bit)
access : read-write

PLLN3 : PLL feedback frequency division ratio setting bit 3
bits : 3 - 2 (0 bit)
access : read-write

PLLN4 : PLL feedback frequency division ratio setting bit 4
bits : 4 - 3 (0 bit)
access : read-write

PLLN5 : PLL feedback frequency division ratio setting bit 5
bits : 5 - 4 (0 bit)
access : read-write


SCM_STR

System Clock Mode Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SCM_STR SCM_STR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MORDY SORDY PLRDY RCM0 RCM1 RCM2

MORDY : Main clock oscillation stable bit
bits : 1 - 0 (0 bit)
access : read-only

SORDY : Sub clock oscillation stable bit
bits : 3 - 2 (0 bit)
access : read-only

PLRDY : PLL oscillation stable bit
bits : 4 - 3 (0 bit)
access : read-only

RCM0 : Master clock selection bit 0
bits : 5 - 4 (0 bit)
access : read-only

RCM1 : Master clock selection bit 1
bits : 6 - 5 (0 bit)
access : read-only

RCM2 : Master clock selection bit 2
bits : 7 - 6 (0 bit)
access : read-only


CSV_CTL

CSV control register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSV_CTL CSV_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCSVE SCSVE FCSDE FCSRE FCD0 FCD1 FCD2

MCSVE : Main CSV function enable bit
bits : 0 - -1 (0 bit)
access : read-write

SCSVE : Sub CSV function enable bit
bits : 1 - 0 (0 bit)
access : read-write

FCSDE : FCS function enable bit
bits : 8 - 7 (0 bit)
access : read-write

FCSRE : FCS reset output enable bit
bits : 9 - 8 (0 bit)
access : read-write

FCD0 : FCS count cycle setting bit 0
bits : 12 - 11 (0 bit)
access : read-write

FCD1 : FCS count cycle setting bit 1
bits : 13 - 12 (0 bit)
access : read-write

FCD2 : FCS count cycle setting bit 2
bits : 14 - 13 (0 bit)
access : read-write


CSV_STR

CSV status register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSV_STR CSV_STR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCMF SCMF

MCMF : Main clock failure detection flag
bits : 0 - -1 (0 bit)
access : read-only

SCMF : Sub clock failure detection flag
bits : 1 - 0 (0 bit)
access : read-only


FCSWH_CTL

Frequency detection window setting register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCSWH_CTL FCSWH_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FWH

FWH : Frequency detection window setting bits (Upper)
bits : 0 - 14 (15 bit)
access : read-write


FCSWL_CTL

Frequency detection window setting register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCSWL_CTL FCSWL_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FWL

FWL : Frequency detection window setting bits (Lower)
bits : 0 - 14 (15 bit)
access : read-write


FCSWD_CTL

Frequency detection counter register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FCSWD_CTL FCSWD_CTL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FWD

FWD : Frequency detection count data
bits : 0 - 14 (15 bit)
access : read-only


DBWDT_CTL

Debug Break Watchdog Timer Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBWDT_CTL DBWDT_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPSWBE DPHWBE

DPSWBE : SW-WDG debug mode break bit
bits : 5 - 4 (0 bit)
access : read-write

DPHWBE : HW-WDG debug mode break bit
bits : 7 - 6 (0 bit)
access : read-write


INT_ENR

Interrupt Enable Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_ENR INT_ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCSE SCSE PCSE FCSE

MCSE : Main oscillation stabilization completion interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write

SCSE : Sub oscillation stabilization completion interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write

PCSE : PLL oscillation stabilization completion interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write

FCSE : Anomalous frequency detection interrupt enable bit
bits : 5 - 4 (0 bit)
access : read-write


INT_STR

Interrupt Status Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INT_STR INT_STR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCSI SCSI PCSI FCSI

MCSI : Main oscillation stabilization completion interrupt status bit
bits : 0 - -1 (0 bit)
access : read-only

SCSI : Sub oscillation stabilization completion interrupt status bit
bits : 1 - 0 (0 bit)
access : read-only

PCSI : PLL oscillation stabilization completion interrupt status bit
bits : 2 - 1 (0 bit)
access : read-only

FCSI : Anomalous frequency detection interrupt status bit
bits : 5 - 4 (0 bit)
access : read-only


INT_CLR

Interrupt Clear Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INT_CLR INT_CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCSC SCSC PCSC FCSC

MCSC : Main oscillation stabilization completion interrupt cause clear bit
bits : 0 - -1 (0 bit)
access : write-only

SCSC : Sub oscillation stabilization completion interrupt cause clear bit
bits : 1 - 0 (0 bit)
access : write-only

PCSC : PLL oscillation stabilization completion interrupt cause clear bit
bits : 2 - 1 (0 bit)
access : write-only

FCSC : Anomalous frequency detection interrupt cause clear bit
bits : 5 - 4 (0 bit)
access : write-only


PLLCG_CTL

PLL Clock Gear Control Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCG_CTL PLLCG_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLCGEN PLLCGSTR PLLCGSTS PLLCGSSN PLLCGSTP PLLCGLP

PLLCGEN : PLL clock gear enable bit
bits : 0 - -1 (0 bit)
access : read-write

PLLCGSTR : PLL clock gear start bit
bits : 1 - 0 (0 bit)
access : read-write

PLLCGSTS : PLL clock gear start bits
bits : 6 - 6 (1 bit)
access : read-write

PLLCGSSN : PLL clock gear start step number configuration bits
bits : 8 - 12 (5 bit)
access : read-write

PLLCGSTP : PLL clock gear step configuration bits
bits : 14 - 14 (1 bit)
access : read-write

PLLCGLP : PLL clock gear step loop configuration bits
bits : 16 - 22 (7 bit)
access : read-write


STB_CTL

Standby Mode Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STB_CTL STB_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM DSTM SPL KEY

STM : Standby mode selection bit
bits : 0 - 0 (1 bit)
access : read-write

DSTM : Deep standby mode select bit
bits : 2 - 1 (0 bit)
access : read-write

SPL : Standby pin level setting bit
bits : 4 - 3 (0 bit)
access : read-write

KEY : Standby mode control write control bit
bits : 16 - 30 (15 bit)
access : read-write


RST_STR

Reset Cause Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RST_STR RST_STR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PONR INITX SWDT HWDT CSVR FCSR SRST

PONR : Power-on reset/low-voltage detection reset flag
bits : 0 - -1 (0 bit)
access : read-only

INITX : INITX pin input reset flag
bits : 1 - 0 (0 bit)
access : read-only

SWDT : Software watchdog reset flag
bits : 4 - 3 (0 bit)
access : read-only

HWDT : Hardware watchdog reset flag
bits : 5 - 4 (0 bit)
access : read-only

CSVR : Clock failure detection reset flag
bits : 6 - 5 (0 bit)
access : read-only

FCSR : Flag for anomalous frequency detection reset
bits : 7 - 6 (0 bit)
access : read-only

SRST : Software reset flag
bits : 8 - 7 (0 bit)
access : read-only



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