\n

MFT0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1ED byte (0x0)
mem_usage : registers
protection : not protected

Registers

OCU_OCCP0

OCU_OCCP1

OCU_OCCP2

OCU_OCCP3

OCU_OCCP4

OCU_OCCP5

OCU_OCSA10

OCU_OCSB10

OCU_OCSD10

OCU_OCSA32

OCU_OCSB32

OCU_OCSD32

OCU_OCSA54

OCU_OCSB54

OCU_OCSD54

OCU_OCSC

OCU_OCSE0

OCU_OCSE1

OCU_OCSE2

OCU_OCSE3

OCU_OCSE4

OCU_OCSE5

FRT_TCCP0

FRT_TCDT0

FRT_TCSA0

FRT_TCSC0

FRT_TCCP1

FRT_TCDT1

FRT_TCSA1

FRT_TCSC1

FRT_TCCP2

FRT_TCDT2

FRT_TCSA2

FRT_TCSC2

FRT_TCAL

OCU_OCFS10

OCU_OCFS32

OCU_OCFS54

ICU_ICFS10

ICU_ICFS32

ADCMP_ACFS10

ADCMP_ACFS32

ADCMP_ACFS54

ICU_ICCP0

ICU_ICCP1

ICU_ICCP2

ICU_ICCP3

ICU_ICSA10

ICU_ICSB10

ICU_ICSA32

ICU_ICSB32

WFG_WFTF10

WFG_WFTA10

WFG_WFTB10

WFG_WFTF32

WFG_WFTA32

WFG_WFTB32

WFG_WFTF54

WFG_WFTA54

WFG_WFTB54

WFG_WFSA10

WFG_WFSA32

WFG_WFSA54

WFG_WFIR

WFG_NZCL

ADCMP_ACMP0

ADCMP_ACMP1

ADCMP_ACMP2

ADCMP_ACMP3

ADCMP_ACMP4

ADCMP_ACMP5

ADCMP_ACSA

ADCMP_ACSC0

ADCMP_ACSD0

ADCMP_ACMC0

ADCMP_ACSC1

ADCMP_ACSD1

ADCMP_ACMC1

ADCMP_ACSC2

ADCMP_ACSD2

ADCMP_ACMC2

ADCMP_ACSC3

ADCMP_ACSD3

ADCMP_ACMC3

ADCMP_ACSC4

ADCMP_ACSD4

ADCMP_ACMC4

ADCMP_ACSC5

ADCMP_ACSD5

ADCMP_ACMC5

FRT_TCSD


OCU_OCCP0

OCU ch.0 Compare Value Store Register
address_offset : 0x102 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCCP0 OCU_OCCP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCCP1

OCU ch.1 Compare Value Store Register
address_offset : 0x106 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCCP1 OCU_OCCP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCCP2

OCU ch.2 Compare Value Store Register
address_offset : 0x10A Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCCP2 OCU_OCCP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCCP3

OCU ch.3 Compare Value Store Register
address_offset : 0x10E Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCCP3 OCU_OCCP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCCP4

OCU ch.4 Compare Value Store Register
address_offset : 0x112 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCCP4 OCU_OCCP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCCP5

OCU ch.5 Compare Value Store Register
address_offset : 0x116 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCCP5 OCU_OCCP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSA10

OCU ch.0/1 Control Register A
address_offset : 0x118 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSA10 OCU_OCSA10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CST0 CST1 IOE0 IOE1 IOP0 IOP1

CST0 : Enables the operation of OCU ch.(0)
bits : 0 - -1 (0 bit)
access : read-write

CST1 : Enables the operation of OCU ch.(1)
bits : 1 - 0 (0 bit)
access : read-write

IOE0 : Generates interrupt, when 1 is set to OCSA.IOP0
bits : 4 - 3 (0 bit)
access : read-write

IOE1 : Generates interrupt, when 1 is set to OCSA.IOP1
bits : 5 - 4 (0 bit)
access : read-write

IOP0 : Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0).
bits : 6 - 5 (0 bit)
access : read-write

IOP1 : Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1).
bits : 7 - 6 (0 bit)
access : read-write


OCU_OCSB10

OCU ch.0/1 Control Register B
address_offset : 0x119 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSB10 OCU_OCSB10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OTD0 OTD1 CMOD FM4

OTD0 : Indicates that the RT(0) output pin is in the High-level output state.
bits : 0 - -1 (0 bit)
access : read-write

OTD1 : Indicates that the RT(1) output pin is in the High-level output state.
bits : 1 - 0 (0 bit)
access : read-write

CMOD : selects OCU's operation mode in combination with OCSC.MOD0 to MOD5
bits : 4 - 3 (0 bit)
access : read-write

FM4 : selects FM4 mode for operating mode
bits : 7 - 6 (0 bit)
access : read-write


OCU_OCSD10

OCU ch.0/1 Control Register D
address_offset : 0x11A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSD10 OCU_OCSD10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCCP0BUFE OCCP1BUFE OCSE0BUFE OCSE1BUFE OPBM0 OPBM1 OEBM0 OEBM1 OFEX0 OFEX1

OCCP0BUFE : Enable buffer register function of OCCP(0)
bits : 0 - 0 (1 bit)
access : read-write

OCCP1BUFE : Enable buffer register function of OCCP(1)
bits : 2 - 2 (1 bit)
access : read-write

OCSE0BUFE : Enable buffer register function of OCSE(0)
bits : 4 - 4 (1 bit)
access : read-write

OCSE1BUFE : Enable buffer register function of OCSE(1)
bits : 6 - 6 (1 bit)
access : read-write

OPBM0 : sets the linked transfer settings with the FRT interrupt mask counter
bits : 8 - 7 (0 bit)
access : read-write

OPBM1 : sets the linked transfer settings with the FRT interrupt mask counter
bits : 9 - 8 (0 bit)
access : read-write

OEBM0 : sets the linked transfer settings with the FRT interrupt mask counter
bits : 10 - 9 (0 bit)
access : read-write

OEBM1 : sets the linked transfer settings with the FRT interrupt mask counter
bits : 11 - 10 (0 bit)
access : read-write

OFEX0 : extends the matching determination conditions of the connected FRT with the OCCP(0) register value
bits : 12 - 11 (0 bit)
access : read-write

OFEX1 : extends the matching determination conditions of the connected FRT with the OCCP(1) register value
bits : 13 - 12 (0 bit)
access : read-write


OCU_OCSA32

OCU ch.2/3 Control Register A
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSA32 OCU_OCSA32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSB32

OCU ch.2/3 Control Register B
address_offset : 0x11D Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSB32 OCU_OCSB32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSD32

OCU ch.2/3 Control Register D
address_offset : 0x11E Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSD32 OCU_OCSD32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSA54

OCU ch.4/5 Control Register A
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSA54 OCU_OCSA54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSB54

OCU ch.4/5 Control Register B
address_offset : 0x121 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSB54 OCU_OCSB54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSD54

OCU ch.4/5 Control Register D
address_offset : 0x122 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSD54 OCU_OCSD54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSC

OCU Control Register C
address_offset : 0x124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSC OCU_OCSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOD0 MOD1 MOD2 MOD3 MOD4 MOD5

MOD0 : OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0,h.1 in combination with OCSB10.CMOD
bits : 8 - 7 (0 bit)
access : read-write

MOD1 : OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0,h.1 in combination with OCSB10.CMOD
bits : 9 - 8 (0 bit)
access : read-write

MOD2 : OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2,h.3 in combination with OCSB32.CMOD
bits : 10 - 9 (0 bit)
access : read-write

MOD3 : OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2,h.3 in combination with OCSB32.CMOD
bits : 11 - 10 (0 bit)
access : read-write

MOD4 : OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4,h.5 in combination with OCSB54.CMOD
bits : 12 - 11 (0 bit)
access : read-write

MOD5 : OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4,h.5 in combination with OCSB54.CMOD
bits : 13 - 12 (0 bit)
access : read-write


OCU_OCSE0

OCU ch.0 Control Register E
address_offset : 0x128 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSE0 OCU_OCSE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCSE

OCSE : specify the setting conditions of the OCU's matching detection register (IOP0)
bits : 0 - 14 (15 bit)
access : read-write


OCU_OCSE1

OCU ch.1 Control Register E
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSE1 OCU_OCSE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCSE

OCSE : specify the setting conditions of the OCU's matching detection register (IOP0/IOP1)
bits : 0 - 30 (31 bit)
access : read-write


OCU_OCSE2

OCU ch.2 Control Register E
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSE2 OCU_OCSE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSE3

OCU ch.3 Control Register E
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSE3 OCU_OCSE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSE4

OCU ch.4 Control Register E
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSE4 OCU_OCSE4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCSE5

OCU ch.5 Control Register E
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCSE5 OCU_OCSE5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCCP0

FRT-ch.0 Cycle Setting Register
address_offset : 0x142 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCCP0 FRT_TCCP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCDT0

FRT-ch.0 Count Value Register
address_offset : 0x146 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCDT0 FRT_TCDT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCSA0

FRT-ch.0 Control Register A
address_offset : 0x148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCSA0 FRT_TCSA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK SCLR MODE STOP BFE ICRE ICLR IRQZE IRQZF ECKE

CLK : FRT clock cycle
bits : 0 - 2 (3 bit)
access : read-write

SCLR : FRT operation state initialization request
bits : 4 - 3 (0 bit)
access : write-only

MODE : FRT's count mode
bits : 5 - 4 (0 bit)
access : read-write

STOP : Puts FRT in stopping state
bits : 6 - 5 (0 bit)
access : read-write

BFE : Enables TCCP's buffer function
bits : 7 - 6 (0 bit)
access : read-write

ICRE : Generates interrupt when 1 is set to TCSA.ICLR
bits : 8 - 7 (0 bit)
access : read-write

ICLR : interrupt flag
bits : 9 - 8 (0 bit)
access : read-write

IRQZE : Generates interrupt, when 1 is set to TCSA.IRQZF
bits : 13 - 12 (0 bit)
access : read-write

IRQZF : zero interrupt flag
bits : 14 - 13 (0 bit)
access : read-write

ECKE : Uses an external input clock (FRCK) as FRT's count clock
bits : 15 - 14 (0 bit)
access : read-write


FRT_TCSC0

FRT-ch.0 Control Register C
address_offset : 0x14A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCSC0 FRT_TCSC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSZI MSPI MSZC MSPC

MSZI : Masked Zero value detection number
bits : 0 - 2 (3 bit)
access : read-write

MSPI : Masked Peak value detection number
bits : 4 - 6 (3 bit)
access : read-write

MSZC : Current counter value of a Zero value detection mask counter
bits : 8 - 10 (3 bit)
access : read-only

MSPC : Current counter value of a Peak value detection mask counter
bits : 12 - 14 (3 bit)
access : read-only


FRT_TCCP1

FRT-ch.1 Cycle Setting Register
address_offset : 0x14E Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCCP1 FRT_TCCP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCDT1

FRT-ch.1 Count Value Register
address_offset : 0x152 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCDT1 FRT_TCDT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCSA1

FRT-ch.1 Control Register A
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCSA1 FRT_TCSA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCSC1

FRT-ch.1 Control Register C
address_offset : 0x156 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCSC1 FRT_TCSC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCCP2

FRT-ch.2 Cycle Setting Register
address_offset : 0x15A Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCCP2 FRT_TCCP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCDT2

FRT-ch.2 Count Value Register
address_offset : 0x15E Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCDT2 FRT_TCDT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCSA2

FRT-ch.2 Control Register A
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCSA2 FRT_TCSA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCSC2

FRT-ch.2 Control Register C
address_offset : 0x162 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCSC2 FRT_TCSC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCAL

FRT Simultaneous Start Control Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCAL FRT_TCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOP00 STOP01 STOP02 STOP10 STOP11 STOP12 STOP20 STOP21 STOP22 SCLR00 SCLR01 SCLR02 SCLR10 SCLR11 SCLR12 SCLR20 SCLR21 SCLR22

STOP00 : Mirror register of the STOP bit located in TCSA0 register of MFT-unit0
bits : 0 - -1 (0 bit)
access : read-write

STOP01 : Mirror register of the STOP bit located in TCSA1 register of MFT-unit0
bits : 1 - 0 (0 bit)
access : read-write

STOP02 : Mirror register of the STOP bit located in TCSA2 register of MFT-unit0
bits : 2 - 1 (0 bit)
access : read-write

STOP10 : Mirror register of the STOP bit located in TCSA0 register of MFT-unit1
bits : 3 - 2 (0 bit)
access : read-write

STOP11 : Mirror register of the STOP bit located in TCSA1 register of MFT-unit1
bits : 4 - 3 (0 bit)
access : read-write

STOP12 : Mirror register of the STOP bit located in TCSA2 register of MFT-unit1
bits : 5 - 4 (0 bit)
access : read-write

STOP20 : Mirror register of the STOP bit located in TCSA0 register of MFT-unit2
bits : 6 - 5 (0 bit)
access : read-write

STOP21 : Mirror register of the STOP bit located in TCSA1 register of MFT-unit2
bits : 7 - 6 (0 bit)
access : read-write

STOP22 : Mirror register of the STOP bit located in TCSA2 register of MFT-unit2
bits : 8 - 7 (0 bit)
access : read-write

SCLR00 : Mirror register of the SCLR bit located in TCSA0 register of MFT-unit0
bits : 16 - 15 (0 bit)
access : write-only

SCLR01 : Mirror register of the SCLR bit located in TCSA1 register of MFT-unit0
bits : 17 - 16 (0 bit)
access : write-only

SCLR02 : Mirror register of the SCLR bit located in TCSA2 register of MFT-unit0
bits : 18 - 17 (0 bit)
access : write-only

SCLR10 : Mirror register of the SCLR bit located in TCSA0 register of MFT-unit1
bits : 19 - 18 (0 bit)
access : write-only

SCLR11 : Mirror register of the SCLR bit located in TCSA1 register of MFT-unit1
bits : 20 - 19 (0 bit)
access : write-only

SCLR12 : Mirror register of the SCLR bit located in TCSA2 register of MFT-unit1
bits : 21 - 20 (0 bit)
access : write-only

SCLR20 : Mirror register of the SCLR bit located in TCSA0 register of MFT-unit2
bits : 22 - 21 (0 bit)
access : write-only

SCLR21 : Mirror register of the SCLR bit located in TCSA1 register of MFT-unit2
bits : 23 - 22 (0 bit)
access : write-only

SCLR22 : Mirror register of the SCLR bit located in TCSA2 register of MFT-unit2
bits : 24 - 23 (0 bit)
access : write-only


OCU_OCFS10

OCU ch.0/1 Connecting FRT Select Register
address_offset : 0x168 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCFS10 OCU_OCFS10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FSO0 FSO1

FSO0 : Connects FRT ch.x to OCU ch.0
bits : 0 - 2 (3 bit)
access : read-write

FSO1 : Connects FRT ch.x to OCU ch.1
bits : 4 - 6 (3 bit)
access : read-write


OCU_OCFS32

OCU ch.2/3 Connecting FRT Select Register
address_offset : 0x169 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCFS32 OCU_OCFS32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCU_OCFS54

OCU ch.4/5 Connecting FRT Select Register
address_offset : 0x16A Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCU_OCFS54 OCU_OCFS54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICFS10

ICU ch.0/1 Connecting FRT Select Register
address_offset : 0x16C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICFS10 ICU_ICFS10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FSI0 FSI1

FSI0 : Connects FRT ch.x to ICU ch.(0)
bits : 0 - 2 (3 bit)
access : read-write

FSI1 : Connects FRT ch.x to ICU ch.(1)
bits : 4 - 6 (3 bit)
access : read-write


ICU_ICFS32

ICU ch.2/3 Connecting FRT Select Register
address_offset : 0x16D Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICFS32 ICU_ICFS32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACFS10

ADCMP ch.0/1 Connecting FRT Select Register
address_offset : 0x170 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACFS10 ADCMP_ACFS10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FSA0 FSA1

FSA0 : specify the FRT to be connected to ADCMP ch.(0)
bits : 0 - 2 (3 bit)
access : read-write

FSA1 : specify the FRT to be connected to ADCMP ch.(1)
bits : 4 - 6 (3 bit)
access : read-write


ADCMP_ACFS32

ADCMP ch.2/3 Connecting FRT Select Register
address_offset : 0x171 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACFS32 ADCMP_ACFS32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACFS54

ADCMP ch.4/5 Connecting FRT Select Register
address_offset : 0x172 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACFS54 ADCMP_ACFS54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICCP0

ICU-ch.0 Capture Value Store Register
address_offset : 0x176 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICU_ICCP0 ICU_ICCP0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICCP1

ICU-ch.1 Capture Value Store Register
address_offset : 0x17A Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICCP1 ICU_ICCP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICCP2

ICU-ch.2 Capture Value Store Register
address_offset : 0x17E Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICCP2 ICU_ICCP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICCP3

ICU-ch.3 Capture Value Store Register
address_offset : 0x182 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICCP3 ICU_ICCP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICSA10

ICU ch.0/1 Control Register A
address_offset : 0x184 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICSA10 ICU_ICSA10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EG0 EG1 ICE0 ICE1 ICP0 ICP1

EG0 : enables/disables the operation of ICU-ch.(0) and selects a valid edge(s)
bits : 0 - 0 (1 bit)
access : read-write

EG1 : enables/disables the operation of ICU-ch.(1) and selects a valid edge(s)
bits : 2 - 2 (1 bit)
access : read-write

ICE0 : Generates interrupt, when 1 is set to ICSA.ICP0.
bits : 4 - 3 (0 bit)
access : read-write

ICE1 : Generates interrupt, when 1 is set to ICSA.ICP1.
bits : 5 - 4 (0 bit)
access : read-write

ICP0 : Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed
bits : 6 - 5 (0 bit)
access : read-write

ICP1 : Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed
bits : 7 - 6 (0 bit)
access : read-write


ICU_ICSB10

ICU ch.0/1 Control Register B
address_offset : 0x185 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICU_ICSB10 ICU_ICSB10 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IEI0 IEI1

IEI0 : indicates the latest valid edge of ICU ch.(0)
bits : 0 - -1 (0 bit)
access : read-only

IEI1 : indicates the latest valid edge of ICU ch.(1)
bits : 1 - 0 (0 bit)
access : read-only


ICU_ICSA32

ICU ch.2/3 Control Register A
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICSA32 ICU_ICSA32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICU_ICSB32

ICU ch.2/3 Control Register B
address_offset : 0x189 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICU_ICSB32 ICU_ICSB32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFTF10

Pulse Counter Value Register for WFG ch.0/1
address_offset : 0x18E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFTF10 WFG_WFTF10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFTA10

WFG Timer Value Register for WFG ch.0/1
address_offset : 0x190 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFTA10 WFG_WFTA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFTB10

WFG Timer Value Register for WFG ch.0/1
address_offset : 0x192 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFTB10 WFG_WFTB10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFTF32

Pulse Counter Value Register for WFG ch.2/3
address_offset : 0x196 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFTF32 WFG_WFTF32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFTA32

WFG Timer Value Register for WFG ch.2/3
address_offset : 0x198 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFTA32 WFG_WFTA32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFTB32

WFG Timer Value Register for WFG ch.2/3
address_offset : 0x19A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFTB32 WFG_WFTB32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFTF54

Pulse Counter Value Register for WFG ch.4/5
address_offset : 0x19E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFTF54 WFG_WFTF54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFTA54

WFG Timer Value Register for WFG ch.4/5
address_offset : 0x1A0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFTA54 WFG_WFTA54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFTB54

WFG Timer Value Register for WFG ch.4/5
address_offset : 0x1A2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFTB54 WFG_WFTB54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFSA10

WFG Control Register A for WFG ch.0/1
address_offset : 0x1A4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFSA10 WFG_WFSA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCK TMD GTEN PSEL PGEN DMOD

DCK : set the count clock cycle for the WFG timer and Pulse counter
bits : 0 - 1 (2 bit)
access : read-write

TMD : select the WFG's operation mode
bits : 3 - 4 (2 bit)
access : read-write

GTEN : selects the output conditions for the CH_GATE output signal of the WFG
bits : 6 - 6 (1 bit)
access : read-write

PSEL : select the PPG timer unit to be used for each channel of the WFG
bits : 8 - 8 (1 bit)
access : read-write

PGEN : specifies how to reflect the CH_PPG signal for each channel of the WFG
bits : 10 - 10 (1 bit)
access : read-write

DMOD : 1specifies polarity for RTO(0) and RTO(1) signal outputs
bits : 12 - 12 (1 bit)
access : read-write


WFG_WFSA32

WFG Control Register A for WFG ch.2/3
address_offset : 0x1A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFSA32 WFG_WFSA32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFSA54

WFG Control Register A for WFG ch.4/5
address_offset : 0x1AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFSA54 WFG_WFSA54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WFG_WFIR

WFG Interrupt Control Register
address_offset : 0x1B0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_WFIR WFG_WFIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTIFA DTICA DTIFB DTICB TMIF10 TMIC10 TMIE10 TMIS10 TMIF32 TMIC32 TMIE32 TMIS32 TMIF54 TMIC54 TMIE54 TMIS54

DTIFA : detects the event of DTTIX signal input via digital noise-canceller
bits : 0 - -1 (0 bit)
access : read-only

DTICA : clears the DTIFA interrupt flag
bits : 1 - 0 (0 bit)
access : write-only

DTIFB : detects DTTIX signal input via analog noise filter
bits : 2 - 1 (0 bit)
access : read-only

DTICB : clears DTIFB bit.
bits : 3 - 2 (0 bit)
access : write-only

TMIF10 : detects the event of WFG10 reload timer interrupt occurrence
bits : 4 - 3 (0 bit)
access : read-only

TMIC10 : clears TIMF10 bit
bits : 5 - 4 (0 bit)
access : write-only

TMIE10 : starts WFG10 reload timer and checks the operation state of it.
bits : 6 - 5 (0 bit)
access : read-write

TMIS10 : stops the WFG10 reload timer and clears TMIF10
bits : 7 - 6 (0 bit)
access : write-only

TMIF32 : detects the event of WFG32 reload timer interrupt occurrence
bits : 8 - 7 (0 bit)
access : read-only

TMIC32 : clears TIMF32 bit
bits : 9 - 8 (0 bit)
access : write-only

TMIE32 : 1stops the WFG32 reload timer and clears TMIF32
bits : 10 - 9 (0 bit)
access : read-write

TMIS32 : stops the WFG32 reload timer and clears TMIF32
bits : 11 - 10 (0 bit)
access : write-only

TMIF54 : detects the event of WFG54 reload timer interrupt occurrence
bits : 12 - 11 (0 bit)
access : read-only

TMIC54 : clears TIMF54 bit
bits : 13 - 12 (0 bit)
access : write-only

TMIE54 : stops the WFG54 reload timer and clears TMIF54
bits : 14 - 13 (0 bit)
access : read-write

TMIS54 : stops the WFG54 reload timer and clears TMIF54
bits : 15 - 14 (0 bit)
access : write-only


WFG_NZCL

NZCL Control Register
address_offset : 0x1B4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WFG_NZCL WFG_NZCL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTIEA NWS SDTI DTIEB DHOLD DIMA DIMB WIM10 WIM32 WIM54

DTIEA : Enables the path for digital noise filter from DTTIX pin
bits : 0 - -1 (0 bit)
access : read-write

NWS : set the noise-canceling width for a digital noise-canceller
bits : 1 - 2 (2 bit)
access : read-write

SDTI : sets the WFIR.DTIFA register by writing to the register from the CPU
bits : 4 - 3 (0 bit)
access : write-only

DTIEB : Enables the path from DTTIX pin to analog noise filter
bits : 5 - 4 (0 bit)
access : read-write

DHOLD : selects whether the RTO output signal of WFG is held when the DTIF interrupt signal is asserted
bits : 7 - 6 (0 bit)
access : read-write

DIMA : selects whether a DTIF interrupt is masked when the WFIR.DTIFA flag is set
bits : 8 - 7 (0 bit)
access : read-write

DIMB : selects whether a DTIF interrupt is masked when the WFIR.TIFDTIFB flag is set
bits : 9 - 8 (0 bit)
access : read-write

WIM10 : selects whether a WFG10 reload timer interrupt is masked when the WFIR.TMIF10 flag is set
bits : 12 - 11 (0 bit)
access : read-write

WIM32 : selects whether a WFG32 reload timer interrupt is masked when the WFIR.TMIF32 flag is set
bits : 13 - 12 (0 bit)
access : read-write

WIM54 : selects whether a WFG54 reload timer interrupt is masked when the WFIR.TMIF54 flag is set
bits : 14 - 13 (0 bit)
access : read-write


ADCMP_ACMP0

ADCMP ch.0 Compare Value Store Register
address_offset : 0x1BA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACMP0 ADCMP_ACMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACMP

ACMP : 0
bits : 0 - 14 (15 bit)
access : read-write


ADCMP_ACMP1

ADCMP ch.1 Compare Value Store Register
address_offset : 0x1BE Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACMP1 ADCMP_ACMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACMP2

ADCMP ch.2 Compare Value Store Register
address_offset : 0x1C2 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACMP2 ADCMP_ACMP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACMP3

ADCMP ch.3 Compare Value Store Register
address_offset : 0x1C6 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACMP3 ADCMP_ACMP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACMP4

ADCMP ch.4 Compare Value Store Register
address_offset : 0x1CA Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACMP4 ADCMP_ACMP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACMP5

ADCMP ch.5 Compare Value Store Register
address_offset : 0x1CE Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACMP5 ADCMP_ACMP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACSA

ADCMP Control Register A
address_offset : 0x1D0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSA ADCMP_ACSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE10 CE32 CE54 SEL10 SEL32 SEL54

CE10 : enables/disables compatibility of ADCMP ch.1 and ch.0 with FM3 Family products
bits : 0 - 0 (1 bit)
access : read-write

CE32 : enables/disables compatibility of ADCMP ch.3 and ch.2 with FM3 Family products
bits : 2 - 2 (1 bit)
access : read-write

CE54 : enables/disables compatibility of ADCMP ch.5 and ch.4 with FM3 Family products
bits : 4 - 4 (1 bit)
access : read-write

SEL10 : selects compatible operation of ADCMP ch.1 and ch.0 with FM3 Family products
bits : 8 - 8 (1 bit)
access : read-write

SEL32 : selects compatible operation of ADCMP ch.3 and ch.2 with FM3 Family products
bits : 10 - 10 (1 bit)
access : read-write

SEL54 : selects compatible operation of ADCMP ch.5 and ch.4 with FM3 Family products
bits : 12 - 12 (1 bit)
access : read-write


ADCMP_ACSC0

ADCMP ch.0 Control Register C
address_offset : 0x1D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSC0 ADCMP_ACSC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BUFE ADSEL APBM

BUFE : select enable/disable and transfer timing for buffer function of the ACMP register.
bits : 0 - 0 (1 bit)
access : read-write

ADSEL : specify the destinations of ADC start signals that are output by ADCMP
bits : 2 - 3 (2 bit)
access : read-write

APBM : sets the linked transfer with the FRT interrupt mask counter
bits : 5 - 4 (0 bit)
access : read-write


ADCMP_ACSD0

ADCMP ch.0 Control Register D
address_offset : 0x1D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSD0 ADCMP_ACSD0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMOD OCUS DE PE UE ZE

AMOD : selects operation mode for ADCMP
bits : 0 - -1 (0 bit)
access : read-write

OCUS : selects the OCU OCCP register that will become the start for offset start
bits : 1 - 0 (0 bit)
access : read-write

DE : enables/disables the operation of the ADCMP that is counting down for the connected FRT
bits : 4 - 3 (0 bit)
access : read-write

PE : enables/disables the operation of the ADCMP that is counting down at the Peak value of the connected FRT
bits : 5 - 4 (0 bit)
access : read-write

UE : enables/disables the operation of the ADCMP that is counting up for the connected FRT
bits : 6 - 5 (0 bit)
access : read-write

ZE : enables/disables the operation of the ADCMP when the FRT is 0x0000
bits : 7 - 6 (0 bit)
access : read-write


ADCMP_ACMC0

ADCMP ch.0 Mask Compare Value Storage Register
address_offset : 0x1D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACMC0 ADCMP_ACMC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMC MZCE MPCE

AMC : specifies the value to be compared with the FRT interrupt mask counter
bits : 0 - 2 (3 bit)
access : read-write

MZCE : specifies whether a comparison is performed with the FRT zero interrupt mask counter
bits : 6 - 5 (0 bit)
access : read-write

MPCE : specifies whether a comparison is performed with the FRT peak interrupt mask counter
bits : 7 - 6 (0 bit)
access : read-write


ADCMP_ACSC1

ADCMP ch.1 Control Register C
address_offset : 0x1D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSC1 ADCMP_ACSC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACSD1

ADCMP ch.1 Control Register D
address_offset : 0x1D9 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSD1 ADCMP_ACSD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACMC1

ADCMP ch.1 Mask Compare Value Storage Register
address_offset : 0x1DA Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACMC1 ADCMP_ACMC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACSC2

ADCMP ch.2 Control Register C
address_offset : 0x1DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSC2 ADCMP_ACSC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACSD2

ADCMP ch.2 Control Register D
address_offset : 0x1DD Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSD2 ADCMP_ACSD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACMC2

ADCMP ch.2 Mask Compare Value Storage Register
address_offset : 0x1DE Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACMC2 ADCMP_ACMC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACSC3

ADCMP ch.3 Control Register C
address_offset : 0x1E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSC3 ADCMP_ACSC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACSD3

ADCMP ch.3 Control Register D
address_offset : 0x1E1 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSD3 ADCMP_ACSD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACMC3

ADCMP ch.3 Mask Compare Value Storage Register
address_offset : 0x1E2 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACMC3 ADCMP_ACMC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACSC4

ADCMP ch.4 Control Register C
address_offset : 0x1E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSC4 ADCMP_ACSC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACSD4

ADCMP ch.4 Control Register D
address_offset : 0x1E5 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSD4 ADCMP_ACSD4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACMC4

ADCMP ch.4 Mask Compare Value Storage Register
address_offset : 0x1E6 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACMC4 ADCMP_ACMC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACSC5

ADCMP ch.5 Control Register C
address_offset : 0x1E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSC5 ADCMP_ACSC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACSD5

ADCMP ch.5 Control Register D
address_offset : 0x1E9 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACSD5 ADCMP_ACSD5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCMP_ACMC5

ADCMP ch.5 Mask Compare Value Storage Register
address_offset : 0x1EA Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCMP_ACMC5 ADCMP_ACMC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FRT_TCSD

FRT Control Register D
address_offset : 0x1EC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRT_TCSD FRT_TCSD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OFMD1 OFMD2

OFMD1 : selects the count mode with offset for FRT ch.1
bits : 0 - -1 (0 bit)
access : read-write

OFMD2 : selects the count mode with offset for FRT ch.2
bits : 1 - 0 (0 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.