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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1B1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x200 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WTCR10

WTCR11

WTCR12

WTCR13

WTCR20

WTCR21

WTSR

WTMIR

WTHR

WTDR

WTDW

WTMOR

WTYR

ALMIR

ALHR

ALDR

ALMOR

ALYR

WTTR0

WTTR1

WTTR2

WTCAL0

WTCAL1

WTCALEN

WTDIV

WTDIVEN

WTCALPRD

WTCOSEL

VB_CLKDIV

WTOSCCNT

CCS

CCB

BOOST

EWKUP

VDET

HIBRST

VBPFR

VBPCR

VBDDR

VBDIR

VBDOR

VBPZR

BREG00

BREG01

BREG02

BREG03

BREG04

BREG05

BREG06

BREG07

BREG08

BREG09

BREG0A

BREG0B

BREG0C

BREG0D

BREG0E

BREG0F

BREG10

BREG11

BREG12

BREG13

BREG14

BREG15

BREG16

BREG17

BREG18

BREG19

BREG1A

BREG1B

BREG1C

BREG1D

BREG1E

BREG1F

BREG20

BREG21

BREG22

BREG23

BREG24

BREG25

BREG26

BREG27

BREG28

BREG29

BREG2A

BREG2B

BREG2C

BREG2D

BREG2E

BREG2F

BREG30

BREG31

BREG32

BREG33

BREG34

BREG35

BREG36

BREG37

BREG38

BREG39

BREG3A

BREG3B

BREG3C

BREG3D

BREG3E

BREG3F

BREG40

BREG41

BREG42

BREG43

BREG44

BREG45

BREG46

BREG47

BREG48

BREG49

BREG4A

BREG4B

BREG4C

BREG4D

BREG4E

BREG4F

BREG50

BREG51

BREG52

BREG53

BREG54

BREG55

BREG56

BREG57

BREG58

BREG59

BREG5A

BREG5B

BREG5C

BREG5D

BREG5E

BREG5F

BREG60

BREG61

BREG62

BREG63

BREG64

BREG65

BREG66

BREG67

BREG68

BREG69

BREG6A

BREG6B

BREG6C

BREG6D

BREG6E

BREG6F

BREG70

BREG71

BREG72

BREG73

BREG74

BREG75

BREG76

BREG77

BREG78

BREG79

BREG7A

BREG7B

BREG7C

BREG7D

BREG7E

BREG7F


WTCR10

Control Register 10
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR10 WTCR10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ST RUN SRST SCST SCRST BUSY TRANS

ST : Start bit
bits : 0 - -1 (0 bit)
access : read-write

RUN : RTC count block operation bit
bits : 2 - 1 (0 bit)
access : read-only

SRST : RTC reset bit
bits : 3 - 2 (0 bit)
access : read-write

SCST : 1-second clock output stop bit
bits : 4 - 3 (0 bit)
access : read-write

SCRST : Sub second generation/1-second generation counter reset bit
bits : 5 - 4 (0 bit)
access : read-write

BUSY : Busy bit
bits : 6 - 5 (0 bit)
access : read-only

TRANS : Transfer flag bit
bits : 7 - 6 (0 bit)
access : read-only


WTCR11

Control Register 11
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR11 WTCR11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MIEN HEN DEN MOEN YEN

MIEN : Alarm minute register enable bit
bits : 0 - -1 (0 bit)
access : read-write

HEN : Alarm hour register enable bit
bits : 1 - 0 (0 bit)
access : read-write

DEN : Alarm day register enable bit
bits : 2 - 1 (0 bit)
access : read-write

MOEN : Alarm month register enable bit
bits : 3 - 2 (0 bit)
access : read-write

YEN : Alarm year register enable bit
bits : 4 - 3 (0 bit)
access : read-write


WTCR12

Control Register 12
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR12 WTCR12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTSSI INTSI INTMI INTHI INTTMI INTALI INTERI INTCRI

INTSSI : Every 0.5-second flag bit
bits : 0 - -1 (0 bit)
access : read-write

INTSI : Every second flag bit
bits : 1 - 0 (0 bit)
access : read-write

INTMI : Every minute flag bit
bits : 2 - 1 (0 bit)
access : read-write

INTHI : Every hour flag bit
bits : 3 - 2 (0 bit)
access : read-write

INTTMI : Timer underflow detection flag bit
bits : 4 - 3 (0 bit)
access : read-write

INTALI : Alarm coincidence flag bit
bits : 5 - 4 (0 bit)
access : read-write

INTERI : Time rewrite error interrupt flag bit
bits : 6 - 5 (0 bit)
access : read-write

INTCRI : Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag bit
bits : 7 - 6 (0 bit)
access : read-write


WTCR13

Control Register 13
address_offset : 0x10C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR13 WTCR13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTSSIE INTSIE INTMIE INTHIE INTTMIE INTALIE INTERIE INTCRIE

INTSSIE : Every 0.5-second interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write

INTSIE : Every second interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write

INTMIE : Every minute interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write

INTHIE : Every hour interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write

INTTMIE : Timer underflow interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write

INTALIE : Alarm coincidence interrupt enable bit
bits : 5 - 4 (0 bit)
access : read-write

INTERIE : Time rewrite error interrupt enable bit
bits : 6 - 5 (0 bit)
access : read-write

INTCRIE : Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable bit
bits : 7 - 6 (0 bit)
access : read-write


WTCR20

Control Register 20
address_offset : 0x110 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR20 WTCR20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CREAD CWRITE BREAD BWRITE PREAD PWRITE

CREAD : RTC setting recall control bit
bits : 0 - -1 (0 bit)
access : read-write

CWRITE : RTC setting save control bit
bits : 1 - 0 (0 bit)
access : read-write

BREAD : Back up register recall control bit
bits : 2 - 1 (0 bit)
access : read-write

BWRITE : Back up register save control bit
bits : 3 - 2 (0 bit)
access : read-write

PREAD : VBAT PORT recall control bit
bits : 4 - 3 (0 bit)
access : read-write

PWRITE : VBAT PORT save control bit
bits : 5 - 4 (0 bit)
access : read-write


WTCR21

Control Register 21
address_offset : 0x114 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR21 WTCR21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TMST TMEN TMRUN

TMST : Timer counter start bit
bits : 0 - -1 (0 bit)
access : read-write

TMEN : Timer counter control bit
bits : 1 - 0 (0 bit)
access : read-write

TMRUN : Timer counter operation bit
bits : 2 - 1 (0 bit)
access : read-only


WTSR

Second Register
address_offset : 0x11C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTSR WTSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 S TS

S : 1st digit of the second information
bits : 0 - 2 (3 bit)
access : read-write

TS : 2nd digit of the second information
bits : 4 - 5 (2 bit)
access : read-write


WTMIR

Minute Register
address_offset : 0x120 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTMIR WTMIR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MI TMI

MI : 1st digit of the minute information
bits : 0 - 2 (3 bit)
access : read-write

TMI : 2nd digit of the minute information
bits : 4 - 5 (2 bit)
access : read-write


WTHR

Hour register
address_offset : 0x124 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTHR WTHR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 H TH

H : 1st digit of the hour information
bits : 0 - 2 (3 bit)
access : read-write

TH : 2nd digit of the hour information
bits : 4 - 4 (1 bit)
access : read-write


WTDR

Day Register
address_offset : 0x128 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTDR WTDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 D TD

D : 1st digit of the day information
bits : 0 - 2 (3 bit)
access : read-write

TD : 2nd digit of the day information
bits : 4 - 4 (1 bit)
access : read-write


WTDW

Day of the Week Register
address_offset : 0x12C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTDW WTDW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DW

DW : Day of the week information
bits : 0 - 1 (2 bit)
access : read-write


WTMOR

Month Register
address_offset : 0x130 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTMOR WTMOR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MO TMO

MO : 1st digit of the month information
bits : 0 - 2 (3 bit)
access : read-write

TMO : 2nd digit of the month information
bits : 4 - 3 (0 bit)
access : read-write


WTYR

Year Register
address_offset : 0x134 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTYR WTYR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 Y TY

Y : 1st digit of the year information
bits : 0 - 2 (3 bit)
access : read-write

TY : 2nd digit of the year information
bits : 4 - 6 (3 bit)
access : read-write


ALMIR

Alarm Minute Register
address_offset : 0x138 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALMIR ALMIR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMI TAMI

AMI : 1st digit of the alarm-set minute information
bits : 0 - 2 (3 bit)
access : read-write

TAMI : 2nd digit of the alarm-set minute information
bits : 4 - 5 (2 bit)
access : read-write


ALHR

Alarm Hour Register
address_offset : 0x13C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALHR ALHR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AH TAH

AH : 1st digit of the alarm-set hour information
bits : 0 - 2 (3 bit)
access : read-write

TAH : 2nd digit of the alarm-set hour information
bits : 4 - 4 (1 bit)
access : read-write


ALDR

Alarm Date Register
address_offset : 0x140 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALDR ALDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AD TAD

AD : 1st digit of the alarm-set date information
bits : 0 - 2 (3 bit)
access : read-write

TAD : 2nd digit of the alarm-set date information
bits : 4 - 4 (1 bit)
access : read-write


ALMOR

Alarm Month Register
address_offset : 0x144 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALMOR ALMOR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMO TAMO

AMO : 1st digit of the alarm-set month information
bits : 0 - 2 (3 bit)
access : read-write

TAMO : 2nd digit of the alarm-set month information
bits : 4 - 3 (0 bit)
access : read-write


ALYR

Alarm Years Register
address_offset : 0x148 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALYR ALYR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AY TAY

AY : 1st digit of the alarm-set year information
bits : 0 - 2 (3 bit)
access : read-write

TAY : 2nd digit of the alarm-set year information
bits : 4 - 6 (3 bit)
access : read-write


WTTR0

Timer Setting Register 0
address_offset : 0x14C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTTR0 WTTR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM7

TM0 : Timer Setting Register
bits : 0 - -1 (0 bit)
access : read-write

TM1 : Timer Setting Register
bits : 1 - 0 (0 bit)
access : read-write

TM2 : Timer Setting Register
bits : 2 - 1 (0 bit)
access : read-write

TM3 : Timer Setting Register
bits : 3 - 2 (0 bit)
access : read-write

TM4 : Timer Setting Register
bits : 4 - 3 (0 bit)
access : read-write

TM5 : Timer Setting Register
bits : 5 - 4 (0 bit)
access : read-write

TM6 : Timer Setting Register
bits : 6 - 5 (0 bit)
access : read-write

TM7 : Timer Setting Register
bits : 7 - 6 (0 bit)
access : read-write


WTTR1

Timer Setting Register 1
address_offset : 0x150 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTTR1 WTTR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TM8 TM9 TM10 TM11 TM12 TM13 TM14 TM15

TM8 : Timer Setting Register
bits : 0 - -1 (0 bit)
access : read-write

TM9 : Timer Setting Register
bits : 1 - 0 (0 bit)
access : read-write

TM10 : Timer Setting Register
bits : 2 - 1 (0 bit)
access : read-write

TM11 : Timer Setting Register
bits : 3 - 2 (0 bit)
access : read-write

TM12 : Timer Setting Register
bits : 4 - 3 (0 bit)
access : read-write

TM13 : Timer Setting Register
bits : 5 - 4 (0 bit)
access : read-write

TM14 : Timer Setting Register
bits : 6 - 5 (0 bit)
access : read-write

TM15 : Timer Setting Register
bits : 7 - 6 (0 bit)
access : read-write


WTTR2

Timer Setting Register 2
address_offset : 0x154 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTTR2 WTTR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TM16 TM17

TM16 : Timer Setting Register
bits : 0 - -1 (0 bit)
access : read-write

TM17 : Timer Setting Register
bits : 1 - 0 (0 bit)
access : read-write


WTCAL0

Frequency Correction Value Setting Register 0
address_offset : 0x158 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCAL0 WTCAL0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCAL0

WTCAL0 : Frequency correction value setting bits 0
bits : 0 - 6 (7 bit)
access : read-write


WTCAL1

Frequency Correction Value Setting Register 1
address_offset : 0x15C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCAL1 WTCAL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCAL1

WTCAL1 : Frequency correction value setting bits 1
bits : 0 - 0 (1 bit)
access : read-write


WTCALEN

Frequency Correction Enable Register
address_offset : 0x160 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCALEN WTCALEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCALEN

WTCALEN : Frequency correction enable bit
bits : 0 - -1 (0 bit)
access : read-write


WTDIV

Division Ratio Setting Register
address_offset : 0x164 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTDIV WTDIV read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTDIV

WTDIV : Division ration setting bits
bits : 0 - 2 (3 bit)
access : read-write


WTDIVEN

Divider Output Enable Register
address_offset : 0x168 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTDIVEN WTDIVEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTDIVEN WTDIVRDY

WTDIVEN : Divider enable bit
bits : 0 - -1 (0 bit)
access : read-write

WTDIVRDY : Divider state bit
bits : 1 - 0 (0 bit)
access : read-only


WTCALPRD

Frequency Correction Period Setting Register
address_offset : 0x16C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCALPRD WTCALPRD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCALPRD

WTCALPRD : Frequency correction value setting bits
bits : 0 - 4 (5 bit)
access : read-write


WTCOSEL

RTCCO Output Selection Register
address_offset : 0x170 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCOSEL WTCOSEL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCOSEL

WTCOSEL : RTCCO output selection bit
bits : 0 - -1 (0 bit)
access : read-write


VB_CLKDIV

VBAT Clock Divider Register
address_offset : 0x174 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VB_CLKDIV VB_CLKDIV read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIV

DIV : Transfer clock set bits
bits : 0 - 6 (7 bit)
access : read-write


WTOSCCNT

WT Oscillation Circuit Control Register
address_offset : 0x178 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTOSCCNT WTOSCCNT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOSCEX SOSCNTL

SOSCEX : Oscillation enable bit
bits : 0 - -1 (0 bit)
access : read-write

SOSCNTL : Cooperative operation control bit
bits : 1 - 0 (0 bit)
access : read-write


CCS

Oscillation Sustain Current Control Register
address_offset : 0x17C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCS CCS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CCS

CCS : Oscillation sustain current set bits
bits : 0 - 6 (7 bit)
access : read-write


CCB

Oscillation Boost Current Control Register
address_offset : 0x180 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCB CCB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CCB

CCB : Oscillation boost current set bits
bits : 0 - 6 (7 bit)
access : read-write


BOOST

Oscillation Boost Clock Setting Register
address_offset : 0x188 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOST BOOST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BOOST

BOOST : Oscillation boost time set bits
bits : 0 - 0 (1 bit)
access : read-write


EWKUP

Wakeup Request Register
address_offset : 0x18C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EWKUP EWKUP read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WUP0

WUP0 : Wakeup request bit
bits : 0 - -1 (0 bit)
access : read-write


VDET

Power-On Circuit State and Power-On Signal Register
address_offset : 0x190 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDET VDET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PON

PON : Power-on bit
bits : 7 - 6 (0 bit)
access : read-write


HIBRST

Hibernation Start Register
address_offset : 0x198 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIBRST HIBRST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HIBRST

HIBRST : Hibernation start bit
bits : 0 - -1 (0 bit)
access : read-write


VBPFR

Port Function Set Register
address_offset : 0x19C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBPFR VBPFR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VPFR0 VPFR1 VPFR2 VPFR3 SPSR0 SPSR1

VPFR0 : Port function of P48/VREGCTL pin set bit
bits : 0 - -1 (0 bit)
access : read-write

VPFR1 : Port function of P49/VWAKEUP pin set bit
bits : 1 - 0 (0 bit)
access : read-write

VPFR2 : Port function of P47/X1A pin set bit
bits : 2 - 1 (0 bit)
access : read-write

VPFR3 : Port function of P46/X0A pin set bit
bits : 3 - 2 (0 bit)
access : read-write

SPSR0 : Oscillation pin function set bits
bits : 4 - 3 (0 bit)
access : read-write

SPSR1 : Oscillation pin function set bits
bits : 5 - 4 (0 bit)
access : read-write


VBPCR

Pull-up Set Register
address_offset : 0x1A0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBPCR VBPCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VPCR0 VPCR1 VPCR2 VPCR3

VPCR0 : P48/VREGCTL pin pull-up set bit
bits : 0 - -1 (0 bit)
access : read-write

VPCR1 : P49/VWAKEUP pin pull-up set bit
bits : 1 - 0 (0 bit)
access : read-write

VPCR2 : P47/X1A pin pull-up set bit
bits : 2 - 1 (0 bit)
access : read-write

VPCR3 : P46/X0A pin pull-up set bit
bits : 3 - 2 (0 bit)
access : read-write


VBDDR

Port I/O Direction Set Register
address_offset : 0x1A4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBDDR VBDDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VDDR0 VDDR1 VDDR2 VDDR3

VDDR0 : Port direction of P48/VREGCTL pin set bit
bits : 0 - -1 (0 bit)
access : read-write

VDDR1 : Port direction of P49/VWAKEUP pin set bit
bits : 1 - 0 (0 bit)
access : read-write

VDDR2 : Port direction of P47/X1A pin set bit
bits : 2 - 1 (0 bit)
access : read-write

VDDR3 : Port direction of P46/X0A pin set bit
bits : 3 - 2 (0 bit)
access : read-write


VBDIR

Port Input Data Register
address_offset : 0x1A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBDIR VBDIR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VDIR0 VDIR1 VDIR2 VDIR3

VDIR0 : Port input data of P48/VREGCTL pin bit
bits : 0 - -1 (0 bit)
access : read-write

VDIR1 : Port input data of P49/VWAKEUP pin bit
bits : 1 - 0 (0 bit)
access : read-write

VDIR2 : Port input data of P47/X1A pin bit
bits : 2 - 1 (0 bit)
access : read-write

VDIR3 : Port input data of P46/X0A pin bit
bits : 3 - 2 (0 bit)
access : read-write


VBDOR

Port Output Data Register
address_offset : 0x1AC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBDOR VBDOR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VDOR0 VDOR1 VDOR2 VDOR3

VDOR0 : Port output data of P48/VREGCTL pin bit
bits : 0 - -1 (0 bit)
access : read-write

VDOR1 : Port output data of P49/VWAKEUP pin bit
bits : 1 - 0 (0 bit)
access : read-write

VDOR2 : Port output data of P47/X1A pin bit
bits : 2 - 1 (0 bit)
access : read-write

VDOR3 : Port output data of P46/X0A pin bit
bits : 3 - 2 (0 bit)
access : read-write


VBPZR

Port Pseudo-Open Drain Set Register
address_offset : 0x1B0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBPZR VBPZR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VPZR0 VPZR1

VPZR0 : P48/VREGCTL pin pseudo-open drain set bit
bits : 0 - -1 (0 bit)
access : read-write

VPZR1 : P49/VWAKEUP pin pseudo-open drain set bit
bits : 1 - 0 (0 bit)
access : read-write


BREG00

Backup Register
address_offset : 0x200 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG00 BREG00 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG01

Backup Register
address_offset : 0x201 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG01 BREG01 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG02

Backup Register
address_offset : 0x202 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG02 BREG02 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG03

Backup Register
address_offset : 0x203 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG03 BREG03 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG04

Backup Register
address_offset : 0x204 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG04 BREG04 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG05

Backup Register
address_offset : 0x205 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG05 BREG05 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG06

Backup Register
address_offset : 0x206 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG06 BREG06 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG07

Backup Register
address_offset : 0x207 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG07 BREG07 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG08

Backup Register
address_offset : 0x208 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG08 BREG08 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG09

Backup Register
address_offset : 0x209 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG09 BREG09 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG0A

Backup Register
address_offset : 0x20A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG0A BREG0A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG0B

Backup Register
address_offset : 0x20B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG0B BREG0B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG0C

Backup Register
address_offset : 0x20C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG0C BREG0C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG0D

Backup Register
address_offset : 0x20D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG0D BREG0D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG0E

Backup Register
address_offset : 0x20E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG0E BREG0E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG0F

Backup Register
address_offset : 0x20F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG0F BREG0F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG10

Backup Register
address_offset : 0x210 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG10 BREG10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG11

Backup Register
address_offset : 0x211 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG11 BREG11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG12

Backup Register
address_offset : 0x212 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG12 BREG12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG13

Backup Register
address_offset : 0x213 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG13 BREG13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG14

Backup Register
address_offset : 0x214 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG14 BREG14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG15

Backup Register
address_offset : 0x215 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG15 BREG15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG16

Backup Register
address_offset : 0x216 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG16 BREG16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG17

Backup Register
address_offset : 0x217 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG17 BREG17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG18

Backup Register
address_offset : 0x218 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG18 BREG18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG19

Backup Register
address_offset : 0x219 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG19 BREG19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG1A

Backup Register
address_offset : 0x21A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG1A BREG1A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG1B

Backup Register
address_offset : 0x21B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG1B BREG1B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG1C

Backup Register
address_offset : 0x21C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG1C BREG1C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG1D

Backup Register
address_offset : 0x21D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG1D BREG1D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG1E

Backup Register
address_offset : 0x21E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG1E BREG1E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG1F

Backup Register
address_offset : 0x21F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG1F BREG1F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG20

Backup Register
address_offset : 0x220 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG20 BREG20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG21

Backup Register
address_offset : 0x221 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG21 BREG21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG22

Backup Register
address_offset : 0x222 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG22 BREG22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG23

Backup Register
address_offset : 0x223 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG23 BREG23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG24

Backup Register
address_offset : 0x224 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG24 BREG24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG25

Backup Register
address_offset : 0x225 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG25 BREG25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG26

Backup Register
address_offset : 0x226 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG26 BREG26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG27

Backup Register
address_offset : 0x227 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG27 BREG27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG28

Backup Register
address_offset : 0x228 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG28 BREG28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG29

Backup Register
address_offset : 0x229 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG29 BREG29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG2A

Backup Register
address_offset : 0x22A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG2A BREG2A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG2B

Backup Register
address_offset : 0x22B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG2B BREG2B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG2C

Backup Register
address_offset : 0x22C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG2C BREG2C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG2D

Backup Register
address_offset : 0x22D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG2D BREG2D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG2E

Backup Register
address_offset : 0x22E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG2E BREG2E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG2F

Backup Register
address_offset : 0x22F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG2F BREG2F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG30

Backup Register
address_offset : 0x230 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG30 BREG30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG31

Backup Register
address_offset : 0x231 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG31 BREG31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG32

Backup Register
address_offset : 0x232 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG32 BREG32 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG33

Backup Register
address_offset : 0x233 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG33 BREG33 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG34

Backup Register
address_offset : 0x234 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG34 BREG34 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG35

Backup Register
address_offset : 0x235 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG35 BREG35 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG36

Backup Register
address_offset : 0x236 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG36 BREG36 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG37

Backup Register
address_offset : 0x237 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG37 BREG37 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG38

Backup Register
address_offset : 0x238 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG38 BREG38 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG39

Backup Register
address_offset : 0x239 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG39 BREG39 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG3A

Backup Register
address_offset : 0x23A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG3A BREG3A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG3B

Backup Register
address_offset : 0x23B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG3B BREG3B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG3C

Backup Register
address_offset : 0x23C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG3C BREG3C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG3D

Backup Register
address_offset : 0x23D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG3D BREG3D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG3E

Backup Register
address_offset : 0x23E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG3E BREG3E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG3F

Backup Register
address_offset : 0x23F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG3F BREG3F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG40

Backup Register
address_offset : 0x240 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG40 BREG40 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG41

Backup Register
address_offset : 0x241 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG41 BREG41 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG42

Backup Register
address_offset : 0x242 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG42 BREG42 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG43

Backup Register
address_offset : 0x243 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG43 BREG43 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG44

Backup Register
address_offset : 0x244 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG44 BREG44 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG45

Backup Register
address_offset : 0x245 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG45 BREG45 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG46

Backup Register
address_offset : 0x246 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG46 BREG46 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG47

Backup Register
address_offset : 0x247 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG47 BREG47 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG48

Backup Register
address_offset : 0x248 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG48 BREG48 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG49

Backup Register
address_offset : 0x249 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG49 BREG49 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG4A

Backup Register
address_offset : 0x24A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG4A BREG4A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG4B

Backup Register
address_offset : 0x24B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG4B BREG4B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG4C

Backup Register
address_offset : 0x24C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG4C BREG4C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG4D

Backup Register
address_offset : 0x24D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG4D BREG4D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG4E

Backup Register
address_offset : 0x24E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG4E BREG4E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG4F

Backup Register
address_offset : 0x24F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG4F BREG4F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG50

Backup Register
address_offset : 0x250 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG50 BREG50 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG51

Backup Register
address_offset : 0x251 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG51 BREG51 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG52

Backup Register
address_offset : 0x252 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG52 BREG52 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG53

Backup Register
address_offset : 0x253 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG53 BREG53 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG54

Backup Register
address_offset : 0x254 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG54 BREG54 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG55

Backup Register
address_offset : 0x255 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG55 BREG55 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG56

Backup Register
address_offset : 0x256 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG56 BREG56 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG57

Backup Register
address_offset : 0x257 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG57 BREG57 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG58

Backup Register
address_offset : 0x258 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG58 BREG58 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG59

Backup Register
address_offset : 0x259 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG59 BREG59 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG5A

Backup Register
address_offset : 0x25A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG5A BREG5A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG5B

Backup Register
address_offset : 0x25B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG5B BREG5B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG5C

Backup Register
address_offset : 0x25C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG5C BREG5C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG5D

Backup Register
address_offset : 0x25D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG5D BREG5D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG5E

Backup Register
address_offset : 0x25E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG5E BREG5E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG5F

Backup Register
address_offset : 0x25F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG5F BREG5F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG60

Backup Register
address_offset : 0x260 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG60 BREG60 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG61

Backup Register
address_offset : 0x261 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG61 BREG61 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG62

Backup Register
address_offset : 0x262 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG62 BREG62 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG63

Backup Register
address_offset : 0x263 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG63 BREG63 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG64

Backup Register
address_offset : 0x264 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG64 BREG64 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG65

Backup Register
address_offset : 0x265 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG65 BREG65 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG66

Backup Register
address_offset : 0x266 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG66 BREG66 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG67

Backup Register
address_offset : 0x267 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG67 BREG67 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG68

Backup Register
address_offset : 0x268 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG68 BREG68 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG69

Backup Register
address_offset : 0x269 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG69 BREG69 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG6A

Backup Register
address_offset : 0x26A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG6A BREG6A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG6B

Backup Register
address_offset : 0x26B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG6B BREG6B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG6C

Backup Register
address_offset : 0x26C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG6C BREG6C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG6D

Backup Register
address_offset : 0x26D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG6D BREG6D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG6E

Backup Register
address_offset : 0x26E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG6E BREG6E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG6F

Backup Register
address_offset : 0x26F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG6F BREG6F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG70

Backup Register
address_offset : 0x270 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG70 BREG70 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG71

Backup Register
address_offset : 0x271 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG71 BREG71 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG72

Backup Register
address_offset : 0x272 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG72 BREG72 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG73

Backup Register
address_offset : 0x273 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG73 BREG73 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG74

Backup Register
address_offset : 0x274 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG74 BREG74 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG75

Backup Register
address_offset : 0x275 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG75 BREG75 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG76

Backup Register
address_offset : 0x276 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG76 BREG76 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG77

Backup Register
address_offset : 0x277 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG77 BREG77 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG78

Backup Register
address_offset : 0x278 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG78 BREG78 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG79

Backup Register
address_offset : 0x279 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG79 BREG79 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG7A

Backup Register
address_offset : 0x27A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG7A BREG7A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG7B

Backup Register
address_offset : 0x27B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG7B BREG7B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG7C

Backup Register
address_offset : 0x27C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG7C BREG7C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG7D

Backup Register
address_offset : 0x27D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG7D BREG7D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG7E

Backup Register
address_offset : 0x27E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG7E BREG7E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG7F

Backup Register
address_offset : 0x27F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG7F BREG7F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0


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