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HYPERBUS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CSR

MBR0

MBR1

MCR0

MCR1

MTR0

MTR1

GPOR

WPR

TEST

IEN

ISR


CSR

Controller Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RACT RDECERR RTRSERR RRSTOERR RDSSLALL WACT WDECERR WTRSERR WRSTOERR

RACT : Read Transaction Active
bits : 0 - -1 (0 bit)
access : read-only

RDECERR : Decode Error in Read Transaction
bits : 8 - 7 (0 bit)
access : read-only

RTRSERR : Transaction Error in Read Transaction
bits : 9 - 8 (0 bit)
access : read-only

RRSTOERR : RSTO Error in Read Transaction
bits : 10 - 9 (0 bit)
access : read-only

RDSSLALL : RDS Stall Error in Read Transaction
bits : 11 - 10 (0 bit)
access : read-only

WACT : Write Transaction Active
bits : 16 - 15 (0 bit)
access : read-only

WDECERR : Decode Error in Write Transaction
bits : 24 - 23 (0 bit)
access : read-only

WTRSERR : Transaction Error in Write Transaction
bits : 25 - 24 (0 bit)
access : read-only

WRSTOERR : RSTO Error in Write Transaction
bits : 26 - 25 (0 bit)
access : read-only


MBR0

Memory Base Address Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBR0 MBR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBR

MBR : Base address for memory space 0
bits : 0 - 30 (31 bit)
access : read-write


MBR1

Memory Base Address Register 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBR1 MBR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MCR0

Memory Configuration Register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR0 MCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRAPSIZE DEVTYPE CRT ACS CRMO

WRAPSIZE : Wrapped Burst Size
bits : 0 - 0 (1 bit)
access : read-write

DEVTYPE : Device Type
bits : 4 - 3 (0 bit)
access : read-write

CRT : Configuration Register Target
bits : 5 - 4 (0 bit)
access : read-write

ACS : Asymmetry Cache System Support
bits : 16 - 15 (0 bit)
access : read-write

CRMO : Continuous Read Merging Option
bits : 17 - 16 (0 bit)
access : read-write


MCR1

Memory Configuration Register 1
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR1 MCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MTR0

Memory Timing Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTR0 MTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTCY WCSH RCSH WCSS RCSS WCSHI RCSHI

LTCY : Latency Cycle for HyperRAM mode
bits : 0 - 2 (3 bit)
access : read-write

WCSH : Write Chip Select Hold After CK falling Edge
bits : 8 - 10 (3 bit)
access : read-write

RCSH : Read Chip Select Hold After CK falling Edge
bits : 12 - 14 (3 bit)
access : read-write

WCSS : Write Chip Select Setup To Next CK Rising Edge
bits : 16 - 18 (3 bit)
access : read-write

RCSS : Read Chip Select Setup To Next CK Rising Edge
bits : 20 - 22 (3 bit)
access : read-write

WCSHI : Write Chip Select High Between Operations
bits : 24 - 26 (3 bit)
access : read-write

RCSHI : Read Chip Select High Between Operations
bits : 28 - 30 (3 bit)
access : read-write


MTR1

Memory Timing Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTR1 MTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPOR

General Purpose Output Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPOR GPOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPO0 GPO1

GPO0 : General Purpose Output Interface
bits : 0 - -1 (0 bit)
access : read-write

GPO1 : General Purpose Output Interface
bits : 1 - 0 (0 bit)
access : read-write


WPR

Write Protection Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPR WPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WP

WP : Write Protection
bits : 0 - -1 (0 bit)
access : read-write


TEST

Test Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST TEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RVD

RVD : Reserved bit
bits : 0 - -1 (0 bit)
access : read-write


IEN

Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPCINTE INTP

RPCINTE : HyperBus Memory Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

INTP : Interrupt Polarity
bits : 31 - 30 (0 bit)
access : read-write


ISR

Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPCINTS

RPCINTS : HyperBus Memory Interrupt Status
bits : 0 - -1 (0 bit)
access : read-only



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