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GDCSUB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x88 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x13C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x148 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x44 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x48 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x58 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x5C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x78 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x7C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x84 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x104 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x108 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x140 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

LockUnlock

VRamInterruptEnable

vram_LockUnlock

vram_LockStatus

vram_sram_select

vram_aberraddr_s0

vram_aberraddr_s1

vram_arbiter_priority

VRamInterruptClear

VRamInterruptStatus

ExtFlashDevSelect

VRamRemapDisable

PanicSwitch

GDC_ClockDivider

WkupTriggerMask

ClockDomainStatus

LockStatus

dsp_LockUnlock

dsp_LockStatus

dsp0_ClockDivider

dsp0_DomainControl

dsp0_ClockShift

dsp0_PowerEnControl

dsp0_ClockGateModeLock

dsp0_ClockGateControl

SDRAMC_ClockDivider

SDRAMC_DomainControl

HSSPIC_ClockDivider

HSSPIC_DomainControl

RPCC_ClockDivider

RPCC_DomainControl

ConfigClockControl


LockUnlock

Lock Protection Setting register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LockUnlock LockUnlock write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LockUnlock

LockUnlock : Protection key of this address block setting bits
bits : 0 - 30 (31 bit)
access : write-only


VRamInterruptEnable

VRAM ECC error interrupt enable/disable register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRamInterruptEnable VRamInterruptEnable read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VramInterruptEnableSec0 VramInterruptEnableSec1

VramInterruptEnableSec0 : Interrupt control of VRAM ECC error for VRAM port0
bits : 0 - -1 (0 bit)
access : read-write

VramInterruptEnableSec1 : Interrupt control of VRAM ECC error for VRAM port1
bits : 1 - 0 (0 bit)
access : read-write


vram_LockUnlock

VRAM LockUnlock Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

vram_LockUnlock vram_LockUnlock read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vram_LockUnlock

vram_LockUnlock : $
bits : 0 - 30 (31 bit)
access : read-write


vram_LockStatus

$
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

vram_LockStatus vram_LockStatus read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vram_LockStatus vram_PrivilegeStatus vram_FreezeStatus

vram_LockStatus : Current status of lock protection
bits : 0 - -1 (0 bit)
access : read-only

vram_PrivilegeStatus : Current status of previlege protection
bits : 4 - 3 (0 bit)
access : read-only

vram_FreezeStatus : Current status of freeze status
bits : 8 - 7 (0 bit)
access : read-only


vram_sram_select

Size of the ECC protected memory region selection register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

vram_sram_select vram_sram_select read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vram_sram_select

vram_sram_select : Selects the size of the ECC protected region
bits : 0 - 10 (11 bit)
access : read-write


vram_aberraddr_s0

GDC bus address of the read access at S0 interface which had a single-bit ECC error
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

vram_aberraddr_s0 vram_aberraddr_s0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vram_aberraddr_s0

vram_aberraddr_s0 : Indicates address which had an ECC single bit error
bits : 0 - 30 (31 bit)
access : read-only


vram_aberraddr_s1

GDC bus address of the read access at S1 interface which had a single-bit ECC error
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

vram_aberraddr_s1 vram_aberraddr_s1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vram_aberraddr_s1

vram_aberraddr_s1 : Indicates address which had an ECC single bit error
bits : 0 - 30 (31 bit)
access : read-only


vram_arbiter_priority

Register assigns fixed arbitration priorities to each GDC bus slave interface
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

vram_arbiter_priority vram_arbiter_priority read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vram_priority_s0_write vram_priority_s0_read vram_priority_s1_read vram_priority_s2_read

vram_priority_s0_write : set priority of S0 interface for write
bits : 0 - 0 (1 bit)
access : read-write

vram_priority_s0_read : set priority of S0 interface for read
bits : 2 - 2 (1 bit)
access : read-write

vram_priority_s1_read : set priority of S1 interface for read
bits : 4 - 4 (1 bit)
access : read-write

vram_priority_s2_read : for internal device test purpose
bits : 6 - 6 (1 bit)
access : read-write


VRamInterruptClear

VRAM ECC error interrupt clear register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

VRamInterruptClear VRamInterruptClear write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VramInterruptClearSec0 VramInterruptClearSec1

VramInterruptClearSec0 : Clear interrupt of VRAM ECC error for VRAM port0
bits : 0 - -1 (0 bit)
access : write-only

VramInterruptClearSec1 : Clear interrupt of VRAM ECC error for VRAM port1
bits : 1 - 0 (0 bit)
access : write-only


VRamInterruptStatus

VRAM ECC error interrupt status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VRamInterruptStatus VRamInterruptStatus read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VramInterruptStatusSec0 VramInterruptStatusSec1

VramInterruptStatusSec0 : Indicator of VRAM Interrupt status for VRAM port0
bits : 0 - -1 (0 bit)
access : read-only

VramInterruptStatusSec1 : Indicator of VRAM Interrupt status for VRAM port1
bits : 1 - 0 (0 bit)
access : read-only


ExtFlashDevSelect

External Flash Device Selection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ExtFlashDevSelect ExtFlashDevSelect read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ExtFlashDevSelect

ExtFlashDevSelect : External memory device selection bit
bits : 0 - -1 (0 bit)
access : read-write


VRamRemapDisable

VRAM Remap Mode Disable register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRamRemapDisable VRamRemapDisable read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VramRemapDisable

VramRemapDisable : VRAM address remap or non-remap selection bit
bits : 0 - -1 (0 bit)
access : read-write


PanicSwitch

Panic display mode switch register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PanicSwitch PanicSwitch read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PanicSwitch

PanicSwitch : Panic display mode or Normal display mode selection bit
bits : 0 - -1 (0 bit)
access : read-write


GDC_ClockDivider

GDC Clock Generation Control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GDC_ClockDivider GDC_ClockDivider read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GDCClockSelect

GDCClockSelect : GDC clock generation control bits
bits : 8 - 22 (15 bit)
access : read-write


WkupTriggerMask

CPU wake-up trigger Mask register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WkupTriggerMask WkupTriggerMask read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WtrigMaskGe WtrigMaskQspi WtrigMaskSdram WtrigMaskRpc

WtrigMaskGe : Wake up trigger mask for GDC Core
bits : 0 - 17 (18 bit)
access : read-write

WtrigMaskQspi : Wake up trigger mask for QSPI interface
bits : 24 - 23 (0 bit)
access : read-write

WtrigMaskSdram : Wake up trigger mask for SDRAM interface
bits : 25 - 24 (0 bit)
access : read-write

WtrigMaskRpc : Wake up trigger mask for HyperBus interface
bits : 26 - 25 (0 bit)
access : read-write


ClockDomainStatus

Clock Domain Status Indication register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ClockDomainStatus ClockDomainStatus read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DspClockDomainReady SdramClockDomainReady RpcClockDomainReady HsspiClockDomainReady

DspClockDomainReady : Clock Status of Display clock domain
bits : 0 - -1 (0 bit)
access : read-write

SdramClockDomainReady : Clcok Status of SDRAM interface clock domain
bits : 1 - 0 (0 bit)
access : read-write

RpcClockDomainReady : Clock Status of HyperBus interface clock domain
bits : 2 - 1 (0 bit)
access : read-write

HsspiClockDomainReady : Clock Status of QSPI interface clock domain
bits : 3 - 2 (0 bit)
access : read-write


LockStatus

Lock Protection Status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LockStatus LockStatus read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LockStatus PrivilegeStatus FreezStatus

LockStatus : Current status of lock protection
bits : 0 - -1 (0 bit)
access : read-only

PrivilegeStatus : Current status of privilege protection
bits : 4 - 3 (0 bit)
access : read-only

FreezStatus : Current status of freeze status
bits : 8 - 7 (0 bit)
access : read-only


dsp_LockUnlock

Display LockUnlock register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

dsp_LockUnlock dsp_LockUnlock write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp_LockUnlock

dsp_LockUnlock : Protection key of this address block setting bits
bits : 0 - 30 (31 bit)
access : write-only


dsp_LockStatus

Display Lock Status indication register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

dsp_LockStatus dsp_LockStatus read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp_LockStatus dsp_PrivilegeStatus dsp_FreezeStatus

dsp_LockStatus : 0
bits : 0 - -1 (0 bit)
access : read-only

dsp_PrivilegeStatus : Current status of provilege protection
bits : 4 - 3 (0 bit)
access : read-only

dsp_FreezeStatus : Current status of freeze status
bits : 8 - 7 (0 bit)
access : read-only


dsp0_ClockDivider

Display Clock Divider Ration Setting Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dsp0_ClockDivider dsp0_ClockDivider read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ClockDivider

dsp0_ClockDivider : Division ration from the Reference clock for peripherals
bits : 8 - 22 (15 bit)
access : read-write


dsp0_DomainControl

Display clock domain control register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dsp0_DomainControl dsp0_DomainControl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ClockEnable dsp0_SoftwareReset

dsp0_ClockEnable : Display clock output control
bits : 0 - -1 (0 bit)
access : read-write

dsp0_SoftwareReset : Display clock domain software reset
bits : 16 - 15 (0 bit)
access : read-write


dsp0_ClockShift

Register for display clock shift
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dsp0_ClockShift dsp0_ClockShift read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ClockInvert dsp0_ClockOffset

dsp0_ClockInvert : Display clock polarity setting bit
bits : 0 - -1 (0 bit)
access : read-write

dsp0_ClockOffset : Display clock phase setting bits
bits : 16 - 22 (7 bit)
access : read-write


dsp0_PowerEnControl

Register for display Power Enable Signal Control
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dsp0_PowerEnControl dsp0_PowerEnControl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Power_Enable

Power_Enable : Power control of external TFT panel setting bit
bits : 0 - -1 (0 bit)
access : read-write


dsp0_ClockGateModeLock

Display Clock Gate Mode Protection Control register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dsp0_ClockGateModeLock dsp0_ClockGateModeLock read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LockUnlock

LockUnlock : Protection of this address block setting bits
bits : 0 - 30 (31 bit)
access : read-write


dsp0_ClockGateControl

Display Clock Gate Control register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dsp0_ClockGateControl dsp0_ClockGateControl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ClockGate_Enable

ClockGate_Enable : Dot clock for external TFT panel control bit
bits : 0 - -1 (0 bit)
access : read-write


SDRAMC_ClockDivider

Division Ratio of SDRAM interface setting register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRAMC_ClockDivider SDRAMC_ClockDivider read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDRAMC_ClockDivider

SDRAMC_ClockDivider : Division ratio from the Reference clock for peripherals
bits : 8 - 22 (15 bit)
access : read-write


SDRAMC_DomainControl

SDRAM interface clock domain setting register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRAMC_DomainControl SDRAMC_DomainControl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDRAMC_ClockEnable SDRAMC_SoftwareReset

SDRAMC_ClockEnable : SDRAM interface clock output control
bits : 0 - -1 (0 bit)
access : read-write

SDRAMC_SoftwareReset : Software reset for SDRAM interface clock domain
bits : 16 - 15 (0 bit)
access : read-write


HSSPIC_ClockDivider

Division Ratio of QSPI interface setting register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSSPIC_ClockDivider HSSPIC_ClockDivider read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSSPIC_ClockDivider

HSSPIC_ClockDivider : Division Ratio from the Reference clock for peripherals
bits : 8 - 22 (15 bit)
access : read-write


HSSPIC_DomainControl

QSPI interface clock domain setting register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSSPIC_DomainControl HSSPIC_DomainControl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSSPIC_ClockEnable HSSPIC_SoftwareReset

HSSPIC_ClockEnable : QSPI interface clock output control
bits : 0 - -1 (0 bit)
access : read-write

HSSPIC_SoftwareReset : Software reset for QSPI interface clock domain
bits : 16 - 15 (0 bit)
access : read-write


RPCC_ClockDivider

Division Ratio of HyperBus interface setting register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPCC_ClockDivider RPCC_ClockDivider read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPCC_ClockDivider

RPCC_ClockDivider : Division Ratio from the Reference clock for peripherals
bits : 0 - 1 (2 bit)
access : read-write


RPCC_DomainControl

HyperBus interface clock domain setting register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPCC_DomainControl RPCC_DomainControl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPCC_ClockEnable

RPCC_ClockEnable : HyperBus interface clock output control
bits : 0 - -1 (0 bit)
access : read-write


ConfigClockControl

CONFIG Clock control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ConfigClockControl ConfigClockControl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ConfigClockSelect

ConfigClockSelect : CONFIG Clock division ratio setting bits
bits : 0 - 1 (2 bit)
access : read-write



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