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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CSR

CCR


CSR

ADC Common status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD1 EOC1 JEOC1 JSTRT1 STRT1 OVR1 ADONS1

AWD1 : Analog watchdog flag of ADC 1
bits : 0 - 0 (1 bit)

EOC1 : End of conversion of ADC 1
bits : 1 - 1 (1 bit)

JEOC1 : Injected channel end of conversion of ADC 1
bits : 2 - 2 (1 bit)

JSTRT1 : Injected channel Start flag of ADC 1
bits : 3 - 3 (1 bit)

STRT1 : Regular channel Start flag of ADC 1
bits : 4 - 4 (1 bit)

OVR1 : Overrun flag of ADC 1
bits : 5 - 5 (1 bit)

ADONS1 : ADON Status of ADC
bits : 6 - 6 (1 bit)


CCR

ADC common control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCPRE TSVREFE

ADCPRE : ADC prescaler
bits : 16 - 17 (2 bit)

TSVREFE : Temperature sensor and VREFINT enable
bits : 23 - 23 (1 bit)



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