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DS

Peripheral Memory Blocks

address_offset : 0x4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x700 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x704 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x708 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x70C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x710 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x714 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x800 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RCK_CTL

PMD_CTL

WRFSR

WIFSR

WIER

WILVR

DSRAMR

BUR01

BUR02

BUR03

BUR04

BUR05

BUR06

BUR07

BUR08

BUR09

BUR10

BUR11

BUR12

BUR13

BUR14

BUR15

BUR16


RCK_CTL

Sub Clock Control Register [BHW]
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCK_CTL RCK_CTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RTCCKE CECCKE

RTCCKE : RTC clock control bit
bits : 0 - -1 (0 bit)
access : read-write

CECCKE : CEC clock control bit
bits : 1 - 0 (0 bit)
access : read-write


PMD_CTL

RTC Mode Control Register [BHW]
address_offset : 0x700 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMD_CTL PMD_CTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RTCE

RTCE : RTC mode control bit
bits : 0 - -1 (0 bit)
access : read-write


WRFSR

Deep Standby Return Cause Register 1 [BHW]
address_offset : 0x704 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WRFSR WRFSR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WINITX WLVDH

WINITX : INITX pin input reset return bit
bits : 0 - -1 (0 bit)
access : read-only

WLVDH : Low-voltage detection reset return bit
bits : 1 - 0 (0 bit)
access : read-only


WIFSR

Deep Standby Return Cause Register 2 [BHW]
address_offset : 0x708 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WIFSR WIFSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRTCI WLVDI WUI0 WUI1 WUI2 WUI3 WUI4 WUI5

WRTCI : RTC interrupt return bit
bits : 0 - -1 (0 bit)
access : read-only

WLVDI : LVD interrupt return bit
bits : 1 - 0 (0 bit)
access : read-only

WUI0 : WKUP pin input return bit 0
bits : 2 - 1 (0 bit)
access : read-only

WUI1 : WKUP pin input return bit 1
bits : 3 - 2 (0 bit)
access : read-only

WUI2 : WKUP pin input return bit 2
bits : 4 - 3 (0 bit)
access : read-only

WUI3 : WKUP pin input return bit 3
bits : 5 - 4 (0 bit)
access : read-only

WUI4 : WKUP pin input return bit 4
bits : 6 - 5 (0 bit)
access : read-only

WUI5 : WKUP pin input return bit 5
bits : 7 - 6 (0 bit)
access : read-only


WIER

Deep Standby Return Enable Register [BHW]
address_offset : 0x70C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WIER WIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRTCE WLVDE WUI1E WUI2E WUI3E WUI4E WUI5E

WRTCE : RTC interrupt return enable bit
bits : 0 - -1 (0 bit)
access : read-write

WLVDE : LVD interrupt return enable bit
bits : 1 - 0 (0 bit)
access : read-write

WUI1E : WKUP pin input return enable bit 1
bits : 3 - 2 (0 bit)
access : read-write

WUI2E : WKUP pin input return enable bit 2
bits : 4 - 3 (0 bit)
access : read-write

WUI3E : WKUP pin input return enable bit 3
bits : 5 - 4 (0 bit)
access : read-write

WUI4E : WKUP pin input return enable bit 4
bits : 6 - 5 (0 bit)
access : read-write

WUI5E : WKUP pin input return enable bit 5
bits : 7 - 6 (0 bit)
access : read-write


WILVR

WKUP Pin Input Level Register [BHW]
address_offset : 0x710 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WILVR WILVR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WUI1LV WUI2LV WUI3LV WUI4LV WUI5LV

WUI1LV : WKUP pin input level select bit 1
bits : 0 - -1 (0 bit)
access : read-write

WUI2LV : WKUP pin input level select bit 2
bits : 1 - 0 (0 bit)
access : read-write

WUI3LV : WKUP pin input level select bit 3
bits : 2 - 1 (0 bit)
access : read-write

WUI4LV : WKUP pin input level select bit 4
bits : 3 - 2 (0 bit)
access : read-write

WUI5LV : WKUP pin input level select bit 5
bits : 4 - 3 (0 bit)
access : read-write


DSRAMR

Deep Standby RAM Retention Register [BHW]
address_offset : 0x714 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSRAMR DSRAMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SRAMR

SRAMR : On-chip SRAM retention control bits
bits : 0 - 0 (1 bit)
access : read-write


BUR01

Backup Registers from 1 [BHW]
address_offset : 0x800 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR01 BUR01 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR02

Backup Registers from 2 [BHW]
address_offset : 0x801 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR02 BUR02 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR03

Backup Registers from 3 [BHW]
address_offset : 0x802 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR03 BUR03 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR04

Backup Registers from 4 [BHW]
address_offset : 0x803 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR04 BUR04 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR05

Backup Registers from 5 [BHW]
address_offset : 0x804 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR05 BUR05 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR06

Backup Registers from 6 [BHW]
address_offset : 0x805 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR06 BUR06 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR07

Backup Registers from 7 [BHW]
address_offset : 0x806 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR07 BUR07 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR08

Backup Registers from 8 [BHW]
address_offset : 0x807 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR08 BUR08 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR09

Backup Registers from 9 [BHW]
address_offset : 0x808 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR09 BUR09 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR10

Backup Registers from 10 [BHW]
address_offset : 0x809 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR10 BUR10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR11

Backup Registers from 11 [BHW]
address_offset : 0x80A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR11 BUR11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR12

Backup Registers from 12 [BHW]
address_offset : 0x80B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR12 BUR12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR13

Backup Registers from 13 [BHW]
address_offset : 0x80C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR13 BUR13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR14

Backup Registers from 14 [BHW]
address_offset : 0x80D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR14 BUR14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR15

Backup Registers from 15 [BHW]
address_offset : 0x80E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR15 BUR15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUR16

Backup Registers from 16 [BHW]
address_offset : 0x80F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUR16 BUR16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0


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