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USB

Peripheral Memory Blocks

address_offset : 0x2100 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2104 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2108 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x210C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2110 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2114 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2118 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x211C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2120 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2124 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2128 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x212C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2130 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2134 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2138 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x213C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2140 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2144 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2148 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x214C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2150 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2154 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2158 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x215C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2160 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2164 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2168 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x216C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2170 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2174 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

Registers

HCNT

HIRQ

HERR

HSTATE

HFCOMP

HRTIMER

HRTIMER2

HADR

HEOF

HFRAME

HTOKEN

UDCC

EP0C

EP1C

EP2C

EP3C

EP4C

EP5C

TMSP

UDCS

UDCIE

EP0IS

EP0OS

EP1S

EP2S

EP3S

EP4S

EP5S

EP0DT

EP1DT

EP2DT

EP3DT

EP4DT

EP5DT


HCNT

Host Control Register [BHW]
address_offset : 0x2100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCNT HCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOST URST SOFIRE DIRE CNNIRE CMPIRE URIRE RWKIRE RETRY CANCEL SOFSTEP

HOST : host mode bit
bits : 0 - -1 (0 bit)
access : read-write

URST : bus reset bit
bits : 1 - 0 (0 bit)
access : read-write

SOFIRE : SOF interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write

DIRE : device disconnection detection interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write

CNNIRE : device connection detection interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write

CMPIRE : token completion interrupt enable bit
bits : 5 - 4 (0 bit)
access : read-write

URIRE : bus reset interrupt enable bit
bits : 6 - 5 (0 bit)
access : read-write

RWKIRE : resume interrupt enable bit
bits : 7 - 6 (0 bit)
access : read-write

RETRY : retry enable bit
bits : 8 - 7 (0 bit)
access : read-write

CANCEL : token cancellation enable bit
bits : 9 - 8 (0 bit)
access : read-write

SOFSTEP : SOF interrupt occurrence selection bit
bits : 10 - 9 (0 bit)
access : read-write


HIRQ

Host Interrupt Register [BHW]
address_offset : 0x2104 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIRQ HIRQ read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOFIRQ DIRQ CNNIRQ CMPIRQ URIRQ RWKIRQ TCAN

SOFIRQ : SOF starting flag
bits : 0 - -1 (0 bit)
access : read-write

DIRQ : device disconnection detection flag
bits : 1 - 0 (0 bit)
access : read-write

CNNIRQ : device connection detection flag
bits : 2 - 1 (0 bit)
access : read-write

CMPIRQ : token completion flag
bits : 3 - 2 (0 bit)
access : read-write

URIRQ : bus reset end flag
bits : 4 - 3 (0 bit)
access : read-write

RWKIRQ : remote Wake-up end flag
bits : 5 - 4 (0 bit)
access : read-write

TCAN : token cancellation flag
bits : 7 - 6 (0 bit)
access : read-write


HERR

Host Error Status Register [BHW]
address_offset : 0x2105 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HERR HERR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HS STUFF TGERR CRC TOUT RERR LSTSOF

HS : handshake status flags
bits : 0 - 0 (1 bit)
access : read-write

STUFF : stuffing error flag
bits : 2 - 1 (0 bit)
access : read-write

TGERR : toggle error flag
bits : 3 - 2 (0 bit)
access : read-write

CRC : CRC error flag
bits : 4 - 3 (0 bit)
access : read-write

TOUT : timeout flag
bits : 5 - 4 (0 bit)
access : read-write

RERR : receive error flag
bits : 6 - 5 (0 bit)
access : read-write

LSTSOF : lost SOF flag
bits : 7 - 6 (0 bit)
access : read-write


HSTATE

Host Status Register [BHW]
address_offset : 0x2108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTATE HSTATE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CSTAT TMODE SUSP SOFBUSY CLKSEL ALIVE

CSTAT : connection status flag
bits : 0 - -1 (0 bit)
access : read-only

TMODE : transmission mode flag
bits : 1 - 0 (0 bit)
access : read-only

SUSP : suspend setting bit
bits : 2 - 1 (0 bit)
access : read-write

SOFBUSY : SOF busy flag
bits : 3 - 2 (0 bit)
access : read-write

CLKSEL : USB operation clock selection bit
bits : 4 - 3 (0 bit)
access : read-write

ALIVE : specify the keep-alive function in the low-speed mode
bits : 5 - 4 (0 bit)
access : read-write


HFCOMP

SOF Interrupt Frame Compare Register [BHW]
address_offset : 0x2109 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFCOMP HFCOMP read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FRAMECOMP

FRAMECOMP : frame compare data
bits : 0 - 6 (7 bit)
access : read-write


HRTIMER

Retry Timer Setup Register [BHW]
address_offset : 0x210C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HRTIMER HRTIMER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTIMER

RTIMER : retry timer setting
bits : 0 - 14 (15 bit)
access : read-write


HRTIMER2

Retry Timer Setup Register 2 [BHW]
address_offset : 0x2110 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HRTIMER2 HRTIMER2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RTIMER2

RTIMER2 : retry timer setting 2
bits : 0 - 0 (1 bit)
access : read-write


HADR

Host Address Register [BHW]
address_offset : 0x2111 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HADR HADR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : Host Address
bits : 0 - 5 (6 bit)
access : read-write


HEOF

EOF Setup Register [BHW]
address_offset : 0x2114 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HEOF HEOF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HEOF

HEOF : End Frame
bits : 0 - 12 (13 bit)
access : read-write


HFRAME

Frame Setup Register [BHW]
address_offset : 0x2118 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFRAME HFRAME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAME

FRAME : Frame Setup
bits : 0 - 9 (10 bit)
access : read-write


HTOKEN

Host Token Endpoint Register [BHW]
address_offset : 0x211C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HTOKEN HTOKEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ENDPT TKNEN TGGL

ENDPT : endpoint bits
bits : 0 - 2 (3 bit)
access : read-write

TKNEN : token enable bits
bits : 4 - 5 (2 bit)
access : read-write

TGGL : toggle bit
bits : 7 - 6 (0 bit)
access : read-write


UDCC

UDC Control Register [BHW]
address_offset : 0x2120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDCC UDCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWC RFBK STALCLREN USTP HCONX RESUM RST

PWC : Power Control bit
bits : 0 - -1 (0 bit)
access : read-write

RFBK : Data Toggle Mode Select bit
bits : 1 - 0 (0 bit)
access : read-write

STALCLREN : Endpoint 1 to 5 STAL bit Clear Select bit
bits : 3 - 2 (0 bit)
access : read-write

USTP : USB Operating Clock Stop bit
bits : 4 - 3 (0 bit)
access : read-write

HCONX : Host Connection bit
bits : 5 - 4 (0 bit)
access : read-write

RESUM : Resume Setting bit
bits : 6 - 5 (0 bit)
access : read-write

RST : Function Reset bit
bits : 7 - 6 (0 bit)
access : read-write


EP0C

EP0 Control Register [HW]
address_offset : 0x2124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP0C EP0C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKS STAL

PKS : Packet Size Endpoint 0 Setting bits
bits : 0 - 5 (6 bit)
access : read-write

STAL : Endpoint 0 Stall Setting bit
bits : 9 - 8 (0 bit)
access : read-write


EP1C

EP1 Control Register [HW]
address_offset : 0x2128 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP1C EP1C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKS STAL NULE DMAE DIR TYPE EPEN

PKS : Packet Size Setting bits
bits : 0 - 7 (8 bit)
access : read-write

STAL : Endpoint Stall Setting bit
bits : 9 - 8 (0 bit)
access : read-write

NULE : Null Automatic Transfer Enable bit
bits : 10 - 9 (0 bit)
access : read-write

DMAE : DMA Automatic Transfer Enable bit
bits : 11 - 10 (0 bit)
access : read-write

DIR : Endpoint Transfer Direction Select bit
bits : 12 - 11 (0 bit)
access : read-write

TYPE : Endpoint Transfer Type Select bits
bits : 13 - 13 (1 bit)
access : read-write

EPEN : Endpoint Enable bit
bits : 15 - 14 (0 bit)
access : read-write


EP2C

EP2 Control Register [HW]
address_offset : 0x212C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP2C EP2C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKS STAL NULE DMAE DIR TYPE EPEN

PKS : Packet Size Setting bits
bits : 0 - 5 (6 bit)
access : read-write

STAL : Endpoint Stall Setting bit
bits : 9 - 8 (0 bit)
access : read-write

NULE : Null Automatic Transfer Enable bit
bits : 10 - 9 (0 bit)
access : read-write

DMAE : DMA Automatic Transfer Enable bit
bits : 11 - 10 (0 bit)
access : read-write

DIR : Endpoint Transfer Direction Select bit
bits : 12 - 11 (0 bit)
access : read-write

TYPE : Endpoint Transfer Type Select bits
bits : 13 - 13 (1 bit)
access : read-write

EPEN : Endpoint Enable bit
bits : 15 - 14 (0 bit)
access : read-write


EP3C

EP3 Control Register [HW]
address_offset : 0x2130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP3C EP3C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EP4C

EP4 Control Register [HW]
address_offset : 0x2134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP4C EP4C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EP5C

EP5 Control Register [HW]
address_offset : 0x2138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP5C EP5C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMSP

Time Stamp Register [HW]
address_offset : 0x213C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TMSP TMSP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMSP

TMSP : Time Stamp bits
bits : 0 - 9 (10 bit)
access : read-only


UDCS

UDC Status Register [BHW]
address_offset : 0x2140 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDCS UDCS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CONF SETP WKUP BRST SOF SUSP

CONF : Configuration Detection bit
bits : 0 - -1 (0 bit)
access : read-write

SETP : Setup Stage Detection bit
bits : 1 - 0 (0 bit)
access : read-write

WKUP : Wake-up Detection bit
bits : 2 - 1 (0 bit)
access : read-write

BRST : Bus Reset Detection bit
bits : 3 - 2 (0 bit)
access : read-write

SOF : SOF Detection bit
bits : 4 - 3 (0 bit)
access : read-write

SUSP : Suspend detection bit
bits : 5 - 4 (0 bit)
access : read-write


UDCIE

UDC Interrupt Enable Register [BHW]
address_offset : 0x2141 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDCIE UDCIE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CONFIE CONFN WKUPIE BRSTIE SOFIE SUSPIE

CONFIE : Configuration Interrupt Enable bit
bits : 0 - -1 (0 bit)
access : read-write

CONFN : Configuration Number Indication bit
bits : 1 - 0 (0 bit)
access : read-only

WKUPIE : Wake-up Interrupt Enable bit
bits : 2 - 1 (0 bit)
access : read-write

BRSTIE : Bus Reset Enable bit
bits : 3 - 2 (0 bit)
access : read-write

SOFIE : SOF Reception Interrupt Enable bit
bits : 4 - 3 (0 bit)
access : read-write

SUSPIE : Suspend Interrupt Enable bit
bits : 5 - 4 (0 bit)
access : read-write


EP0IS

EP0I Status Register [HW]
address_offset : 0x2144 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP0IS EP0IS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRQI DRQIIE BFINI

DRQI : Send/Receive Data Interrupt Request bit
bits : 10 - 9 (0 bit)
access : read-write

DRQIIE : Send Data Interrupt Enable bit
bits : 14 - 13 (0 bit)
access : read-write

BFINI : Send Buffer Initialization bit
bits : 15 - 14 (0 bit)
access : read-write


EP0OS

EP0O Status Register [HW]
address_offset : 0x2148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP0OS EP0OS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE SPK DRQO SPKIE DRQOIE BFINI

SIZE : Packet Size Indication bit
bits : 0 - 5 (6 bit)
access : read-only

SPK : Short Packet Interrupt Request bit
bits : 9 - 8 (0 bit)
access : read-write

DRQO : Receive Data Interrupt Request bit
bits : 10 - 9 (0 bit)
access : read-write

SPKIE : Short Packet Interrupt Enable bit
bits : 13 - 12 (0 bit)
access : read-write

DRQOIE : Receive Data Interrupt Enable bit
bits : 14 - 13 (0 bit)
access : read-write

BFINI : Receive Buffer Initialization bit
bits : 15 - 14 (0 bit)
access : read-write


EP1S

EP1 Status Register [HW]
address_offset : 0x214C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP1S EP1S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE SPK DRQ BUSY SPKIE DRQIE BFINI

SIZE : packet SIZE
bits : 0 - 7 (8 bit)
access : read-only

SPK : Short Packet Interrupt Request bit
bits : 9 - 8 (0 bit)
access : read-write

DRQ : Packet Transfer Interrupt Request bit
bits : 10 - 9 (0 bit)
access : read-write

BUSY : Busy Flag bit
bits : 11 - 10 (0 bit)
access : read-only

SPKIE : Short Packet Interrupt Enable bit
bits : 13 - 12 (0 bit)
access : read-write

DRQIE : Packet Transfer Interrupt Enable bit
bits : 14 - 13 (0 bit)
access : read-write

BFINI : Send/Receive Buffer Initialization bit
bits : 15 - 14 (0 bit)
access : read-write


EP2S

EP2 Status Register [HW]
address_offset : 0x2150 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP2S EP2S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE SPK DRQ BUSY SPKIE DRQIE BFINI

SIZE : packet SIZE
bits : 0 - 5 (6 bit)
access : read-only

SPK : Short Packet Interrupt Request bit
bits : 9 - 8 (0 bit)
access : read-write

DRQ : Packet Transfer Interrupt Request bit
bits : 10 - 9 (0 bit)
access : read-write

BUSY : Busy Flag bit
bits : 11 - 10 (0 bit)
access : read-only

SPKIE : Short Packet Interrupt Enable bit
bits : 13 - 12 (0 bit)
access : read-write

DRQIE : Packet Transfer Interrupt Enable bit
bits : 14 - 13 (0 bit)
access : read-write

BFINI : Send/Receive Buffer Initialization bit
bits : 15 - 14 (0 bit)
access : read-write


EP3S

EP3 Status Register [HW]
address_offset : 0x2154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP3S EP3S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EP4S

EP4 Status Register [HW]
address_offset : 0x2158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP4S EP4S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EP5S

EP5 Status Register [HW]
address_offset : 0x215C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP5S EP5S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EP0DT

EP0 Data Register [BHW]
address_offset : 0x2160 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP0DT EP0DT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BFDT

BFDT : Endpoint Send/Receive Buffer Data
bits : 0 - 14 (15 bit)
access : read-write


EP1DT

EP1 Data Register [BHW]
address_offset : 0x2164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP1DT EP1DT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EP2DT

EP2 Data Register [BHW]
address_offset : 0x2168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP2DT EP2DT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EP3DT

EP3 Data Register [BHW]
address_offset : 0x216C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP3DT EP3DT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EP4DT

EP4 Data Register [BHW]
address_offset : 0x2170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP4DT EP4DT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EP5DT

EP5 Data Register [BHW]
address_offset : 0x2174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP5DT EP5DT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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