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SDIF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x55 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xE0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x58 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xFC Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x118 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x154 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SSA2

SRESP0

AHBCFGL

AHBCFGH

SPWSWCL

SPWSWCH

STUNSETL

STUNSETH

STUNSTL

STUNSTH

PSWISTL

PSWISTH

PSWISTEL

PSWISTEH

SRESP1

PSWISGEL

PSWISGEH

MMCSDCL

MMCSDCH

MCWIRQC0

MCWIRQC1

MCWIRQC2

MCWIRQC3

MCRPCKBL

MCRPCKBH

SRESP2

SCDETECS

SRESP3

SRESP4

SRESP5

SRESP6

SRESP7

SBUFDP

SPRSTAT

SHCTL1

SPWRCTL

SBLKGPCTL

SWKUPCTL

SCLKCTL

STOCTL

SSRST

SNINTST

SEINTST

SNINTSTE

SEINTSTE

SNINTSGE

SEINTSGE

SACMDEST

SHCTL2

SBSIZE

CAPBLTY0

CAPBLTY1

CAPBLTY2

CAPBLTY3

MXCCAPY0

MXCCAPY1

MXCCAPY2

MXCCAPY3

FEACEST

SFEEIST

ADMAEST

SADSA0

SADSA1

SADSA2

SADSA3

SBLCNT

SPRVAL0

SPRVAL1

SPRVAL2

SPRVAL3

SPRVAL4

SPRVAL5

SPRVAL6

SPRVAL7

SSA1

STRSFMD

SCMMD

SSHBCTLL

SSHBCTLH

SSLIST

SHCTLV


SSA2

SDMA System Address / Argument 2 Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSA2 SSA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRESP0

Response Register 0 [BHW]
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRESP0 SRESP0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AHBCFGL

AHB Config Register L [BHW]
address_offset : 0x100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBCFGL AHBCFGL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INCRSEL SINEN BSLOCK BSLOCKSEL ENDIANSEL

INCRSEL : AHB fixed length burst type Select
bits : 0 - 1 (2 bit)
access : read-write

SINEN : Burst type for byte transfer Select
bits : 3 - 2 (0 bit)
access : read-write

BSLOCK : Bus Lock Function
bits : 4 - 3 (0 bit)
access : read-write

BSLOCKSEL : Bus Lock Select
bits : 5 - 4 (0 bit)
access : read-write

ENDIANSEL : Big/Little Endian Select
bits : 6 - 5 (0 bit)
access : read-write


AHBCFGH

AHB Config Registe H [BHW]
address_offset : 0x102 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBCFGH AHBCFGH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPWSWCL

Power Switching Register L [BHW]
address_offset : 0x104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPWSWCL SPWSWCL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATPWRSWEN IOREGSEL

ATPWRSWEN : Auto Power Switching Select
bits : 0 - -1 (0 bit)
access : read-write

IOREGSEL : I/O Register Selecting
bits : 1 - 0 (0 bit)
access : read-write


SPWSWCH

Power Switching Register H [BHW]
address_offset : 0x106 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPWSWCH SPWSWCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

STUNSETL

Tuning Setting Register L [BHW]
address_offset : 0x108 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STUNSETL STUNSETL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TNPTSEL TNPHSELEN TNERRBDSEL RETNTAPSEL RETNRNGSEL

TNPTSEL : Tuning Point Select
bits : 0 - 6 (7 bit)
access : read-write

TNPHSELEN : Tuning Phase Select Enable
bits : 8 - 7 (0 bit)
access : read-write

TNERRBDSEL : Tuning Error Border Select
bits : 9 - 8 (0 bit)
access : read-write

RETNTAPSEL : Re-Tuning Tap Select
bits : 10 - 9 (0 bit)
access : read-write

RETNRNGSEL : Re-Tuning Range Select
bits : 11 - 11 (1 bit)
access : read-write


STUNSETH

Tuning Setting Register H [BHW]
address_offset : 0x10A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STUNSETH STUNSETH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDCFCHKDS DTOTCNTVAL

CMDCFCHKDS : CMD Conflict Check Disable
bits : 0 - -1 (0 bit)
access : read-write

DTOTCNTVAL : Data Timeout Counter Value For Auto Re-Tuning
bits : 8 - 10 (3 bit)
access : read-write


STUNSTL

Tuning Status Register L [BHW]
address_offset : 0x10C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STUNSTL STUNSTL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REP8TNRSLT REP3TNRSLT

REP8TNRSLT : 8 Phase Tuning / Re-Tuning Result
bits : 0 - 6 (7 bit)
access : read-only

REP3TNRSLT : 3 Phase Re-Tuning Result
bits : 8 - 9 (2 bit)
access : read-only


STUNSTH

Tuning Status Register H [BHW]
address_offset : 0x10E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STUNSTH STUNSTH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSTTNPNT

PRSTTNPNT : Present Tuning point
bits : 0 - 6 (7 bit)
access : read-only


PSWISTL

Power Switching Interrupt Status Register L [BHW]
address_offset : 0x118 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSWISTL PSWISTL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT5MS INT1MS

INT5MS : 5ms Wait Interrupt
bits : 0 - -1 (0 bit)
access : read-only

INT1MS : 1ms Wait Interrupt
bits : 1 - 0 (0 bit)
access : read-only


PSWISTH

Power Switching Interrupt Status Register H [BHW]
address_offset : 0x11A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSWISTH PSWISTH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PSWISTEL

Power Switching Interrupt Status Enable Register L [BHW]
address_offset : 0x11C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSWISTEL PSWISTEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT5MSSTS INT1MSSTS

INT5MSSTS : 5ms Wait Interrupt Status Enable
bits : 0 - -1 (0 bit)
access : read-write

INT1MSSTS : 1ms Wait Interrupt Status Enable
bits : 1 - 0 (0 bit)
access : read-write


PSWISTEH

Power Switching Interrupt Status Enable Register H [BHW]
address_offset : 0x11E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSWISTEH PSWISTEH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRESP1

Response Register 1 [BHW]
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRESP1 SRESP1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PSWISGEL

Power Switching Interrupt Signal Enable Register L [BHW]
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSWISGEL PSWISGEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT5MSSGEN INT1MSSGEN

INT5MSSGEN : 5ms Wait Interrupt Signal Enable
bits : 0 - -1 (0 bit)
access : read-write

INT1MSSGEN : 1ms Wait Interrupt Signal Enable
bits : 1 - 0 (0 bit)
access : read-write


PSWISGEH

Power Switching Interrupt Signal Enable Register H [BHW]
address_offset : 0x122 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSWISGEH PSWISGEH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MMCSDCL

MMC/eSD Control Register L [BHW]
address_offset : 0x124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMCSDCL MMCSDCL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCKRSTESD RSTMMC VCCCTLMMC VCCQCTLMMC MMCDDRSEL CMDDATDLY

LCKRSTESD : Lock-Reset Control for MMC
bits : 0 - -1 (0 bit)
access : read-write

RSTMMC : RST_n Control for MMC
bits : 1 - 0 (0 bit)
access : read-write

VCCCTLMMC : VCC Control for MMC
bits : 2 - 1 (0 bit)
access : read-write

VCCQCTLMMC : VCCQ Control for MMC
bits : 3 - 2 (0 bit)
access : read-write

MMCDDRSEL : MMC DDR Select
bits : 8 - 7 (0 bit)
access : read-write

CMDDATDLY : CMD / DAT Delay Select
bits : 9 - 8 (0 bit)
access : read-write


MMCSDCH

MMC/eSD Control Register H [BHW]
address_offset : 0x126 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMCSDCH MMCSDCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTACKENMMC BTABTENMMC BTMDENMMC

BTACKENMMC : Boot Ack Enable for MMC
bits : 0 - -1 (0 bit)
access : read-write

BTABTENMMC : Boot Auto Abort Enable for MMC
bits : 1 - 0 (0 bit)
access : read-write

BTMDENMMC : Boot Mode Enable for MMC
bits : 2 - 1 (0 bit)
access : read-write


MCWIRQC0

MMC Wait IRQ Control Register 0 [BHW]
address_offset : 0x128 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCWIRQC0 MCWIRQC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTIRQEN WTIRQST

WTIRQEN : Wait IRQ Enable
bits : 0 - -1 (0 bit)
access : read-write

WTIRQST : Wait IRQ State
bits : 1 - 0 (0 bit)
access : read-write


MCWIRQC1

MMC Wait IRQ Control Register 1 [BHW]
address_offset : 0x12A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCWIRQC1 MCWIRQC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTIRQCNCLR

WTIRQCNCLR : Wait IRQ Cancel Response
bits : 0 - 14 (15 bit)
access : read-write


MCWIRQC2

MMC Wait IRQ Control Register 2 [BHW]
address_offset : 0x12C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCWIRQC2 MCWIRQC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTIRQCNCLR

WTIRQCNCLR : Wait IRQ Cancel Response
bits : 0 - 14 (15 bit)
access : read-write


MCWIRQC3

MMC Wait IRQ Control Register 3 [BHW]
address_offset : 0x12E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCWIRQC3 MCWIRQC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTIRQCNCLR

WTIRQCNCLR : Wait IRQ Cancel Response
bits : 0 - 14 (15 bit)
access : read-write


MCRPCKBL

MMC Response Check Bit Register L [BHW]
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MCRPCKBL MCRPCKBL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHECKBIT1 CHECKBIT2

CHECKBIT1 : Check Bit 1
bits : 0 - 5 (6 bit)
access : read-only

CHECKBIT2 : Check Bit 2
bits : 7 - 11 (5 bit)
access : read-only


MCRPCKBH

MMC Response Check Bit Register H [BHW]
address_offset : 0x132 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MCRPCKBH MCRPCKBH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRESP2

Response Register 2 [BHW]
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRESP2 SRESP2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCDETECS

Card Detect Setting Register [BHW]
address_offset : 0x154 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SCDETECS SCDETECS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDDEBTCVAL

CDDEBTCVAL : Card Detect Debounce Timer Counter Value
bits : 8 - 10 (3 bit)
access : read-only


SRESP3

Response Register 3 [BHW]
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRESP3 SRESP3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRESP4

Response Register 4 [BHW]
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRESP4 SRESP4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRESP5

Response Register 5 [BHW]
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRESP5 SRESP5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRESP6

Response Register 6 [BHW]
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRESP6 SRESP6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRESP7

Response Register 7 [BHW]
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRESP7 SRESP7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SBUFDP

Buffer Data Port Register [BHW]
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SBUFDP SBUFDP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPRSTAT

Present State Register [BHW]
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPRSTAT SPRSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDINH CMDDATINH DATLNACT RETUNEREQ WRTRSFACT RDTRSFACT BUFWREN BUFRDEN CARDINS CARDSTB CARDDET WPPINLVL LNSGNLVL CMDLNSGN

CMDINH : Command Inhibit (CMD)
bits : 0 - -1 (0 bit)
access : read-only

CMDDATINH : Command Inhibit (DAT)
bits : 1 - 0 (0 bit)
access : read-only

DATLNACT : DAT Line Active
bits : 2 - 1 (0 bit)
access : read-only

RETUNEREQ : Re-Tuning Request
bits : 3 - 2 (0 bit)
access : read-only

WRTRSFACT : Write Transfer Active
bits : 8 - 7 (0 bit)
access : read-only

RDTRSFACT : Read Transfer Active
bits : 9 - 8 (0 bit)
access : read-only

BUFWREN : Buffer Write Enable
bits : 10 - 9 (0 bit)
access : read-only

BUFRDEN : Buffer Read Enable
bits : 11 - 10 (0 bit)
access : read-only

CARDINS : Card Inserted
bits : 16 - 15 (0 bit)
access : read-only

CARDSTB : Card State Stable
bits : 17 - 16 (0 bit)
access : read-only

CARDDET : Card Detect Pin Level
bits : 18 - 17 (0 bit)
access : read-only

WPPINLVL : Write Protect Switch Pin Level
bits : 19 - 18 (0 bit)
access : read-only

LNSGNLVL : DAT Line Signal Level
bits : 20 - 22 (3 bit)
access : read-only

CMDLNSGN : CMD Line Signal Level
bits : 24 - 23 (0 bit)
access : read-only


SHCTL1

Host Control 1 Register [BHW]
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHCTL1 SHCTL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LEDCTRL DATAWIDTH HIGHSPDEN DMASEL EXTDTWIDTH CDTSTLVL CDSGNSEL

LEDCTRL : LED Control
bits : 0 - -1 (0 bit)
access : read-write

DATAWIDTH : Data Transfer Width
bits : 1 - 0 (0 bit)
access : read-write

HIGHSPDEN : High Speed Enable
bits : 2 - 1 (0 bit)
access : read-write

DMASEL : DMA Select
bits : 3 - 3 (1 bit)
access : read-write

EXTDTWIDTH : Extended Data Transfer Width
bits : 5 - 4 (0 bit)
access : read-write

CDTSTLVL : Card Detect Test Level
bits : 6 - 5 (0 bit)
access : read-write

CDSGNSEL : Card Detect Signal Selection
bits : 7 - 6 (0 bit)
access : read-write


SPWRCTL

Power Control Register [BHW]
address_offset : 0x29 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPWRCTL SPWRCTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SDBUSPWR SDBUSVLSEL

SDBUSPWR : SD Bus Power
bits : 0 - -1 (0 bit)
access : read-write

SDBUSVLSEL : SD Bus Voltage Select
bits : 1 - 2 (2 bit)
access : read-write


SBLKGPCTL

Block Gap Control Register [BHW]
address_offset : 0x2A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SBLKGPCTL SBLKGPCTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BLCKGSTPREQ CONTREQ RDWAITCTL BLCKGAPINT

BLCKGSTPREQ : Stop At Block Gap Request
bits : 0 - -1 (0 bit)
access : read-write

CONTREQ : Continue Request
bits : 1 - 0 (0 bit)
access : read-write

RDWAITCTL : Read Wait Control
bits : 2 - 1 (0 bit)
access : read-write

BLCKGAPINT : Interrupt At Block Gap
bits : 3 - 2 (0 bit)
access : read-write


SWKUPCTL

Wakeup Control Register [BHW]
address_offset : 0x2B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWKUPCTL SWKUPCTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WKUPEVNTEN0 WKUPEVNTEN1 WKUPEVNTEN2

WKUPEVNTEN0 : Wakeup Event Enable On SD Card Interrupt
bits : 0 - -1 (0 bit)
access : read-write

WKUPEVNTEN1 : Wakeup Event Enable On SD Card Insertion
bits : 1 - 0 (0 bit)
access : read-write

WKUPEVNTEN2 : Wakeup Event Enable On SD Card Removal
bits : 2 - 1 (0 bit)
access : read-write


SCLKCTL

Clock Control Register [BHW]
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCLKCTL SCLKCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTLCLCKEN INTLCLCKST SDCLCKEN CLCKGENSEL UPSDCLKSEL SDCLKSEL

INTLCLCKEN : Internal Clock Enable
bits : 0 - -1 (0 bit)
access : read-write

INTLCLCKST : Internal Clock Stable
bits : 1 - 0 (0 bit)
access : read-only

SDCLCKEN : SD Clock Enable
bits : 2 - 1 (0 bit)
access : read-write

CLCKGENSEL : Clock Generator Select
bits : 5 - 4 (0 bit)
access : read-write

UPSDCLKSEL : Upper Bits of SDCLK Frequency Select
bits : 6 - 6 (1 bit)
access : read-write

SDCLKSEL : SDCLK Frequency Select
bits : 8 - 14 (7 bit)
access : read-write


STOCTL

Timeout Control Register [BHW]
address_offset : 0x2E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STOCTL STOCTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTTMOUTVAL

DTTMOUTVAL : Data Timeout Counter Value
bits : 0 - 2 (3 bit)
access : read-write


SSRST

Software Reset Register [BHW]
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSRST SSRST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRSTALL SWRSTCMDLN SWRSTDATLN

SWRSTALL : Software Reset for All
bits : 0 - -1 (0 bit)
access : read-write

SWRSTCMDLN : Software Reset for CMD Line
bits : 1 - 0 (0 bit)
access : read-write

SWRSTDATLN : Software Reset for DAT Line
bits : 2 - 1 (0 bit)
access : read-write


SNINTST

Normal Interrupt Status Register [BHW]
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SNINTST SNINTST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDCMPLT TRSFCMPLT BLCKGEVNT DMAINT BUFWRRDY BUFRDRDY CARDINS CARDRMV CARDINT INT_A INT_B INT_C RETUNEEVT ERRORINT

CMDCMPLT : Command Complete
bits : 0 - -1 (0 bit)
access : read-only

TRSFCMPLT : Transfer Complete
bits : 1 - 0 (0 bit)
access : read-only

BLCKGEVNT : Block Gap Event
bits : 2 - 1 (0 bit)
access : read-only

DMAINT : DMA Interrupt
bits : 3 - 2 (0 bit)
access : read-only

BUFWRRDY : Buffer Write Ready
bits : 4 - 3 (0 bit)
access : read-only

BUFRDRDY : Buffer Read Ready
bits : 5 - 4 (0 bit)
access : read-only

CARDINS : Card Insertion
bits : 6 - 5 (0 bit)
access : read-only

CARDRMV : Card Removal
bits : 7 - 6 (0 bit)
access : read-only

CARDINT : Card Interrupt
bits : 8 - 7 (0 bit)
access : read-only

INT_A : INT_A Interrupt
bits : 9 - 8 (0 bit)
access : read-only

INT_B : INT_B Interrupt
bits : 10 - 9 (0 bit)
access : read-only

INT_C : INT_C Interrupt
bits : 11 - 10 (0 bit)
access : read-only

RETUNEEVT : Re-Tuning Event
bits : 12 - 11 (0 bit)
access : read-only

ERRORINT : Error Interrupt
bits : 15 - 14 (0 bit)
access : read-only


SEINTST

Error Interrupt Status Register [BHW]
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SEINTST SEINTST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDTOERR CMDCRCERR CMDEBERR CMDIDXERR DTTOERR DTCRCERR DTEBERR CRTLMTERR ACMD12ERR ADMAERR TUNINGERR BTACKERR ACMD19ERR AHBMSTERR

CMDTOERR : Command Timeout Error
bits : 0 - -1 (0 bit)
access : read-only

CMDCRCERR : Command CRC Error
bits : 1 - 0 (0 bit)
access : read-only

CMDEBERR : Command End Bit Error
bits : 2 - 1 (0 bit)
access : read-only

CMDIDXERR : Command Index Error
bits : 3 - 2 (0 bit)
access : read-only

DTTOERR : Data Timeout Error
bits : 4 - 3 (0 bit)
access : read-only

DTCRCERR : Data CRC Error
bits : 5 - 4 (0 bit)
access : read-only

DTEBERR : Data End Bit Error
bits : 6 - 5 (0 bit)
access : read-only

CRTLMTERR : Current Limit Error
bits : 7 - 6 (0 bit)
access : read-only

ACMD12ERR : Auto CMD12 Error
bits : 8 - 7 (0 bit)
access : read-only

ADMAERR : ADMA Error
bits : 9 - 8 (0 bit)
access : read-only

TUNINGERR : Tuning Error
bits : 10 - 9 (0 bit)
access : read-only

BTACKERR : Boot Acknowledge Error
bits : 12 - 11 (0 bit)
access : read-only

ACMD19ERR : Auto CMD19 Error
bits : 13 - 12 (0 bit)
access : read-only

AHBMSTERR : AHB Master Error
bits : 14 - 13 (0 bit)
access : read-only


SNINTSTE

Normal Interrupt Status Enable Register [BHW]
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNINTSTE SNINTSTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDCMPLTS TRSFCMPLTS BLCKGEVNTS DMAINTS BUFWRRDYS BUFRDRDYS CARDINSS CARDRMVS CARDINTS INT_AS INT_BS INT_CS RETUNEEVTS

CMDCMPLTS : Command Complete Status Enable
bits : 0 - -1 (0 bit)
access : read-write

TRSFCMPLTS : Transfer Complete Status Enable
bits : 1 - 0 (0 bit)
access : read-write

BLCKGEVNTS : Block Gap Event Status Enable
bits : 2 - 1 (0 bit)
access : read-write

DMAINTS : DMA Interrupt Status Enable
bits : 3 - 2 (0 bit)
access : read-write

BUFWRRDYS : Buffer Write Ready Status Enable
bits : 4 - 3 (0 bit)
access : read-write

BUFRDRDYS : Buffer Read Ready Status Enable
bits : 5 - 4 (0 bit)
access : read-write

CARDINSS : Card Insertion Status Enable
bits : 6 - 5 (0 bit)
access : read-write

CARDRMVS : Card Removal Status Enable
bits : 7 - 6 (0 bit)
access : read-write

CARDINTS : Card Interrupt Status Enable
bits : 8 - 7 (0 bit)
access : read-write

INT_AS : INT_A Status Enable
bits : 9 - 8 (0 bit)
access : read-write

INT_BS : INT_B Status Enable
bits : 10 - 9 (0 bit)
access : read-write

INT_CS : INT_C Status Enable
bits : 11 - 10 (0 bit)
access : read-write

RETUNEEVTS : Re-Tuning Event Status Enable
bits : 12 - 11 (0 bit)
access : read-write


SEINTSTE

Error Interrupt Status Enable Register [BHW]
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEINTSTE SEINTSTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDTOERRS CMDCRCERRS CMDEBERRS CMDIDXERRS DTTOERRS DTCRCERRS DTEBERRS CRTLMTERRS ACMD12ERRS ADMAERRS TUNINGERRS BTACKERRS ACMD19ERRS AHBMSTERRS

CMDTOERRS : Command Timeout Error Status Enable
bits : 0 - -1 (0 bit)
access : read-write

CMDCRCERRS : Command CRC Error Status Enable
bits : 1 - 0 (0 bit)
access : read-write

CMDEBERRS : Command End Bit Error Status Enable
bits : 2 - 1 (0 bit)
access : read-write

CMDIDXERRS : Command Index Error Status Enable
bits : 3 - 2 (0 bit)
access : read-write

DTTOERRS : Data Timeout Error Status Enable
bits : 4 - 3 (0 bit)
access : read-write

DTCRCERRS : Data CRC Error Status Enable
bits : 5 - 4 (0 bit)
access : read-write

DTEBERRS : Data End Bit Error Status Enable
bits : 6 - 5 (0 bit)
access : read-write

CRTLMTERRS : Current limit Error Status Enable
bits : 7 - 6 (0 bit)
access : read-write

ACMD12ERRS : Auto CMD Error Status Enable
bits : 8 - 7 (0 bit)
access : read-write

ADMAERRS : ADMA Error Status Enable
bits : 9 - 8 (0 bit)
access : read-write

TUNINGERRS : Tuning Error Status Enable
bits : 10 - 9 (0 bit)
access : read-write

BTACKERRS : Boot Acknowledge Error Status Enable
bits : 12 - 11 (0 bit)
access : read-write

ACMD19ERRS : Auto CMD19 Error Status Enable
bits : 13 - 12 (0 bit)
access : read-write

AHBMSTERRS : AHB Master Error Status Enable
bits : 14 - 13 (0 bit)
access : read-write


SNINTSGE

Normal Interrupt Signal Enable Register [BHW]
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNINTSGE SNINTSGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDCMPLTG TRSFCMPLTG BLCKGEVNTG DMAINTG BUFWRRDYG BUFRDRDYG CARDINSG CARDRMVG CARDINTG INT_AG INT_BG INT_CG RETUNEEVTG

CMDCMPLTG : Command Complete Signal Enable
bits : 0 - -1 (0 bit)
access : read-write

TRSFCMPLTG : Transfer Complete Signal Enable
bits : 1 - 0 (0 bit)
access : read-write

BLCKGEVNTG : Block Gap Event Signal Enable
bits : 2 - 1 (0 bit)
access : read-write

DMAINTG : DMA Interrupt Signal Enable
bits : 3 - 2 (0 bit)
access : read-write

BUFWRRDYG : Buffer Write Ready Signal Enable
bits : 4 - 3 (0 bit)
access : read-write

BUFRDRDYG : Buffer Read Ready Signal Enable
bits : 5 - 4 (0 bit)
access : read-write

CARDINSG : Card Insertion Signal Enable
bits : 6 - 5 (0 bit)
access : read-write

CARDRMVG : Card Removal Signal Enable
bits : 7 - 6 (0 bit)
access : read-write

CARDINTG : Card Interrupt Signal Enable
bits : 8 - 7 (0 bit)
access : read-write

INT_AG : INT_A Signal Enable
bits : 9 - 8 (0 bit)
access : read-write

INT_BG : INT_B Signal Enable
bits : 10 - 9 (0 bit)
access : read-write

INT_CG : INT_C Signal Enable
bits : 11 - 10 (0 bit)
access : read-write

RETUNEEVTG : Re-Tuning Event Signal Enable
bits : 12 - 11 (0 bit)
access : read-write


SEINTSGE

Error Interrupt Signal Enable Register [BHW]
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEINTSGE SEINTSGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDTOERRG CMDCRCERRG CMDEBERRG CMDIDXERRG DTTOERRG DTCRCERRG DTEBERRG CRTLMTERRG ACMD12ERRG ADMAERRG TUNINGERRG BTACKERRG ACMD19ERRG AHBMSTERRG

CMDTOERRG : Command Timeout Error Signal Enable
bits : 0 - -1 (0 bit)
access : read-write

CMDCRCERRG : Command CRC Error Signal Enable
bits : 1 - 0 (0 bit)
access : read-write

CMDEBERRG : Command End Bit Error Signal Enable
bits : 2 - 1 (0 bit)
access : read-write

CMDIDXERRG : Command Index Error Signal Enable
bits : 3 - 2 (0 bit)
access : read-write

DTTOERRG : Data Timeout Error Signal Enable
bits : 4 - 3 (0 bit)
access : read-write

DTCRCERRG : Data CRC Error Signal Enable
bits : 5 - 4 (0 bit)
access : read-write

DTEBERRG : Data End Bit Error Signal Enable
bits : 6 - 5 (0 bit)
access : read-write

CRTLMTERRG : Current limit Error Signal Enable
bits : 7 - 6 (0 bit)
access : read-write

ACMD12ERRG : Auto CMD Error Signal Enable
bits : 8 - 7 (0 bit)
access : read-write

ADMAERRG : ADMA Error Signal Enable
bits : 9 - 8 (0 bit)
access : read-write

TUNINGERRG : Tuning Error Signal Enable
bits : 10 - 9 (0 bit)
access : read-write

BTACKERRG : Boot Acknowledge Error Signal Enable
bits : 12 - 11 (0 bit)
access : read-write

ACMD19ERRG : Auto CMD19 Error Signal Enable
bits : 13 - 12 (0 bit)
access : read-write

AHBMSTERRG : AHB Master Error Signal Enable
bits : 14 - 13 (0 bit)
access : read-write


SACMDEST

Auto CMD Error Status Register [BHW]
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SACMDEST SACMDEST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACMD12NOEX ACMDTOERR ACMDCRCERR ACMDEBERR ACMDIDXERR CMDND12ERR

ACMD12NOEX : Auto CMD12 not executed
bits : 0 - -1 (0 bit)
access : read-only

ACMDTOERR : Auto CMD Timeout Error
bits : 1 - 0 (0 bit)
access : read-only

ACMDCRCERR : Auto CMD CRC Error
bits : 2 - 1 (0 bit)
access : read-only

ACMDEBERR : Auto CMD End Bit Error
bits : 3 - 2 (0 bit)
access : read-only

ACMDIDXERR : Auto CMD Index Error
bits : 4 - 3 (0 bit)
access : read-only

CMDND12ERR : Command Not Issued by Auto CMD12 Error
bits : 7 - 6 (0 bit)
access : read-only


SHCTL2

Host Control 2 Register [BHW]
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHCTL2 SHCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UHSMDSEL V18SGNEN DRVSEL DOTUING SMPCLKSEL ASYINTEN PREVALEN

UHSMDSEL : UHS Mode Select
bits : 0 - 1 (2 bit)
access : read-write

V18SGNEN : 1.8V Signaling Enable
bits : 3 - 2 (0 bit)
access : read-write

DRVSEL : Driver Strength Select
bits : 4 - 4 (1 bit)
access : read-write

DOTUING : Execute Tuning
bits : 6 - 5 (0 bit)
access : read-write

SMPCLKSEL : Sampling Clock Select
bits : 7 - 6 (0 bit)
access : read-write

ASYINTEN : Asynchronous Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write

PREVALEN : Preset Value Enable
bits : 15 - 14 (0 bit)
access : read-write


SBSIZE

Block Size Register [BHW]
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SBSIZE SBSIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRSFBLCKSZ HSDMABUFBD

TRSFBLCKSZ : Transfer Block Size
bits : 0 - 10 (11 bit)
access : read-write

HSDMABUFBD : Host SDMA Buffer Boundary
bits : 12 - 13 (2 bit)
access : read-write


CAPBLTY0

Capabilities Register 0 [BHW]
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPBLTY0 CAPBLTY0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOCLKFREQ TOCLKUNIT SDBASECLK

TOCLKFREQ : Timeout Clock Frequency
bits : 0 - 4 (5 bit)
access : read-only

TOCLKUNIT : Timeout Clock Unit
bits : 7 - 6 (0 bit)
access : read-only

SDBASECLK : Base Clock Frequency For SD Clock
bits : 8 - 14 (7 bit)
access : read-only


CAPBLTY1

Capabilities Register 1 [BHW]
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPBLTY1 CAPBLTY1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXBLCKLEN EMBD8BIT ADMA2SPT HGHSPDSPT SDMASPT LWPWRSPT V33SPT V30SPT V18SPT BUS64SPT ASYINTSPT STOPTYPE

MAXBLCKLEN : Max Block Length
bits : 0 - 0 (1 bit)
access : read-only

EMBD8BIT : 8-bit Support for Embedded Device
bits : 2 - 1 (0 bit)
access : read-only

ADMA2SPT : ADMA2 Support
bits : 3 - 2 (0 bit)
access : read-only

HGHSPDSPT : High Speed Support
bits : 5 - 4 (0 bit)
access : read-only

SDMASPT : SDMA Support
bits : 6 - 5 (0 bit)
access : read-only

LWPWRSPT : Suspend/Resume Suppoort
bits : 7 - 6 (0 bit)
access : read-only

V33SPT : Voltage Support 3.3V
bits : 8 - 7 (0 bit)
access : read-only

V30SPT : Voltage Support 3.0V
bits : 9 - 8 (0 bit)
access : read-only

V18SPT : Voltage Support 1.8V
bits : 10 - 9 (0 bit)
access : read-only

BUS64SPT : 64-bit System Bus Support
bits : 12 - 11 (0 bit)
access : read-only

ASYINTSPT : Asynchronous Interrupt Support
bits : 13 - 12 (0 bit)
access : read-only

STOPTYPE : Slot Type
bits : 14 - 14 (1 bit)
access : read-only


CAPBLTY2

Capabilities Register 2 [BHW]
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPBLTY2 CAPBLTY2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDR50SPT SDR104SPT DDR50SPT DRVTPASPT DRVTPCSPT DRVTPDSPT TMCNTRETN USETNSDR50 RETNMODE

SDR50SPT : SDR50 Support
bits : 0 - -1 (0 bit)
access : read-only

SDR104SPT : SDR104 Support
bits : 1 - 0 (0 bit)
access : read-only

DDR50SPT : DDR50 Support
bits : 2 - 1 (0 bit)
access : read-only

DRVTPASPT : Driver Type A Support
bits : 4 - 3 (0 bit)
access : read-only

DRVTPCSPT : Driver Type C Support
bits : 5 - 4 (0 bit)
access : read-only

DRVTPDSPT : Driver Type D Support
bits : 6 - 5 (0 bit)
access : read-only

TMCNTRETN : Timer Count for Re-Tuning
bits : 8 - 10 (3 bit)
access : read-only

USETNSDR50 : Use Tuning for SDR50
bits : 13 - 12 (0 bit)
access : read-only

RETNMODE : Re-Tuning Modes
bits : 14 - 14 (1 bit)
access : read-only


CAPBLTY3

Capabilities Register 3 [BHW]
address_offset : 0x46 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPBLTY3 CAPBLTY3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKMULTPL

CLKMULTPL : Clock Multiplier
bits : 0 - 6 (7 bit)
access : read-only


MXCCAPY0

Maximum Current Capabilities Register 0 [BHW]
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MXCCAPY0 MXCCAPY0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V33MAXCUR V30MAXCUR

V33MAXCUR : Maximum Current for 3.3V
bits : 0 - 6 (7 bit)
access : read-only

V30MAXCUR : Maximum Current for 3.0V
bits : 8 - 14 (7 bit)
access : read-only


MXCCAPY1

Maximum Current Capabilities Register 1 [BHW]
address_offset : 0x4A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MXCCAPY1 MXCCAPY1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V18MAXCUR

V18MAXCUR : Maximum Current for 1.8V
bits : 0 - 6 (7 bit)
access : read-only


MXCCAPY2

Maximum Current Capabilities Register 2 [BHW]
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MXCCAPY2 MXCCAPY2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MXCCAPY3

Maximum Current Capabilities Register 3 [BHW]
address_offset : 0x4E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MXCCAPY3 MXCCAPY3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FEACEST

Force Event Register for Auto CMD Error Status [BHW]
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FEACEST FEACEST write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEVNT12ND FEVNTTO FEVNTCRC FEVNTEB FEVNTIDX FEVNTCMD12

FEVNT12ND : Force Event for Auto CMD12 not executed
bits : 0 - -1 (0 bit)
access : write-only

FEVNTTO : Force Event for Auto CMD Timeout Error
bits : 1 - 0 (0 bit)
access : write-only

FEVNTCRC : Force Event for Auto CMD CRC Error
bits : 2 - 1 (0 bit)
access : write-only

FEVNTEB : Force Event for Auto CMD End Bit Error
bits : 3 - 2 (0 bit)
access : write-only

FEVNTIDX : Force Event for Auto CMD Index Error
bits : 4 - 3 (0 bit)
access : write-only

FEVNTCMD12 : Force Event for Command Not Issued by Auto CMD12 Error
bits : 7 - 6 (0 bit)
access : write-only


SFEEIST

Force Event Register for Error Interrupt Status [BHW]
address_offset : 0x52 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SFEEIST SFEEIST write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FETOERR FECRCERR FEEBERR FEIDXERR FEDTOTERR FEDTCRCERR FEDTEBERR FECRLTERR FEA12ERR FEADMAERR FETUNEERR FEACKERR FEA19ERR FEAHBMSERR

FETOERR : Force Event for Command Timeout Error
bits : 0 - -1 (0 bit)
access : write-only

FECRCERR : Force Event for Command CRC Error
bits : 1 - 0 (0 bit)
access : write-only

FEEBERR : Force Event for Command End Bit Error
bits : 2 - 1 (0 bit)
access : write-only

FEIDXERR : Force Event for Command Index Error
bits : 3 - 2 (0 bit)
access : write-only

FEDTOTERR : Force Event for Data Timeout Error
bits : 4 - 3 (0 bit)
access : write-only

FEDTCRCERR : Force Event for Data CRC Error
bits : 5 - 4 (0 bit)
access : write-only

FEDTEBERR : Force Event for Data End Bit Error
bits : 6 - 5 (0 bit)
access : write-only

FECRLTERR : Force Event for Current limit Error
bits : 7 - 6 (0 bit)
access : write-only

FEA12ERR : Force Event for Auto CMD12 Error
bits : 8 - 7 (0 bit)
access : write-only

FEADMAERR : Force Event for ADMA Error
bits : 9 - 8 (0 bit)
access : write-only

FETUNEERR : Force Event for Tuning Error
bits : 10 - 9 (0 bit)
access : write-only

FEACKERR : Force Event for Boot Acknowledge Error
bits : 12 - 11 (0 bit)
access : write-only

FEA19ERR : Force Event for Auto CMD19 Error
bits : 13 - 12 (0 bit)
access : write-only

FEAHBMSERR : Force Event for AHB Master Error
bits : 14 - 13 (0 bit)
access : write-only


ADMAEST

ADMA Error Status Register [BHW]
address_offset : 0x54 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADMAEST ADMAEST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ADMAERRS ADMALENME

ADMAERRS : ADMA Error Status
bits : 0 - 0 (1 bit)
access : read-write

ADMALENME : ADMA Length Mismatch Error
bits : 2 - 1 (0 bit)
access : read-write


SADSA0

ADMA System Address Register 0 [BHW]
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADSA0 SADSA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR1500

ADR1500 : AdMA System Address [15:0]
bits : 0 - 14 (15 bit)
access : read-write


SADSA1

ADMA System Address Register 1 [BHW]
address_offset : 0x5A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADSA1 SADSA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR3116

ADR3116 : AdMA System Address [31:16]
bits : 0 - 14 (15 bit)
access : read-write


SADSA2

ADMA System Address Register 2 [BHW]
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADSA2 SADSA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR4732

ADR4732 : AdMA System Address [47:32]
bits : 0 - 14 (15 bit)
access : read-write


SADSA3

ADMA System Address Register 3 [BHW]
address_offset : 0x5E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADSA3 SADSA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR6348

ADR6348 : AdMA System Address [63:48]
bits : 0 - 14 (15 bit)
access : read-write


SBLCNT

Block Count Register [BHW]
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SBLCNT SBLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPRVAL0

Preset Value Register for Initialization [BHW]
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPRVAL0 SPRVAL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCFSELVAL CGSELVAL DSSELVAL

SCFSELVAL : SDCLK Frequency Select Value
bits : 0 - 8 (9 bit)
access : read-write

CGSELVAL : Clock Generator Select Value
bits : 10 - 9 (0 bit)
access : read-write

DSSELVAL : Driver Strength Select Value
bits : 14 - 14 (1 bit)
access : read-write


SPRVAL1

Preset Value Register for Default Speed [BHW]
address_offset : 0x62 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPRVAL1 SPRVAL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCFSELVAL CGSELVAL DSSELVAL

SCFSELVAL : SDCLK Frequency Select Value
bits : 0 - 8 (9 bit)
access : read-write

CGSELVAL : Clock Generator Select Value
bits : 10 - 9 (0 bit)
access : read-write

DSSELVAL : Driver Strength Select Value
bits : 14 - 14 (1 bit)
access : read-write


SPRVAL2

Preset Value Register for High Speed [BHW]
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPRVAL2 SPRVAL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCFSELVAL CGSELVAL DSSELVAL

SCFSELVAL : SDCLK Frequency Select Value
bits : 0 - 8 (9 bit)
access : read-write

CGSELVAL : Clock Generator Select Value
bits : 10 - 9 (0 bit)
access : read-write

DSSELVAL : Driver Strength Select Value
bits : 14 - 14 (1 bit)
access : read-write


SPRVAL3

Preset Value Register for SDR12 [BHW]
address_offset : 0x66 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPRVAL3 SPRVAL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCFSELVAL CGSELVAL DSSELVAL

SCFSELVAL : SDCLK Frequency Select Value
bits : 0 - 8 (9 bit)
access : read-write

CGSELVAL : Clock Generator Select Value
bits : 10 - 9 (0 bit)
access : read-write

DSSELVAL : Driver Strength Select Value
bits : 14 - 14 (1 bit)
access : read-write


SPRVAL4

Preset Value Register for SDR25 [BHW]
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPRVAL4 SPRVAL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCFSELVAL CGSELVAL DSSELVAL

SCFSELVAL : SDCLK Frequency Select Value
bits : 0 - 8 (9 bit)
access : read-write

CGSELVAL : Clock Generator Select Value
bits : 10 - 9 (0 bit)
access : read-write

DSSELVAL : Driver Strength Select Value
bits : 14 - 14 (1 bit)
access : read-write


SPRVAL5

Preset Value Register for SDR50 [BHW]
address_offset : 0x6A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPRVAL5 SPRVAL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCFSELVAL CGSELVAL DSSELVAL

SCFSELVAL : SDCLK Frequency Select Value
bits : 0 - 8 (9 bit)
access : read-write

CGSELVAL : Clock Generator Select Value
bits : 10 - 9 (0 bit)
access : read-write

DSSELVAL : Driver Strength Select Value
bits : 14 - 14 (1 bit)
access : read-write


SPRVAL6

Preset Value Register for SDR104 [BHW]
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPRVAL6 SPRVAL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCFSELVAL CGSELVAL DSSELVAL

SCFSELVAL : SDCLK Frequency Select Value
bits : 0 - 8 (9 bit)
access : read-write

CGSELVAL : Clock Generator Select Value
bits : 10 - 9 (0 bit)
access : read-write

DSSELVAL : Driver Strength Select Value
bits : 14 - 14 (1 bit)
access : read-write


SPRVAL7

Preset Value Register for DDR50 [BHW]
address_offset : 0x6E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPRVAL7 SPRVAL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCFSELVAL CGSELVAL DSSELVAL

SCFSELVAL : SDCLK Frequency Select Value
bits : 0 - 8 (9 bit)
access : read-write

CGSELVAL : Clock Generator Select Value
bits : 10 - 9 (0 bit)
access : read-write

DSSELVAL : Driver Strength Select Value
bits : 14 - 14 (1 bit)
access : read-write


SSA1

Argument 1 Register [BHW]
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSA1 SSA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

STRSFMD

Transfer Mode Register [BHW]
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STRSFMD STRSFMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN BLCKCNTEN AUTOCMDEN DTTRSFDIR BLCKCNTSEL

DMAEN : DMA Enable
bits : 0 - -1 (0 bit)
access : read-write

BLCKCNTEN : Block Count Enable
bits : 1 - 0 (0 bit)
access : read-write

AUTOCMDEN : Auto Command Enable
bits : 2 - 2 (1 bit)
access : read-write

DTTRSFDIR : Data Transfer Direction Select
bits : 4 - 3 (0 bit)
access : read-write

BLCKCNTSEL : Multi / Single Block select
bits : 5 - 4 (0 bit)
access : read-write


SCMMD

Command Register [BHW]
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMMD SCMMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESPTYPE CMDCRCCHKE CMDIDXCHKE DATPRESSEL CMDTYPE CMDINDEX

RESPTYPE : Response Type Select
bits : 0 - 0 (1 bit)
access : read-write

CMDCRCCHKE : Command CRC Check Enable
bits : 3 - 2 (0 bit)
access : read-write

CMDIDXCHKE : Command Index Check Enable
bits : 4 - 3 (0 bit)
access : read-write

DATPRESSEL : Data Present Select
bits : 5 - 4 (0 bit)
access : read-write

CMDTYPE : Command Type
bits : 6 - 6 (1 bit)
access : read-write

CMDINDEX : Command Index
bits : 8 - 12 (5 bit)
access : read-write


SSHBCTLL

Shared Bus Control Register L [BHW]
address_offset : 0xE0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSHBCTLL SSHBCTLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLCKPIN INTINPIN BUSWDPRST

CLCKPIN : Number of Clock Pins
bits : 0 - 1 (2 bit)
access : read-write

INTINPIN : Number of Interrupt Input Pins
bits : 4 - 4 (1 bit)
access : read-write

BUSWDPRST : Bus Width Preset
bits : 8 - 13 (6 bit)
access : read-write


SSHBCTLH

Shared Bus Control Register H [BHW]
address_offset : 0xE2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSHBCTLH SSHBCTLH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLCKPINSEL INTPINSEL BEPWRCTL

CLCKPINSEL : Clock Pin Select
bits : 0 - 1 (2 bit)
access : read-write

INTPINSEL : Interrupt Pin Select
bits : 4 - 5 (2 bit)
access : read-write

BEPWRCTL : Back-End Power Control
bits : 8 - 13 (6 bit)
access : read-write


SSLIST

Slot Interrupt Status Register [BHW]
address_offset : 0xFC Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSLIST SSLIST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOTINTSGN

SLOTINTSGN : Interrupt Signal For Each Slot
bits : 0 - 6 (7 bit)
access : read-only


SHCTLV

Host Controller Version Register [BHW]
address_offset : 0xFE Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SHCTLV SHCTLV read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPECVERNUM VNDVERNUM

SPECVERNUM : Specification Version Number
bits : 0 - 6 (7 bit)
access : read-only

VNDVERNUM : Vendor Version Number
bits : 8 - 14 (7 bit)
access : read-only



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