\n
address_offset : 0xFC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
Software-based Simultaneous Startup Register [BHW]
address_offset : 0xFC Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SSSR0 : Software-based simultaneous startup bit of Ch.0
bits : 0 - -1 (0 bit)
access : write-only
SSSR1 : Software-based simultaneous startup bit of Ch.1
bits : 1 - 0 (0 bit)
access : write-only
SSSR2 : Software-based simultaneous startup bit of Ch.2
bits : 2 - 1 (0 bit)
access : write-only
SSSR3 : Software-based simultaneous startup bit of Ch.3
bits : 3 - 2 (0 bit)
access : write-only
SSSR4 : Software-based simultaneous startup bit of Ch.4
bits : 4 - 3 (0 bit)
access : write-only
SSSR5 : Software-based simultaneous startup bit of Ch.5
bits : 5 - 4 (0 bit)
access : write-only
SSSR6 : Software-based simultaneous startup bit of Ch.6
bits : 6 - 5 (0 bit)
access : write-only
SSSR7 : Software-based simultaneous startup bit of Ch.7
bits : 7 - 6 (0 bit)
access : write-only
SSSR8 : Software-based simultaneous startup bit of Ch.8
bits : 8 - 7 (0 bit)
access : write-only
SSSR9 : Software-based simultaneous startup bit of Ch.9
bits : 9 - 8 (0 bit)
access : write-only
SSSR10 : Software-based simultaneous startup bit of Ch.10
bits : 10 - 9 (0 bit)
access : write-only
SSSR11 : Software-based simultaneous startup bit of Ch.11
bits : 11 - 10 (0 bit)
access : write-only
SSSR12 : Software-based simultaneous startup bit of Ch.12
bits : 12 - 11 (0 bit)
access : write-only
SSSR13 : Software-based simultaneous startup bit of Ch.13
bits : 13 - 12 (0 bit)
access : write-only
SSSR14 : Software-based simultaneous startup bit of Ch.14
bits : 14 - 13 (0 bit)
access : write-only
SSSR15 : Software-based simultaneous startup bit of Ch.15
bits : 15 - 14 (0 bit)
access : write-only
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