\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
IMR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR : Interrupt mask on line x
bits : 0 - 22 (23 bit)
SWIER
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWIER : Software interrupt on line x
bits : 0 - 22 (23 bit)
PR
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PR : Pending bit
bits : 0 - 22 (23 bit)
EMR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR : Event mask on line x
bits : 0 - 22 (23 bit)
RTSR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR : Rising edge trigger event configuration bit of line x
bits : 0 - 22 (23 bit)
FTSR
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR : Falling edge trigger event configuration bit of line x
bits : 0 - 22 (23 bit)
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