\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x300 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
Mode Register 0 [W]
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTH : specify Data Width
bits : 0 - 0 (1 bit)
access : read-write
RBMON : Read Byte Mask ON
bits : 2 - 1 (0 bit)
access : read-write
WEOFF : disable the write enable signal (MWEX) operation
bits : 3 - 2 (0 bit)
access : read-write
NAND : NAND Flash memory mode
bits : 4 - 3 (0 bit)
access : read-write
PAGE : NOR Flash memory page access mode
bits : 5 - 4 (0 bit)
access : read-write
RDY : control the external RDY function
bits : 6 - 5 (0 bit)
access : read-write
SHRTDOUT : select to which idle cycle the write data output is extended
bits : 7 - 6 (0 bit)
access : read-write
MPXMODE : select operation bus mode
bits : 8 - 7 (0 bit)
access : read-write
ALEINV : set up the polarity of the ALE signal
bits : 9 - 8 (0 bit)
access : read-write
MPXDOFF : select whether or not the address is output to the data lines in multiplex mode
bits : 11 - 10 (0 bit)
access : read-write
MPXCSOF : select a CS assertion from the start of accessing to the end of address output
bits : 12 - 11 (0 bit)
access : read-write
MOEXEUP : select how to set the MOEX width
bits : 13 - 12 (0 bit)
access : read-write
Mode Register 4 [W]
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDRAM Mode Register [W]
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDON : SDRAM ON
bits : 0 - -1 (0 bit)
access : read-write
PDON : Power Down ON
bits : 1 - 0 (0 bit)
access : read-write
ROFF : Refresh OFF
bits : 2 - 1 (0 bit)
access : read-write
CASEL : Column Address Select
bits : 4 - 4 (1 bit)
access : read-write
RASEL : Row Address Select
bits : 8 - 10 (3 bit)
access : read-write
BASEL : Bank Address Select
bits : 12 - 14 (3 bit)
access : read-write
MSDCLKOFF : MSDCLK OFF
bits : 16 - 15 (0 bit)
access : read-write
Refresh Timer Register [W]
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFC : Refresh Count
bits : 0 - 14 (15 bit)
access : read-write
NREF : Number of Refresh
bits : 16 - 22 (7 bit)
access : read-write
PREF : Pre-Refresh
bits : 24 - 23 (0 bit)
access : read-write
Power Down Count Register [W]
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDC : Power Down Count
bits : 0 - 14 (15 bit)
access : read-write
SDRAM Timing Register [W]
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CL : CAS Latency
bits : 0 - 0 (1 bit)
access : read-write
TRC : RAS Cycle time
bits : 4 - 6 (3 bit)
access : read-write
TRP : RAS Precharge time
bits : 8 - 10 (3 bit)
access : read-write
TRCD : RAS-CAS Delay
bits : 12 - 14 (3 bit)
access : read-write
TRAS : RAS active time
bits : 16 - 18 (3 bit)
access : read-write
TREFC : Refresh Cycle time
bits : 20 - 22 (3 bit)
access : read-write
TDPL : Data-in to Precharge Lead Time
bits : 24 - 24 (1 bit)
access : read-write
BOFF : Buffer readout bit
bits : 31 - 30 (0 bit)
access : read-write
SDRAM Command Register [W]
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDAD : SDRAM ADress
bits : 0 - 14 (15 bit)
access : read-write
SDWE : SDRAM Write Enable
bits : 16 - 15 (0 bit)
access : read-write
SDCAS : SDRAM CAS
bits : 17 - 16 (0 bit)
access : read-write
SDRAS : SDRAM RAS
bits : 18 - 17 (0 bit)
access : read-write
SDCS : SDRAM Chip Select
bits : 19 - 18 (0 bit)
access : read-write
SDCKE : SDRAM CKE
bits : 20 - 19 (0 bit)
access : read-write
PEND : Pend
bits : 31 - 30 (0 bit)
access : read-only
Mode Register 5 [W]
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mode Register 6 [W]
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mode Register 7 [W]
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timing Register 0 [W]
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RACC : Read Access Cycle
bits : 0 - 2 (3 bit)
access : read-write
RADC : Read Address Setup cycle
bits : 4 - 6 (3 bit)
access : read-write
FRADC : First Read Address Cycle
bits : 8 - 10 (3 bit)
access : read-write
RIDLC : Read Idle Cycle
bits : 12 - 14 (3 bit)
access : read-write
WACC : Write Access Cycle
bits : 16 - 18 (3 bit)
access : read-write
WADC : Write Address Setup cycle
bits : 20 - 22 (3 bit)
access : read-write
WWEC : Write Enable Cycle
bits : 24 - 26 (3 bit)
access : read-write
WIDLC : Write Idle Cycle
bits : 28 - 30 (3 bit)
access : read-write
Memory Controller Register [W]
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFER : SRAM/Flash Error
bits : 0 - -1 (0 bit)
access : read-write
SDER : SDRAM Error
bits : 1 - 0 (0 bit)
access : read-write
SFION : SRAM/Flash error Interrupt ON
bits : 2 - 1 (0 bit)
access : read-write
SDION : SDRAM error Interrupt ON
bits : 3 - 2 (0 bit)
access : read-write
Timing Register 1 [W]
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timing Register 2 [W]
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timing Register 3 [W]
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timing Register 4 [W]
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Division Clock Register [W]
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDIV : MCLK Division Ratio Setup
bits : 0 - 2 (3 bit)
access : read-write
MCLKON : MCLK ON
bits : 4 - 3 (0 bit)
access : read-write
Error Status Register [W]
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WERR : WERR
bits : 0 - -1 (0 bit)
access : read-only
Write Error Address Register [W]
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : ADDR
bits : 0 - 30 (31 bit)
access : read-only
Error Status Clear Register [W]
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WERRCLR : Write Error Clear
bits : 0 - -1 (0 bit)
access : write-only
Access Mode Register [W]
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAEN : WAEN
bits : 0 - -1 (0 bit)
access : read-write
Timing Register 5 [W]
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timing Register 6 [W]
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timing Register 7 [W]
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mode Register 1 [W]
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Area Register 0 [W]
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write
MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write
Area Register 1 [W]
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write
MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write
Area Register 2 [W]
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write
MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write
Area Register 3 [W]
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write
MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write
Area Register 4 [W]
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write
MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write
Area Register 5 [W]
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write
MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write
Area Register 6 [W]
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write
MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write
Area Register 7 [W]
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write
MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write
ALE Timing Register 0 [W]
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALC : Address Latch Cycle
bits : 0 - 2 (3 bit)
access : read-write
ALES : Address Latch Enable Setup cycle
bits : 4 - 6 (3 bit)
access : read-write
ALEW : Address Latch Enable Width
bits : 8 - 10 (3 bit)
access : read-write
ALE Timing Register 1 [W]
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALE Timing Register 2 [W]
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALE Timing Register 3 [W]
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALE Timing Register 4 [W]
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALE Timing Register 5 [W]
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALE Timing Register 6 [W]
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALE Timing Register 7 [W]
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mode Register 2 [W]
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mode Register 3 [W]
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.