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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x34 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x44 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x54 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x60 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x64 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x68 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x5C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x48 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x58 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x6C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x70 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x74 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x78 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x7C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x88 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x90 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x98 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x9C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xAC Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xB0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WTCR10

WTCR20

BREG00

BREG01

BREG02

BREG03

BREG04

BREG05

BREG06

BREG07

BREG08

BREG09

BREG0A

BREG0B

BREG0C

BREG0D

BREG0E

BREG0F

BREG10

BREG11

BREG12

BREG13

BREG14

BREG15

BREG16

BREG17

BREG18

BREG19

BREG1A

BREG1B

BREG1C

BREG1D

BREG1E

BREG1F

BREG20

BREG21

BREG22

BREG23

BREG24

BREG25

BREG26

BREG27

BREG28

BREG29

BREG2A

BREG2B

BREG2C

BREG2D

BREG2E

BREG2F

BREG30

BREG31

BREG32

BREG33

BREG34

BREG35

BREG36

BREG37

BREG38

BREG39

BREG3A

BREG3B

BREG3C

BREG3D

BREG3E

BREG3F

WTCR21

BREG40

BREG41

BREG42

BREG43

BREG44

BREG45

BREG46

BREG47

BREG48

BREG49

BREG4A

BREG4B

BREG4C

BREG4D

BREG4E

BREG4F

BREG50

BREG51

BREG52

BREG53

BREG54

BREG55

BREG56

BREG57

BREG58

BREG59

BREG5A

BREG5B

BREG5C

BREG5D

BREG5E

BREG5F

BREG60

BREG61

BREG62

BREG63

BREG64

BREG65

BREG66

BREG67

BREG68

BREG69

BREG6A

BREG6B

BREG6C

BREG6D

BREG6E

BREG6F

BREG70

BREG71

BREG72

BREG73

BREG74

BREG75

BREG76

BREG77

BREG78

BREG79

BREG7A

BREG7B

BREG7C

BREG7D

BREG7E

BREG7F

WTSR

WTMIR

WTHR

WTDR

WTDW

WTMOR

WTYR

ALMIR

ALHR

WTCR11

ALDR

ALMOR

ALYR

WTTR0

WTTR1

WTTR2

WTCAL0

WTCAL1

WTCALEN

WTDIV

WTDIVEN

WTCALPRD

WTCOSEL

VB_CLKDIV

WTOSCCNT

CCS

WTCR12

CCB

BOOST

EWKUP

VDET

HIBRST

VBPFR

VBPCR

VBDDR

VBDIR

VBDOR

VBPZR

WTCR13


WTCR10

Control Register 10 [BHW]
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR10 WTCR10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ST RUN SRST SCST SCRST BUSY TRANS

ST : Start bit
bits : 0 - -1 (0 bit)
access : read-write

RUN : RTC count block operation bit
bits : 2 - 1 (0 bit)
access : read-only

SRST : RTC reset bit
bits : 3 - 2 (0 bit)
access : write-only

SCST : 1-second clock output stop bit
bits : 4 - 3 (0 bit)
access : read-write

SCRST : Sub second generation/1-second generation counter reset bit
bits : 5 - 4 (0 bit)
access : read-write

BUSY : Busy bit
bits : 6 - 5 (0 bit)
access : read-only

TRANS : Transfer flag bit
bits : 7 - 6 (0 bit)
access : read-only


WTCR20

Control Register 20 [BHW]
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR20 WTCR20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CREAD CWRITE BREAD BWRITE PREAD PWRITE

CREAD : RTC setting recall control bit
bits : 0 - -1 (0 bit)
access : read-write

CWRITE : RTC setting save control bit
bits : 1 - 0 (0 bit)
access : read-write

BREAD : Back up register recall control bit
bits : 2 - 1 (0 bit)
access : read-write

BWRITE : Back up register save control bit
bits : 3 - 2 (0 bit)
access : read-write

PREAD : VBAT PORT recall control bit
bits : 4 - 3 (0 bit)
access : read-write

PWRITE : VBAT PORT save control bit
bits : 5 - 4 (0 bit)
access : read-write


BREG00

Backup Register [BHW]
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG00 BREG00 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG01

Backup Register [BHW]
address_offset : 0x101 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG01 BREG01 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG02

Backup Register [BHW]
address_offset : 0x102 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG02 BREG02 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG03

Backup Register [BHW]
address_offset : 0x103 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG03 BREG03 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG04

Backup Register [BHW]
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG04 BREG04 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG05

Backup Register [BHW]
address_offset : 0x105 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG05 BREG05 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG06

Backup Register [BHW]
address_offset : 0x106 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG06 BREG06 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG07

Backup Register [BHW]
address_offset : 0x107 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG07 BREG07 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG08

Backup Register [BHW]
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG08 BREG08 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG09

Backup Register [BHW]
address_offset : 0x109 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG09 BREG09 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG0A

Backup Register [BHW]
address_offset : 0x10A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG0A BREG0A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG0B

Backup Register [BHW]
address_offset : 0x10B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG0B BREG0B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG0C

Backup Register [BHW]
address_offset : 0x10C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG0C BREG0C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG0D

Backup Register [BHW]
address_offset : 0x10D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG0D BREG0D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG0E

Backup Register [BHW]
address_offset : 0x10E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG0E BREG0E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG0F

Backup Register [BHW]
address_offset : 0x10F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG0F BREG0F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG10

Backup Register [BHW]
address_offset : 0x110 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG10 BREG10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG11

Backup Register [BHW]
address_offset : 0x111 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG11 BREG11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG12

Backup Register [BHW]
address_offset : 0x112 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG12 BREG12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG13

Backup Register [BHW]
address_offset : 0x113 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG13 BREG13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG14

Backup Register [BHW]
address_offset : 0x114 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG14 BREG14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG15

Backup Register [BHW]
address_offset : 0x115 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG15 BREG15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG16

Backup Register [BHW]
address_offset : 0x116 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG16 BREG16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG17

Backup Register [BHW]
address_offset : 0x117 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG17 BREG17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG18

Backup Register [BHW]
address_offset : 0x118 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG18 BREG18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG19

Backup Register [BHW]
address_offset : 0x119 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG19 BREG19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG1A

Backup Register [BHW]
address_offset : 0x11A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG1A BREG1A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG1B

Backup Register [BHW]
address_offset : 0x11B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG1B BREG1B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG1C

Backup Register [BHW]
address_offset : 0x11C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG1C BREG1C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG1D

Backup Register [BHW]
address_offset : 0x11D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG1D BREG1D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG1E

Backup Register [BHW]
address_offset : 0x11E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG1E BREG1E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG1F

Backup Register [BHW]
address_offset : 0x11F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG1F BREG1F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG20

Backup Register [BHW]
address_offset : 0x120 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG20 BREG20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG21

Backup Register [BHW]
address_offset : 0x121 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG21 BREG21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG22

Backup Register [BHW]
address_offset : 0x122 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG22 BREG22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG23

Backup Register [BHW]
address_offset : 0x123 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG23 BREG23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG24

Backup Register [BHW]
address_offset : 0x124 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG24 BREG24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG25

Backup Register [BHW]
address_offset : 0x125 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG25 BREG25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG26

Backup Register [BHW]
address_offset : 0x126 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG26 BREG26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG27

Backup Register [BHW]
address_offset : 0x127 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG27 BREG27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG28

Backup Register [BHW]
address_offset : 0x128 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG28 BREG28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG29

Backup Register [BHW]
address_offset : 0x129 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG29 BREG29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG2A

Backup Register [BHW]
address_offset : 0x12A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG2A BREG2A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG2B

Backup Register [BHW]
address_offset : 0x12B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG2B BREG2B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG2C

Backup Register [BHW]
address_offset : 0x12C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG2C BREG2C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG2D

Backup Register [BHW]
address_offset : 0x12D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG2D BREG2D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG2E

Backup Register [BHW]
address_offset : 0x12E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG2E BREG2E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG2F

Backup Register [BHW]
address_offset : 0x12F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG2F BREG2F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG30

Backup Register [BHW]
address_offset : 0x130 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG30 BREG30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG31

Backup Register [BHW]
address_offset : 0x131 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG31 BREG31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG32

Backup Register [BHW]
address_offset : 0x132 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG32 BREG32 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG33

Backup Register [BHW]
address_offset : 0x133 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG33 BREG33 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG34

Backup Register [BHW]
address_offset : 0x134 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG34 BREG34 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG35

Backup Register [BHW]
address_offset : 0x135 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG35 BREG35 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG36

Backup Register [BHW]
address_offset : 0x136 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG36 BREG36 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG37

Backup Register [BHW]
address_offset : 0x137 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG37 BREG37 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG38

Backup Register [BHW]
address_offset : 0x138 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG38 BREG38 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG39

Backup Register [BHW]
address_offset : 0x139 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG39 BREG39 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG3A

Backup Register [BHW]
address_offset : 0x13A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG3A BREG3A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG3B

Backup Register [BHW]
address_offset : 0x13B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG3B BREG3B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG3C

Backup Register [BHW]
address_offset : 0x13C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG3C BREG3C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG3D

Backup Register [BHW]
address_offset : 0x13D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG3D BREG3D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG3E

Backup Register [BHW]
address_offset : 0x13E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG3E BREG3E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG3F

Backup Register [BHW]
address_offset : 0x13F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG3F BREG3F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

WTCR21

Control Register 21 [BHW]
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR21 WTCR21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TMST TMEN TMRUN

TMST : Timer counter start bit
bits : 0 - -1 (0 bit)
access : read-write

TMEN : Timer counter control bit
bits : 1 - 0 (0 bit)
access : read-write

TMRUN : Timer counter operation bit
bits : 2 - 1 (0 bit)
access : read-only


BREG40

Backup Register [BHW]
address_offset : 0x140 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG40 BREG40 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG41

Backup Register [BHW]
address_offset : 0x141 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG41 BREG41 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG42

Backup Register [BHW]
address_offset : 0x142 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG42 BREG42 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG43

Backup Register [BHW]
address_offset : 0x143 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG43 BREG43 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG44

Backup Register [BHW]
address_offset : 0x144 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG44 BREG44 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG45

Backup Register [BHW]
address_offset : 0x145 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG45 BREG45 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG46

Backup Register [BHW]
address_offset : 0x146 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG46 BREG46 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG47

Backup Register [BHW]
address_offset : 0x147 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG47 BREG47 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG48

Backup Register [BHW]
address_offset : 0x148 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG48 BREG48 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG49

Backup Register [BHW]
address_offset : 0x149 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG49 BREG49 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG4A

Backup Register [BHW]
address_offset : 0x14A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG4A BREG4A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG4B

Backup Register [BHW]
address_offset : 0x14B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG4B BREG4B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG4C

Backup Register [BHW]
address_offset : 0x14C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG4C BREG4C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG4D

Backup Register [BHW]
address_offset : 0x14D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG4D BREG4D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG4E

Backup Register [BHW]
address_offset : 0x14E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG4E BREG4E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG4F

Backup Register [BHW]
address_offset : 0x14F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG4F BREG4F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG50

Backup Register [BHW]
address_offset : 0x150 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG50 BREG50 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG51

Backup Register [BHW]
address_offset : 0x151 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG51 BREG51 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG52

Backup Register [BHW]
address_offset : 0x152 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG52 BREG52 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG53

Backup Register [BHW]
address_offset : 0x153 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG53 BREG53 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG54

Backup Register [BHW]
address_offset : 0x154 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG54 BREG54 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG55

Backup Register [BHW]
address_offset : 0x155 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG55 BREG55 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG56

Backup Register [BHW]
address_offset : 0x156 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG56 BREG56 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG57

Backup Register [BHW]
address_offset : 0x157 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG57 BREG57 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG58

Backup Register [BHW]
address_offset : 0x158 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG58 BREG58 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG59

Backup Register [BHW]
address_offset : 0x159 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG59 BREG59 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG5A

Backup Register [BHW]
address_offset : 0x15A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG5A BREG5A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG5B

Backup Register [BHW]
address_offset : 0x15B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG5B BREG5B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG5C

Backup Register [BHW]
address_offset : 0x15C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG5C BREG5C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG5D

Backup Register [BHW]
address_offset : 0x15D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG5D BREG5D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG5E

Backup Register [BHW]
address_offset : 0x15E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG5E BREG5E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG5F

Backup Register [BHW]
address_offset : 0x15F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG5F BREG5F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG60

Backup Register [BHW]
address_offset : 0x160 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG60 BREG60 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG61

Backup Register [BHW]
address_offset : 0x161 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG61 BREG61 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG62

Backup Register [BHW]
address_offset : 0x162 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG62 BREG62 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG63

Backup Register [BHW]
address_offset : 0x163 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG63 BREG63 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG64

Backup Register [BHW]
address_offset : 0x164 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG64 BREG64 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG65

Backup Register [BHW]
address_offset : 0x165 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG65 BREG65 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG66

Backup Register [BHW]
address_offset : 0x166 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG66 BREG66 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG67

Backup Register [BHW]
address_offset : 0x167 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG67 BREG67 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG68

Backup Register [BHW]
address_offset : 0x168 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG68 BREG68 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG69

Backup Register [BHW]
address_offset : 0x169 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG69 BREG69 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG6A

Backup Register [BHW]
address_offset : 0x16A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG6A BREG6A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG6B

Backup Register [BHW]
address_offset : 0x16B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG6B BREG6B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG6C

Backup Register [BHW]
address_offset : 0x16C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG6C BREG6C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG6D

Backup Register [BHW]
address_offset : 0x16D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG6D BREG6D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG6E

Backup Register [BHW]
address_offset : 0x16E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG6E BREG6E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG6F

Backup Register [BHW]
address_offset : 0x16F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG6F BREG6F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG70

Backup Register [BHW]
address_offset : 0x170 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG70 BREG70 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG71

Backup Register [BHW]
address_offset : 0x171 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG71 BREG71 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG72

Backup Register [BHW]
address_offset : 0x172 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG72 BREG72 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG73

Backup Register [BHW]
address_offset : 0x173 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG73 BREG73 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG74

Backup Register [BHW]
address_offset : 0x174 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG74 BREG74 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG75

Backup Register [BHW]
address_offset : 0x175 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG75 BREG75 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG76

Backup Register [BHW]
address_offset : 0x176 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG76 BREG76 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG77

Backup Register [BHW]
address_offset : 0x177 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG77 BREG77 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG78

Backup Register [BHW]
address_offset : 0x178 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG78 BREG78 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG79

Backup Register [BHW]
address_offset : 0x179 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG79 BREG79 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG7A

Backup Register [BHW]
address_offset : 0x17A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG7A BREG7A read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG7B

Backup Register [BHW]
address_offset : 0x17B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG7B BREG7B read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG7C

Backup Register [BHW]
address_offset : 0x17C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG7C BREG7C read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG7D

Backup Register [BHW]
address_offset : 0x17D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG7D BREG7D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG7E

Backup Register [BHW]
address_offset : 0x17E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG7E BREG7E read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BREG7F

Backup Register [BHW]
address_offset : 0x17F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREG7F BREG7F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

WTSR

Second Register [BHW]
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTSR WTSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 S TS

S : 1st digit of the second information
bits : 0 - 2 (3 bit)
access : read-write

TS : 2nd digit of the second information
bits : 4 - 5 (2 bit)
access : read-write


WTMIR

Minute Register [BHW]
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTMIR WTMIR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MI TMI

MI : 1st digit of the minute information
bits : 0 - 2 (3 bit)
access : read-write

TMI : 2nd digit of the minute information
bits : 4 - 5 (2 bit)
access : read-write


WTHR

Hour register [BHW]
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTHR WTHR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 H TH

H : 1st digit of the hour information
bits : 0 - 2 (3 bit)
access : read-write

TH : 2nd digit of the hour information
bits : 4 - 4 (1 bit)
access : read-write


WTDR

Day Register [BHW]
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTDR WTDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 D TD

D : 1st digit of the day information
bits : 0 - 2 (3 bit)
access : read-write

TD : 2nd digit of the day information
bits : 4 - 4 (1 bit)
access : read-write


WTDW

Day of the Week Register [BHW]
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTDW WTDW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DW

DW : Day of the week information
bits : 0 - 1 (2 bit)
access : read-write


WTMOR

Month Register [BHW]
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTMOR WTMOR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MO TMO

MO : 1st digit of the month information
bits : 0 - 2 (3 bit)
access : read-write

TMO : 2nd digit of the month information
bits : 4 - 3 (0 bit)
access : read-write


WTYR

Year Register [BHW]
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTYR WTYR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 Y TY

Y : 1st digit of the year information
bits : 0 - 2 (3 bit)
access : read-write

TY : 2nd digit of the year information
bits : 4 - 6 (3 bit)
access : read-write


ALMIR

Alarm Minute Register [BHW]
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALMIR ALMIR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMI TAMI

AMI : 1st digit of the alarm-set minute information
bits : 0 - 2 (3 bit)
access : read-write

TAMI : 2nd digit of the alarm-set minute information
bits : 4 - 5 (2 bit)
access : read-write


ALHR

Alarm Hour Register [BHW]
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALHR ALHR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AH TAH

AH : 1st digit of the alarm-set hour information
bits : 0 - 2 (3 bit)
access : read-write

TAH : 2nd digit of the alarm-set hour information
bits : 4 - 4 (1 bit)
access : read-write


WTCR11

Control Register 11 [BHW]
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR11 WTCR11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MIEN HEN DEN MOEN YEN

MIEN : Alarm minute register enable bit
bits : 0 - -1 (0 bit)
access : read-write

HEN : Alarm hour register enable bit
bits : 1 - 0 (0 bit)
access : read-write

DEN : Alarm day register enable bit
bits : 2 - 1 (0 bit)
access : read-write

MOEN : Alarm month register enable bit
bits : 3 - 2 (0 bit)
access : read-write

YEN : Alarm year register enable bit
bits : 4 - 3 (0 bit)
access : read-write


ALDR

Alarm Date Register [BHW]
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALDR ALDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AD TAD

AD : 1st digit of the alarm-set date information
bits : 0 - 2 (3 bit)
access : read-write

TAD : 2nd digit of the alarm-set date information
bits : 4 - 4 (1 bit)
access : read-write


ALMOR

Alarm Month Register [BHW]
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALMOR ALMOR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMO TAMO

AMO : 1st digit of the alarm-set month information
bits : 0 - 2 (3 bit)
access : read-write

TAMO : 2nd digit of the alarm-set month information
bits : 4 - 3 (0 bit)
access : read-write


ALYR

Alarm Years Register [BHW]
address_offset : 0x48 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALYR ALYR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AY TAY

AY : 1st digit of the alarm-set year information
bits : 0 - 2 (3 bit)
access : read-write

TAY : 2nd digit of the alarm-set year information
bits : 4 - 6 (3 bit)
access : read-write


WTTR0

Timer Setting Register 0 [BHW]
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTTR0 WTTR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TM

TM : Timer Setting Register
bits : 0 - 6 (7 bit)
access : read-write


WTTR1

Timer Setting Register 1 [BHW]
address_offset : 0x50 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTTR1 WTTR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TM

TM : Timer Setting Register
bits : 0 - 6 (7 bit)
access : read-write


WTTR2

Timer Setting Register 2 [BHW]
address_offset : 0x54 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTTR2 WTTR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TM

TM : Timer Setting Register
bits : 0 - 0 (1 bit)
access : read-write


WTCAL0

Frequency Correction Value Setting Register 0 [BHW]
address_offset : 0x58 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCAL0 WTCAL0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCAL0

WTCAL0 : Frequency correction value setting bits 0
bits : 0 - 6 (7 bit)
access : read-write


WTCAL1

Frequency Correction Value Setting Register 1 [BHW]
address_offset : 0x5C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCAL1 WTCAL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCAL1

WTCAL1 : Frequency correction value setting bits 1
bits : 0 - 0 (1 bit)
access : read-write


WTCALEN

Frequency Correction Enable Register [BHW]
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCALEN WTCALEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCALEN

WTCALEN : Frequency correction enable bit
bits : 0 - -1 (0 bit)
access : read-write


WTDIV

Division Ratio Setting Register [BHW]
address_offset : 0x64 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTDIV WTDIV read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTDIV

WTDIV : Division ration setting bits
bits : 0 - 2 (3 bit)
access : read-write


WTDIVEN

Divider Output Enable Register [BHW]
address_offset : 0x68 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTDIVEN WTDIVEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTDIVEN WTDIVRDY

WTDIVEN : Divider enable bit
bits : 0 - -1 (0 bit)
access : read-write

WTDIVRDY : Divider state bit
bits : 1 - 0 (0 bit)
access : read-only


WTCALPRD

Frequency Correction Period Setting Register [BHW]
address_offset : 0x6C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCALPRD WTCALPRD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCALPRD

WTCALPRD : Frequency correction value setting bits
bits : 0 - 4 (5 bit)
access : read-write


WTCOSEL

RTCCO Output Selection Register [BHW]
address_offset : 0x70 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCOSEL WTCOSEL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCOSEL

WTCOSEL : RTCCO output selection bit
bits : 0 - -1 (0 bit)
access : read-write


VB_CLKDIV

VBAT Clock Divider Register [BHW]
address_offset : 0x74 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VB_CLKDIV VB_CLKDIV read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIV

DIV : Transfer clock set bits
bits : 0 - 6 (7 bit)
access : read-write


WTOSCCNT

WT Oscillation Circuit Control Register [BHW]
address_offset : 0x78 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTOSCCNT WTOSCCNT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOSCEX SOSCNTL

SOSCEX : Oscillation enable bit
bits : 0 - -1 (0 bit)
access : read-write

SOSCNTL : Cooperative operation control bit
bits : 1 - 0 (0 bit)
access : read-write


CCS

Oscillation Sustain Current Control Register [BHW]
address_offset : 0x7C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCS CCS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CCS

CCS : Oscillation sustain current set bits
bits : 0 - 6 (7 bit)
access : read-write


WTCR12

Control Register 12 [BHW]
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR12 WTCR12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTSSI INTSI INTMI INTHI INTTMI INTALI INTERI INTCRI

INTSSI : Every 0.5-second flag bit
bits : 0 - -1 (0 bit)
access : read-write

INTSI : Every second flag bit
bits : 1 - 0 (0 bit)
access : read-write

INTMI : Every minute flag bit
bits : 2 - 1 (0 bit)
access : read-write

INTHI : Every hour flag bit
bits : 3 - 2 (0 bit)
access : read-write

INTTMI : Timer underflow detection flag bit
bits : 4 - 3 (0 bit)
access : read-write

INTALI : Alarm coincidence flag bit
bits : 5 - 4 (0 bit)
access : read-write

INTERI : Time rewrite error interrupt flag bit
bits : 6 - 5 (0 bit)
access : read-write

INTCRI : Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag bit
bits : 7 - 6 (0 bit)
access : read-write


CCB

Oscillation Boost Current Control Register [BHW]
address_offset : 0x80 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCB CCB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CCB

CCB : Oscillation boost current set bits
bits : 0 - 6 (7 bit)
access : read-write


BOOST

Oscillation Boost Clock Setting Register [BHW]
address_offset : 0x88 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOST BOOST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BOOST

BOOST : Oscillation boost time set bits
bits : 0 - 0 (1 bit)
access : read-write


EWKUP

Wakeup Request Register [BHW]
address_offset : 0x8C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EWKUP EWKUP read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WUP0

WUP0 : Wakeup request bit
bits : 0 - -1 (0 bit)
access : read-write


VDET

Power-On Circuit State and Power-On Signal Register [BHW]
address_offset : 0x90 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDET VDET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PON

PON : Power-on bit
bits : 7 - 6 (0 bit)
access : read-write


HIBRST

Hibernation Start Register [BHW]
address_offset : 0x98 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIBRST HIBRST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HIBRST

HIBRST : Hibernation start bit
bits : 0 - -1 (0 bit)
access : read-write


VBPFR

Port Function Set Register [BHW]
address_offset : 0x9C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBPFR VBPFR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VPFR0 VPFR1 VPFR2 VPFR3 SPSR

VPFR0 : Port function of P48/VREGCTL pin set bit
bits : 0 - -1 (0 bit)
access : read-write

VPFR1 : Port function of P49/VWAKEUP pin set bit
bits : 1 - 0 (0 bit)
access : read-write

VPFR2 : Port function of P47/X1A pin set bit
bits : 2 - 1 (0 bit)
access : read-write

VPFR3 : Port function of P46/X0A pin set bit
bits : 3 - 2 (0 bit)
access : read-write

SPSR : Oscillation pin function set bits
bits : 4 - 4 (1 bit)
access : read-write


VBPCR

Pull-up Set Register [BHW]
address_offset : 0xA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBPCR VBPCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VPCR0 VPCR1 VPCR2 VPCR3

VPCR0 : P48/VREGCTL pin pull-up set bit
bits : 0 - -1 (0 bit)
access : read-write

VPCR1 : P49/VWAKEUP pin pull-up set bit
bits : 1 - 0 (0 bit)
access : read-write

VPCR2 : P47/X1A pin pull-up set bit
bits : 2 - 1 (0 bit)
access : read-write

VPCR3 : P46/X0A pin pull-up set bit
bits : 3 - 2 (0 bit)
access : read-write


VBDDR

Port I/O Direction Set Register [BHW]
address_offset : 0xA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBDDR VBDDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VDDR0 VDDR1 VDDR2 VDDR3

VDDR0 : Port direction of P48/VREGCTL pin set bit
bits : 0 - -1 (0 bit)
access : read-write

VDDR1 : Port direction of P49/VWAKEUP pin set bit
bits : 1 - 0 (0 bit)
access : read-write

VDDR2 : Port direction of P47/X1A pin set bit
bits : 2 - 1 (0 bit)
access : read-write

VDDR3 : Port direction of P46/X0A pin set bit
bits : 3 - 2 (0 bit)
access : read-write


VBDIR

Port Input Data Register [BHW]
address_offset : 0xA8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBDIR VBDIR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VDIR0 VDIR1 VDIR2 VDIR3

VDIR0 : Port input data of P48/VREGCTL pin bit
bits : 0 - -1 (0 bit)
access : read-write

VDIR1 : Port input data of P49/VWAKEUP pin bit
bits : 1 - 0 (0 bit)
access : read-write

VDIR2 : Port input data of P47/X1A pin bit
bits : 2 - 1 (0 bit)
access : read-write

VDIR3 : Port input data of P46/X0A pin bit
bits : 3 - 2 (0 bit)
access : read-write


VBDOR

Port Output Data Register [BHW]
address_offset : 0xAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBDOR VBDOR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VDOR0 VDOR1 VDOR2 VDOR3

VDOR0 : Port output data of P48/VREGCTL pin bit
bits : 0 - -1 (0 bit)
access : read-write

VDOR1 : Port output data of P49/VWAKEUP pin bit
bits : 1 - 0 (0 bit)
access : read-write

VDOR2 : Port output data of P47/X1A pin bit
bits : 2 - 1 (0 bit)
access : read-write

VDOR3 : Port output data of P46/X0A pin bit
bits : 3 - 2 (0 bit)
access : read-write


VBPZR

Port Pseudo-Open Drain Set Register [BHW]
address_offset : 0xB0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBPZR VBPZR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VPZR0 VPZR1

VPZR0 : P48/VREGCTL pin pseudo-open drain set bit
bits : 0 - -1 (0 bit)
access : read-write

VPZR1 : P49/VWAKEUP pin pseudo-open drain set bit
bits : 1 - 0 (0 bit)
access : read-write


WTCR13

Control Register 13 [BHW]
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR13 WTCR13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTSSIE INTSIE INTMIE INTHIE INTTMIE INTALIE INTERIE INTCRIE

INTSSIE : Every 0.5-second interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write

INTSIE : Every second interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write

INTMIE : Every minute interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write

INTHIE : Every hour interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write

INTTMIE : Timer underflow interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write

INTALIE : Alarm coincidence interrupt enable bit
bits : 5 - 4 (0 bit)
access : read-write

INTERIE : Time rewrite error interrupt enable bit
bits : 6 - 5 (0 bit)
access : read-write

INTCRIE : Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable bit
bits : 7 - 6 (0 bit)
access : read-write



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