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CAN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xE byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0xE byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0xE byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x60 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x90 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xB0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRLR

IF1CREQ

IF1CMSK

IF1MSK

IF1ARB

IF1MCTR

STATR

IF1DTA_L

IF1DTB_L

IF1DTA_B

IF1DTB_B

ERRCNT

IF2CREQ

IF2CMSK

IF2MSK

IF2ARB

IF2MCTR

IF2DTA_L

IF2DTB_L

BTR

IF2DTA_B

IF2DTB_B

INTR

TREQR

NEWDT

TESTR

INTPND

MSGVAL

BRPER


CTRLR

CAN Control Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLR CTRLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT IE SIE EIE DAR CCE TEST

INIT : Initialization bit
bits : 0 - -1 (0 bit)
access : read-write

IE : Interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write

SIE : Status interrupt code enable bit
bits : 2 - 1 (0 bit)
access : read-write

EIE : Error interrupt code enable bit
bits : 3 - 2 (0 bit)
access : read-write

DAR : Automatic retransmission disable bit
bits : 5 - 4 (0 bit)
access : read-write

CCE : Bit Timing Register write enable bit
bits : 6 - 5 (0 bit)
access : read-write

TEST : Test mode enable bit
bits : 7 - 6 (0 bit)
access : read-write


IF1CREQ

IF1 Command Request Register [BHW]
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1CREQ IF1CREQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MESSAGENUMBER BUSY

MESSAGENUMBER : Message number
bits : 0 - 6 (7 bit)
access : read-write

BUSY : Busy flag bit
bits : 15 - 14 (0 bit)
access : read-write


IF1CMSK

IF1 Command Mask Register [BHW]
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1CMSK IF1CMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATAB DATAA NEWDAT CIP CONTROL ARB MASK WR_RD

DATAB : Data 4-7 update bit
bits : 0 - -1 (0 bit)
access : read-write

DATAA : Data 0-3 update bit
bits : 1 - 0 (0 bit)
access : read-write

NEWDAT : Message transmission request bit
bits : 2 - 1 (0 bit)
access : read-write

CIP : Interrupt clear bit
bits : 3 - 2 (0 bit)
access : read-write

CONTROL : Control data update bit
bits : 4 - 3 (0 bit)
access : read-write

ARB : Arbitration data update bit
bits : 5 - 4 (0 bit)
access : read-write

MASK : Mask data update bit
bits : 6 - 5 (0 bit)
access : read-write

WR_RD : Writing or reading control bit
bits : 7 - 6 (0 bit)
access : read-write


IF1MSK

IF1 Mask Registers [BHW]
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1MSK IF1MSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSK MDIR MXTD

MSK : Msk
bits : 0 - 27 (28 bit)
access : read-write

MDIR : MDir
bits : 30 - 29 (0 bit)
access : read-write

MXTD : MXtd
bits : 31 - 30 (0 bit)
access : read-write


IF1ARB

IF1 Arbitration Registers [BHW]
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1ARB IF1ARB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID DIR XTD MSGVAL

ID : ID
bits : 0 - 27 (28 bit)
access : read-write

DIR : Dir
bits : 29 - 28 (0 bit)
access : read-write

XTD : Xtd
bits : 30 - 29 (0 bit)
access : read-write

MSGVAL : MsgVal
bits : 31 - 30 (0 bit)
access : read-write


IF1MCTR

IF1 Message Control Register [BHW]
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1MCTR IF1MCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC EOB TXRQST RMTEN RXIE TXIE UMASK INTPND MSGLST NEWDAT

DLC : DLC
bits : 0 - 2 (3 bit)
access : read-write

EOB : EoB
bits : 7 - 6 (0 bit)
access : read-write

TXRQST : TxRqst
bits : 8 - 7 (0 bit)
access : read-write

RMTEN : RmtEn
bits : 9 - 8 (0 bit)
access : read-write

RXIE : RxIE
bits : 10 - 9 (0 bit)
access : read-write

TXIE : TxIE
bits : 11 - 10 (0 bit)
access : read-write

UMASK : UMask
bits : 12 - 11 (0 bit)
access : read-write

INTPND : IntPnd
bits : 13 - 12 (0 bit)
access : read-write

MSGLST : MsgLst
bits : 14 - 13 (0 bit)
access : read-write

NEWDAT : NewDat
bits : 15 - 14 (0 bit)
access : read-write


STATR

CAN Status Register [BHW]
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATR STATR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEC TXOK RXOK EPASS EWARN BOFF

LEC : Last error code bits
bits : 0 - 1 (2 bit)
access : read-write

TXOK : Successful message transmission bit
bits : 3 - 2 (0 bit)
access : read-write

RXOK : Successful message reception bit
bits : 4 - 3 (0 bit)
access : read-write

EPASS : Error passive bit
bits : 5 - 4 (0 bit)
access : read-only

EWARN : Warning bit
bits : 6 - 5 (0 bit)
access : read-only

BOFF : Busoff bit
bits : 7 - 6 (0 bit)
access : read-only


IF1DTA_L

IF1 Data Registers A [BHW]
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DTA_L IF1DTA_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA0 DATA1 DATA2 DATA3

DATA0 : Data(0) Little Endian
bits : 0 - 6 (7 bit)
access : read-write

DATA1 : Data(1) Little Endian
bits : 8 - 14 (7 bit)
access : read-write

DATA2 : Data(2) Little Endian
bits : 16 - 22 (7 bit)
access : read-write

DATA3 : Data(3) Little Endian
bits : 24 - 30 (7 bit)
access : read-write


IF1DTB_L

IF1 Data Registers B [BHW]
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DTB_L IF1DTB_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA4 DATA5 DATA6 DATA7

DATA4 : Data(4) Little Endian
bits : 0 - 6 (7 bit)
access : read-write

DATA5 : Data(5) Little Endian
bits : 8 - 14 (7 bit)
access : read-write

DATA6 : Data(6) Little Endian
bits : 16 - 22 (7 bit)
access : read-write

DATA7 : Data(7) Little Endian
bits : 24 - 30 (7 bit)
access : read-write


IF1DTA_B

IF1 Data Registers A [BHW]
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DTA_B IF1DTA_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA3 DATA2 DATA1 DATA0

DATA3 : Data(3) Big Endian
bits : 0 - 6 (7 bit)
access : read-write

DATA2 : Data(2) Big Endian
bits : 8 - 14 (7 bit)
access : read-write

DATA1 : Data(1) Big Endian
bits : 16 - 22 (7 bit)
access : read-write

DATA0 : Data(0) Big Endian
bits : 24 - 30 (7 bit)
access : read-write


IF1DTB_B

IF1 Data Registers B [BHW]
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DTB_B IF1DTB_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA7 DATA6 DATA5 DATA4

DATA7 : Data(7) Big Endian
bits : 0 - 6 (7 bit)
access : read-write

DATA6 : Data(6) Big Endian
bits : 8 - 14 (7 bit)
access : read-write

DATA5 : Data(5) Big Endian
bits : 16 - 22 (7 bit)
access : read-write

DATA4 : Data(4) Big Endian
bits : 24 - 30 (7 bit)
access : read-write


ERRCNT

CAN Error Counter [BHW]
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ERRCNT ERRCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEC REC RP

TEC : Send error counter
bits : 0 - 6 (7 bit)
access : read-only

REC : Receive error counter
bits : 8 - 13 (6 bit)
access : read-only

RP : Receive error passive indication
bits : 15 - 14 (0 bit)
access : read-only


IF2CREQ

IF2 Command Request Register [BHW]
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2CREQ IF2CREQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MESSAGENUMBER BUSY

MESSAGENUMBER : Message number
bits : 0 - 6 (7 bit)
access : read-write

BUSY : Busy flag bit
bits : 15 - 14 (0 bit)
access : read-write


IF2CMSK

IF2 Command Mask Register [BHW]
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2CMSK IF2CMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATAB DATAA NEWDAT CIP CONTROL ARB MASK WR_RD

DATAB : Data 4-7 update bit
bits : 0 - -1 (0 bit)
access : read-write

DATAA : Data 0-3 update bit
bits : 1 - 0 (0 bit)
access : read-write

NEWDAT : Message transmission request bit
bits : 2 - 1 (0 bit)
access : read-write

CIP : Interrupt clear bit
bits : 3 - 2 (0 bit)
access : read-write

CONTROL : Control data update bit
bits : 4 - 3 (0 bit)
access : read-write

ARB : Arbitration data update bit
bits : 5 - 4 (0 bit)
access : read-write

MASK : Mask data update bit
bits : 6 - 5 (0 bit)
access : read-write

WR_RD : Writing or reading control bit
bits : 7 - 6 (0 bit)
access : read-write


IF2MSK

IF2 Mask Registers [BHW]
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2MSK IF2MSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSK MDIR MXTD

MSK : Msk
bits : 0 - 27 (28 bit)
access : read-write

MDIR : MDir
bits : 30 - 29 (0 bit)
access : read-write

MXTD : MXtd
bits : 31 - 30 (0 bit)
access : read-write


IF2ARB

IF2 Arbitration Registers [BHW]
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2ARB IF2ARB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID DIR XTD MSGVAL

ID : ID
bits : 0 - 27 (28 bit)
access : read-write

DIR : Dir
bits : 29 - 28 (0 bit)
access : read-write

XTD : Xtd
bits : 30 - 29 (0 bit)
access : read-write

MSGVAL : MsgVal
bits : 31 - 30 (0 bit)
access : read-write


IF2MCTR

IF2 Message Control Register [BHW]
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2MCTR IF2MCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC EOB TXRQST RMTEN RXIE TXIE UMASK INTPND MSGLST NEWDAT

DLC : DLC
bits : 0 - 2 (3 bit)
access : read-write

EOB : EoB
bits : 7 - 6 (0 bit)
access : read-write

TXRQST : TxRqst
bits : 8 - 7 (0 bit)
access : read-write

RMTEN : RmtEn
bits : 9 - 8 (0 bit)
access : read-write

RXIE : RxIE
bits : 10 - 9 (0 bit)
access : read-write

TXIE : TxIE
bits : 11 - 10 (0 bit)
access : read-write

UMASK : UMask
bits : 12 - 11 (0 bit)
access : read-write

INTPND : IntPnd
bits : 13 - 12 (0 bit)
access : read-write

MSGLST : MsgLst
bits : 14 - 13 (0 bit)
access : read-write

NEWDAT : NewDat
bits : 15 - 14 (0 bit)
access : read-write


IF2DTA_L

IF2 Data Registers A [BHW]
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DTA_L IF2DTA_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA0 DATA1 DATA2 DATA3

DATA0 : Data(0) Little Endian
bits : 0 - 6 (7 bit)
access : read-write

DATA1 : Data(1) Little Endian
bits : 8 - 14 (7 bit)
access : read-write

DATA2 : Data(2) Little Endian
bits : 16 - 22 (7 bit)
access : read-write

DATA3 : Data(3) Little Endian
bits : 24 - 30 (7 bit)
access : read-write


IF2DTB_L

IF2 Data Registers B [BHW]
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DTB_L IF2DTB_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA4 DATA5 DATA6 DATA7

DATA4 : Data(4) Little Endian
bits : 0 - 6 (7 bit)
access : read-write

DATA5 : Data(5) Little Endian
bits : 8 - 14 (7 bit)
access : read-write

DATA6 : Data(6) Little Endian
bits : 16 - 22 (7 bit)
access : read-write

DATA7 : Data(7) Little Endian
bits : 24 - 30 (7 bit)
access : read-write


BTR

CAN Bit Timing Register [BHW]
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR BTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRP SJW TSEG1 TSEG2

BRP : Baud rate prescaler setting bits
bits : 0 - 4 (5 bit)
access : read-write

SJW : Resynchronization jump width setting bits
bits : 6 - 6 (1 bit)
access : read-write

TSEG1 : Time segment 1 setting bits
bits : 8 - 10 (3 bit)
access : read-write

TSEG2 : Time segment 2 setting bits
bits : 12 - 13 (2 bit)
access : read-write


IF2DTA_B

IF2 Data Registers A [BHW]
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DTA_B IF2DTA_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA3 DATA2 DATA1 DATA0

DATA3 : Data(3) Big Endian
bits : 0 - 6 (7 bit)
access : read-write

DATA2 : Data(2) Big Endian
bits : 8 - 14 (7 bit)
access : read-write

DATA1 : Data(1) Big Endian
bits : 16 - 22 (7 bit)
access : read-write

DATA0 : Data(0) Big Endian
bits : 24 - 30 (7 bit)
access : read-write


IF2DTB_B

IF2 Data Registers B [BHW]
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DTB_B IF2DTB_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA7 DATA6 DATA5 DATA4

DATA7 : Data(7) Big Endian
bits : 0 - 6 (7 bit)
access : read-write

DATA6 : Data(6) Big Endian
bits : 8 - 14 (7 bit)
access : read-write

DATA5 : Data(5) Big Endian
bits : 16 - 22 (7 bit)
access : read-write

DATA4 : Data(4) Big Endian
bits : 24 - 30 (7 bit)
access : read-write


INTR

CAN Interrupt Register [BHW]
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTID

INTID : Interrupt Code
bits : 0 - 14 (15 bit)
access : read-only


TREQR

CAN Transmit Request Registers [BHW]
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TREQR TREQR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXRQST1 TXRQST2 TXRQST3 TXRQST4 TXRQST5 TXRQST6 TXRQST7 TXRQST8 TXRQST9 TXRQST10 TXRQST11 TXRQST12 TXRQST13 TXRQST14 TXRQST15 TXRQST16 TXRQST17 TXRQST18 TXRQST19 TXRQST20 TXRQST21 TXRQST22 TXRQST23 TXRQST24 TXRQST25 TXRQST26 TXRQST27 TXRQST28 TXRQST29 TXRQST30 TXRQST31 TXRQST32

TXRQST1 : Bit0 of TREQR
bits : 0 - -1 (0 bit)
access : read-only

TXRQST2 : Bit1 of TREQR
bits : 1 - 0 (0 bit)
access : read-only

TXRQST3 : Bit2 of TREQR
bits : 2 - 1 (0 bit)
access : read-only

TXRQST4 : Bit3 of TREQR
bits : 3 - 2 (0 bit)
access : read-only

TXRQST5 : Bit4 of TREQR
bits : 4 - 3 (0 bit)
access : read-only

TXRQST6 : Bit5 of TREQR
bits : 5 - 4 (0 bit)
access : read-only

TXRQST7 : Bit6 of TREQR
bits : 6 - 5 (0 bit)
access : read-only

TXRQST8 : Bit7 of TREQR
bits : 7 - 6 (0 bit)
access : read-only

TXRQST9 : Bit8 of TREQR
bits : 8 - 7 (0 bit)
access : read-only

TXRQST10 : Bit9 of TREQR
bits : 9 - 8 (0 bit)
access : read-only

TXRQST11 : Bit10 of TREQR
bits : 10 - 9 (0 bit)
access : read-only

TXRQST12 : Bit11 of TREQR
bits : 11 - 10 (0 bit)
access : read-only

TXRQST13 : Bit12 of TREQR
bits : 12 - 11 (0 bit)
access : read-only

TXRQST14 : Bit13 of TREQR
bits : 13 - 12 (0 bit)
access : read-only

TXRQST15 : Bit14 of TREQR
bits : 14 - 13 (0 bit)
access : read-only

TXRQST16 : Bit15 of TREQR
bits : 15 - 14 (0 bit)
access : read-only

TXRQST17 : Bit16 of TREQR
bits : 16 - 15 (0 bit)
access : read-only

TXRQST18 : Bit17 of TREQR
bits : 17 - 16 (0 bit)
access : read-only

TXRQST19 : Bit18 of TREQR
bits : 18 - 17 (0 bit)
access : read-only

TXRQST20 : Bit19 of TREQR
bits : 19 - 18 (0 bit)
access : read-only

TXRQST21 : Bit20 of TREQR
bits : 20 - 19 (0 bit)
access : read-only

TXRQST22 : Bit21 of TREQR
bits : 21 - 20 (0 bit)
access : read-only

TXRQST23 : Bit22 of TREQR
bits : 22 - 21 (0 bit)
access : read-only

TXRQST24 : Bit23 of TREQR
bits : 23 - 22 (0 bit)
access : read-only

TXRQST25 : Bit24 of TREQR
bits : 24 - 23 (0 bit)
access : read-only

TXRQST26 : Bit25 of TREQR
bits : 25 - 24 (0 bit)
access : read-only

TXRQST27 : Bit26 of TREQR
bits : 26 - 25 (0 bit)
access : read-only

TXRQST28 : Bit27 of TREQR
bits : 27 - 26 (0 bit)
access : read-only

TXRQST29 : Bit28 of TREQR
bits : 28 - 27 (0 bit)
access : read-only

TXRQST30 : Bit29 of TREQR
bits : 29 - 28 (0 bit)
access : read-only

TXRQST31 : Bit30 of TREQR
bits : 30 - 29 (0 bit)
access : read-only

TXRQST32 : Bit31 of TREQR
bits : 31 - 30 (0 bit)
access : read-only


NEWDT

CAN New Data Registers [BHW]
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NEWDT NEWDT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NEWDAT1 NEWDAT2 NEWDAT3 NEWDAT4 NEWDAT5 NEWDAT6 NEWDAT7 NEWDAT8 NEWDAT9 NEWDAT10 NEWDAT11 NEWDAT12 NEWDAT13 NEWDAT14 NEWDAT15 NEWDAT16 NEWDAT17 NEWDAT18 NEWDAT19 NEWDAT20 NEWDAT21 NEWDAT22 NEWDAT23 NEWDAT24 NEWDAT25 NEWDAT26 NEWDAT27 NEWDAT28 NEWDAT29 NEWDAT30 NEWDAT31 NEWDAT32

NEWDAT1 : Bit0 of NEWDT
bits : 0 - -1 (0 bit)
access : read-only

NEWDAT2 : Bit1 of NEWDT
bits : 1 - 0 (0 bit)
access : read-only

NEWDAT3 : Bit2 of NEWDT
bits : 2 - 1 (0 bit)
access : read-only

NEWDAT4 : Bit3 of NEWDT
bits : 3 - 2 (0 bit)
access : read-only

NEWDAT5 : Bit4 of NEWDT
bits : 4 - 3 (0 bit)
access : read-only

NEWDAT6 : Bit5 of NEWDT
bits : 5 - 4 (0 bit)
access : read-only

NEWDAT7 : Bit6 of NEWDT
bits : 6 - 5 (0 bit)
access : read-only

NEWDAT8 : Bit7 of NEWDT
bits : 7 - 6 (0 bit)
access : read-only

NEWDAT9 : Bit8 of NEWDT
bits : 8 - 7 (0 bit)
access : read-only

NEWDAT10 : Bit9 of NEWDT
bits : 9 - 8 (0 bit)
access : read-only

NEWDAT11 : Bit10 of NEWDT
bits : 10 - 9 (0 bit)
access : read-only

NEWDAT12 : Bit11 of NEWDT
bits : 11 - 10 (0 bit)
access : read-only

NEWDAT13 : Bit12 of NEWDT
bits : 12 - 11 (0 bit)
access : read-only

NEWDAT14 : Bit13 of NEWDT
bits : 13 - 12 (0 bit)
access : read-only

NEWDAT15 : Bit14 of NEWDT
bits : 14 - 13 (0 bit)
access : read-only

NEWDAT16 : Bit15 of NEWDT
bits : 15 - 14 (0 bit)
access : read-only

NEWDAT17 : Bit16 of NEWDT
bits : 16 - 15 (0 bit)
access : read-only

NEWDAT18 : Bit17 of NEWDT
bits : 17 - 16 (0 bit)
access : read-only

NEWDAT19 : Bit18 of NEWDT
bits : 18 - 17 (0 bit)
access : read-only

NEWDAT20 : Bit19 of NEWDT
bits : 19 - 18 (0 bit)
access : read-only

NEWDAT21 : Bit20 of NEWDT
bits : 20 - 19 (0 bit)
access : read-only

NEWDAT22 : Bit21 of NEWDT
bits : 21 - 20 (0 bit)
access : read-only

NEWDAT23 : Bit22 of NEWDT
bits : 22 - 21 (0 bit)
access : read-only

NEWDAT24 : Bit23 of NEWDT
bits : 23 - 22 (0 bit)
access : read-only

NEWDAT25 : Bit24 of NEWDT
bits : 24 - 23 (0 bit)
access : read-only

NEWDAT26 : Bit25 of NEWDT
bits : 25 - 24 (0 bit)
access : read-only

NEWDAT27 : Bit26 of NEWDT
bits : 26 - 25 (0 bit)
access : read-only

NEWDAT28 : Bit27 of NEWDT
bits : 27 - 26 (0 bit)
access : read-only

NEWDAT29 : Bit28 of NEWDT
bits : 28 - 27 (0 bit)
access : read-only

NEWDAT30 : Bit29 of NEWDT
bits : 29 - 28 (0 bit)
access : read-only

NEWDAT31 : Bit30 of NEWDT
bits : 30 - 29 (0 bit)
access : read-only

NEWDAT32 : Bit31 of NEWDT
bits : 31 - 30 (0 bit)
access : read-only


TESTR

CAN Test Register [BHW]
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TESTR TESTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASIC SILENT LBACK TX RX

BASIC : Basic mode
bits : 2 - 1 (0 bit)
access : read-write

SILENT : Silent mode
bits : 3 - 2 (0 bit)
access : read-write

LBACK : Loop back mode
bits : 4 - 3 (0 bit)
access : read-write

TX : TX pin control bit
bits : 5 - 5 (1 bit)
access : read-write

RX : Rx pin monitor bit
bits : 7 - 6 (0 bit)
access : read-only


INTPND

CAN Interrupt Pending Registers [BHW]
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTPND INTPND read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPND1 INTPND2 INTPND3 INTPND4 INTPND5 INTPND6 INTPND7 INTPND8 INTPND9 INTPND10 INTPND11 INTPND12 INTPND13 INTPND14 INTPND15 INTPND16 INTPND17 INTPND18 INTPND19 INTPND20 INTPND21 INTPND22 INTPND23 INTPND24 INTPND25 INTPND26 INTPND27 INTPND28 INTPND29 INTPND30 INTPND31 INTPND32

INTPND1 : Bit0 of INTPND
bits : 0 - -1 (0 bit)
access : read-only

INTPND2 : Bit1 of INTPND
bits : 1 - 0 (0 bit)
access : read-only

INTPND3 : Bit2 of INTPND
bits : 2 - 1 (0 bit)
access : read-only

INTPND4 : Bit3 of INTPND
bits : 3 - 2 (0 bit)
access : read-only

INTPND5 : Bit4 of INTPND
bits : 4 - 3 (0 bit)
access : read-only

INTPND6 : Bit5 of INTPND
bits : 5 - 4 (0 bit)
access : read-only

INTPND7 : Bit6 of INTPND
bits : 6 - 5 (0 bit)
access : read-only

INTPND8 : Bit7 of INTPND
bits : 7 - 6 (0 bit)
access : read-only

INTPND9 : Bit8 of INTPND
bits : 8 - 7 (0 bit)
access : read-only

INTPND10 : Bit9 of INTPND
bits : 9 - 8 (0 bit)
access : read-only

INTPND11 : Bit10 of INTPND
bits : 10 - 9 (0 bit)
access : read-only

INTPND12 : Bit11 of INTPND
bits : 11 - 10 (0 bit)
access : read-only

INTPND13 : Bit12 of INTPND
bits : 12 - 11 (0 bit)
access : read-only

INTPND14 : Bit13 of INTPND
bits : 13 - 12 (0 bit)
access : read-only

INTPND15 : Bit14 of INTPND
bits : 14 - 13 (0 bit)
access : read-only

INTPND16 : Bit15 of INTPND
bits : 15 - 14 (0 bit)
access : read-only

INTPND17 : Bit16 of INTPND
bits : 16 - 15 (0 bit)
access : read-only

INTPND18 : Bit17 of INTPND
bits : 17 - 16 (0 bit)
access : read-only

INTPND19 : Bit18 of INTPND
bits : 18 - 17 (0 bit)
access : read-only

INTPND20 : Bit19 of INTPND
bits : 19 - 18 (0 bit)
access : read-only

INTPND21 : Bit20 of INTPND
bits : 20 - 19 (0 bit)
access : read-only

INTPND22 : Bit21 of INTPND
bits : 21 - 20 (0 bit)
access : read-only

INTPND23 : Bit22 of INTPND
bits : 22 - 21 (0 bit)
access : read-only

INTPND24 : Bit23 of INTPND
bits : 23 - 22 (0 bit)
access : read-only

INTPND25 : Bit24 of INTPND
bits : 24 - 23 (0 bit)
access : read-only

INTPND26 : Bit25 of INTPND
bits : 25 - 24 (0 bit)
access : read-only

INTPND27 : Bit26 of INTPND
bits : 26 - 25 (0 bit)
access : read-only

INTPND28 : Bit27 of INTPND
bits : 27 - 26 (0 bit)
access : read-only

INTPND29 : Bit28 of INTPND
bits : 28 - 27 (0 bit)
access : read-only

INTPND30 : Bit29 of INTPND
bits : 29 - 28 (0 bit)
access : read-only

INTPND31 : Bit30 of INTPND
bits : 30 - 29 (0 bit)
access : read-only

INTPND32 : Bit31 of INTPND
bits : 31 - 30 (0 bit)
access : read-only


MSGVAL

CAN Message Valid Register [BHW]
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSGVAL MSGVAL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSGVAL1 MSGVAL2 MSGVAL3 MSGVAL4 MSGVAL5 MSGVAL6 MSGVAL7 MSGVAL8 MSGVAL9 MSGVAL10 MSGVAL11 MSGVAL12 MSGVAL13 MSGVAL14 MSGVAL15 MSGVAL16 MSGVAL17 MSGVAL18 MSGVAL19 MSGVAL20 MSGVAL21 MSGVAL22 MSGVAL23 MSGVAL24 MSGVAL25 MSGVAL26 MSGVAL27 MSGVAL28 MSGVAL29 MSGVAL30 MSGVAL31 MSGVAL32

MSGVAL1 : Bit0 of MSGVAL
bits : 0 - -1 (0 bit)
access : read-only

MSGVAL2 : Bit1 of MSGVAL
bits : 1 - 0 (0 bit)
access : read-only

MSGVAL3 : Bit2 of MSGVAL
bits : 2 - 1 (0 bit)
access : read-only

MSGVAL4 : Bit3 of MSGVAL
bits : 3 - 2 (0 bit)
access : read-only

MSGVAL5 : Bit4 of MSGVAL
bits : 4 - 3 (0 bit)
access : read-only

MSGVAL6 : Bit5 of MSGVAL
bits : 5 - 4 (0 bit)
access : read-only

MSGVAL7 : Bit6 of MSGVAL
bits : 6 - 5 (0 bit)
access : read-only

MSGVAL8 : Bit7 of MSGVAL
bits : 7 - 6 (0 bit)
access : read-only

MSGVAL9 : Bit8 of MSGVAL
bits : 8 - 7 (0 bit)
access : read-only

MSGVAL10 : Bit9 of MSGVAL
bits : 9 - 8 (0 bit)
access : read-only

MSGVAL11 : Bit10 of MSGVAL
bits : 10 - 9 (0 bit)
access : read-only

MSGVAL12 : Bit11 of MSGVAL
bits : 11 - 10 (0 bit)
access : read-only

MSGVAL13 : Bit12 of MSGVAL
bits : 12 - 11 (0 bit)
access : read-only

MSGVAL14 : Bit13 of MSGVAL
bits : 13 - 12 (0 bit)
access : read-only

MSGVAL15 : Bit14 of MSGVAL
bits : 14 - 13 (0 bit)
access : read-only

MSGVAL16 : Bit15 of MSGVAL
bits : 15 - 14 (0 bit)
access : read-only

MSGVAL17 : Bit16 of MSGVAL
bits : 16 - 15 (0 bit)
access : read-only

MSGVAL18 : Bit17 of MSGVAL
bits : 17 - 16 (0 bit)
access : read-only

MSGVAL19 : Bit18 of MSGVAL
bits : 18 - 17 (0 bit)
access : read-only

MSGVAL20 : Bit19 of MSGVAL
bits : 19 - 18 (0 bit)
access : read-only

MSGVAL21 : Bit20 of MSGVAL
bits : 20 - 19 (0 bit)
access : read-only

MSGVAL22 : Bit21 of MSGVAL
bits : 21 - 20 (0 bit)
access : read-only

MSGVAL23 : Bit22 of MSGVAL
bits : 22 - 21 (0 bit)
access : read-only

MSGVAL24 : Bit23 of MSGVAL
bits : 23 - 22 (0 bit)
access : read-only

MSGVAL25 : Bit24 of MSGVAL
bits : 24 - 23 (0 bit)
access : read-only

MSGVAL26 : Bit25 of MSGVAL
bits : 25 - 24 (0 bit)
access : read-only

MSGVAL27 : Bit26 of MSGVAL
bits : 26 - 25 (0 bit)
access : read-only

MSGVAL28 : Bit27 of MSGVAL
bits : 27 - 26 (0 bit)
access : read-only

MSGVAL29 : Bit28 of MSGVAL
bits : 28 - 27 (0 bit)
access : read-only

MSGVAL30 : Bit29 of MSGVAL
bits : 29 - 28 (0 bit)
access : read-only

MSGVAL31 : Bit30 of MSGVAL
bits : 30 - 29 (0 bit)
access : read-only

MSGVAL32 : Bit31 of MSGVAL
bits : 31 - 30 (0 bit)
access : read-only


BRPER

CAN Prescaler Extension Register [BHW]
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRPER BRPER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRPE

BRPE : Baud rate prescaler extension bit
bits : 0 - 2 (3 bit)
access : read-write



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