\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSION : Internal high-speed clock enable
bits : 0 - 0 (1 bit)
access : read-write
HSIRDY : Internal high-speed clock ready flag
bits : 1 - 1 (1 bit)
access : read-only
MSION : MSI clock enable
bits : 8 - 8 (1 bit)
access : read-write
MSIRDY : MSI clock ready flag
bits : 9 - 9 (1 bit)
access : read-only
HSEON : HSE clock enable
bits : 16 - 16 (1 bit)
access : read-write
HSERDY : HSE clock ready flag
bits : 17 - 17 (1 bit)
access : read-only
HSEBYP : HSE clock bypass
bits : 18 - 18 (1 bit)
access : read-write
PLLON : PLL enable
bits : 24 - 24 (1 bit)
access : read-write
PLLRDY : PLL clock ready flag
bits : 25 - 25 (1 bit)
access : read-only
CSSON : Clock security system enable
bits : 28 - 28 (1 bit)
access : read-write
RTCPRE0 : RTCPRE0
bits : 29 - 29 (1 bit)
access : read-write
RTCPRE1 : TC/LCD prescaler
bits : 30 - 30 (1 bit)
access : read-write
AHB peripheral reset register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOARST : IO port A reset
bits : 0 - 0 (1 bit)
GPIOBRST : IO port B reset
bits : 1 - 1 (1 bit)
GPIOCRST : IO port C reset
bits : 2 - 2 (1 bit)
GPIODRST : IO port D reset
bits : 3 - 3 (1 bit)
GPIOERST : IO port E reset
bits : 4 - 4 (1 bit)
GPIOHRST : IO port H reset
bits : 5 - 5 (1 bit)
GPIOFRST : IO port F reset
bits : 6 - 6 (1 bit)
GPIOGRST : IO port G reset
bits : 7 - 7 (1 bit)
CRCRST : CRC reset
bits : 12 - 12 (1 bit)
FLITFRST : FLITF reset
bits : 15 - 15 (1 bit)
DMA1RST : DMA1 reset
bits : 24 - 24 (1 bit)
DMA2RST : DMA2 reset
bits : 25 - 25 (1 bit)
APB2 peripheral reset register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGRST : SYSCFGRST
bits : 0 - 0 (1 bit)
TIM9RST : TIM9RST
bits : 2 - 2 (1 bit)
TM10RST : TM10RST
bits : 3 - 3 (1 bit)
TM11RST : TM11RST
bits : 4 - 4 (1 bit)
ADC1RST : ADC1RST
bits : 9 - 9 (1 bit)
SPI1RST : SPI1RST
bits : 12 - 12 (1 bit)
USART1RST : USART1RST
bits : 14 - 14 (1 bit)
APB1 peripheral reset register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2RST : Timer 2 reset
bits : 0 - 0 (1 bit)
TIM3RST : Timer 3 reset
bits : 1 - 1 (1 bit)
TIM4RST : Timer 4 reset
bits : 2 - 2 (1 bit)
TIM5RST : Timer 5 reset
bits : 3 - 3 (1 bit)
TIM6RST : Timer 6reset
bits : 4 - 4 (1 bit)
TIM7RST : Timer 7 reset
bits : 5 - 5 (1 bit)
LCDRST : LCD reset
bits : 9 - 9 (1 bit)
WWDRST : Window watchdog reset
bits : 11 - 11 (1 bit)
SPI2RST : SPI 2 reset
bits : 14 - 14 (1 bit)
SPI3RST : SPI 3 reset
bits : 15 - 15 (1 bit)
USART2RST : USART 2 reset
bits : 17 - 17 (1 bit)
USART3RST : USART 3 reset
bits : 18 - 18 (1 bit)
I2C1RST : I2C 1 reset
bits : 21 - 21 (1 bit)
I2C2RST : I2C 2 reset
bits : 22 - 22 (1 bit)
USBRST : USB reset
bits : 23 - 23 (1 bit)
PWRRST : Power interface reset
bits : 28 - 28 (1 bit)
DACRST : DAC interface reset
bits : 29 - 29 (1 bit)
COMPRST : COMP interface reset
bits : 31 - 31 (1 bit)
AHB peripheral clock enable register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOPAEN : IO port A clock enable
bits : 0 - 0 (1 bit)
GPIOPBEN : IO port B clock enable
bits : 1 - 1 (1 bit)
GPIOPCEN : IO port C clock enable
bits : 2 - 2 (1 bit)
GPIOPDEN : IO port D clock enable
bits : 3 - 3 (1 bit)
GPIOPEEN : IO port E clock enable
bits : 4 - 4 (1 bit)
GPIOPHEN : IO port H clock enable
bits : 5 - 5 (1 bit)
GPIOPFEN : IO port F clock enable
bits : 6 - 6 (1 bit)
GPIOPGEN : IO port G clock enable
bits : 7 - 7 (1 bit)
CRCEN : CRC clock enable
bits : 12 - 12 (1 bit)
FLITFEN : FLITF clock enable
bits : 15 - 15 (1 bit)
DMA1EN : DMA1 clock enable
bits : 24 - 24 (1 bit)
DMA2EN : DMA2 clock enable
bits : 25 - 25 (1 bit)
APB2 peripheral clock enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGEN : System configuration controller clock enable
bits : 0 - 0 (1 bit)
TIM9EN : TIM9 timer clock enable
bits : 2 - 2 (1 bit)
TIM10EN : TIM10 timer clock enable
bits : 3 - 3 (1 bit)
TIM11EN : TIM11 timer clock enable
bits : 4 - 4 (1 bit)
ADC1EN : ADC1 interface clock enable
bits : 9 - 9 (1 bit)
SPI1EN : SPI 1 clock enable
bits : 12 - 12 (1 bit)
USART1EN : USART1 clock enable
bits : 14 - 14 (1 bit)
APB1 peripheral clock enable register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2EN : Timer 2 clock enable
bits : 0 - 0 (1 bit)
TIM3EN : Timer 3 clock enable
bits : 1 - 1 (1 bit)
TIM4EN : Timer 4 clock enable
bits : 2 - 2 (1 bit)
TIM5EN : Timer 5 clock enable
bits : 3 - 3 (1 bit)
TIM6EN : Timer 6 clock enable
bits : 4 - 4 (1 bit)
TIM7EN : Timer 7 clock enable
bits : 5 - 5 (1 bit)
LCDEN : LCD clock enable
bits : 9 - 9 (1 bit)
WWDGEN : Window watchdog clock enable
bits : 11 - 11 (1 bit)
SPI2EN : SPI 2 clock enable
bits : 14 - 14 (1 bit)
SPI3EN : SPI 3 clock enable
bits : 15 - 15 (1 bit)
USART2EN : USART 2 clock enable
bits : 17 - 17 (1 bit)
USART3EN : USART 3 clock enable
bits : 18 - 18 (1 bit)
I2C1EN : I2C 1 clock enable
bits : 21 - 21 (1 bit)
I2C2EN : I2C 2 clock enable
bits : 22 - 22 (1 bit)
USBEN : USB clock enable
bits : 23 - 23 (1 bit)
PWREN : Power interface clock enable
bits : 28 - 28 (1 bit)
DACEN : DAC interface clock enable
bits : 29 - 29 (1 bit)
COMPEN : COMP interface clock enable
bits : 31 - 31 (1 bit)
AHB peripheral clock enable in low power mode register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOALPEN : IO port A clock enable during Sleep mode
bits : 0 - 0 (1 bit)
GPIOBLPEN : IO port B clock enable during Sleep mode
bits : 1 - 1 (1 bit)
GPIOCLPEN : IO port C clock enable during Sleep mode
bits : 2 - 2 (1 bit)
GPIODLPEN : IO port D clock enable during Sleep mode
bits : 3 - 3 (1 bit)
GPIOELPEN : IO port E clock enable during Sleep mode
bits : 4 - 4 (1 bit)
GPIOHLPEN : IO port H clock enable during Sleep mode
bits : 5 - 5 (1 bit)
GPIOFLPEN : IO port F clock enable during Sleep mode
bits : 6 - 6 (1 bit)
GPIOGLPEN : IO port G clock enable during Sleep mode
bits : 7 - 7 (1 bit)
CRCLPEN : CRC clock enable during Sleep mode
bits : 12 - 12 (1 bit)
FLITFLPEN : FLITF clock enable during Sleep mode
bits : 15 - 15 (1 bit)
SRAMLPEN : SRAM clock enable during Sleep mode
bits : 16 - 16 (1 bit)
DMA1LPEN : DMA1 clock enable during Sleep mode
bits : 24 - 24 (1 bit)
DMA2LPEN : DMA2 clock enable during Sleep mode
bits : 25 - 25 (1 bit)
APB2 peripheral clock enable in low power mode register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGLPEN : System configuration controller clock enable during Sleep mode
bits : 0 - 0 (1 bit)
TIM9LPEN : TIM9 timer clock enable during Sleep mode
bits : 2 - 2 (1 bit)
TIM10LPEN : TIM10 timer clock enable during Sleep mode
bits : 3 - 3 (1 bit)
TIM11LPEN : TIM11 timer clock enable during Sleep mode
bits : 4 - 4 (1 bit)
ADC1LPEN : ADC1 interface clock enable during Sleep mode
bits : 9 - 9 (1 bit)
SPI1LPEN : SPI 1 clock enable during Sleep mode
bits : 12 - 12 (1 bit)
USART1LPEN : USART1 clock enable during Sleep mode
bits : 14 - 14 (1 bit)
APB1 peripheral clock enable in low power mode register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2LPEN : Timer 2 clock enable during Sleep mode
bits : 0 - 0 (1 bit)
TIM3LPEN : Timer 3 clock enable during Sleep mode
bits : 1 - 1 (1 bit)
TIM4LPEN : Timer 4 clock enable during Sleep mode
bits : 2 - 2 (1 bit)
TIM6LPEN : Timer 6 clock enable during Sleep mode
bits : 4 - 4 (1 bit)
TIM7LPEN : Timer 7 clock enable during Sleep mode
bits : 5 - 5 (1 bit)
LCDLPEN : LCD clock enable during Sleep mode
bits : 9 - 9 (1 bit)
WWDGLPEN : Window watchdog clock enable during Sleep mode
bits : 11 - 11 (1 bit)
SPI2LPEN : SPI 2 clock enable during Sleep mode
bits : 14 - 14 (1 bit)
USART2LPEN : USART 2 clock enable during Sleep mode
bits : 17 - 17 (1 bit)
USART3LPEN : USART 3 clock enable during Sleep mode
bits : 18 - 18 (1 bit)
I2C1LPEN : I2C 1 clock enable during Sleep mode
bits : 21 - 21 (1 bit)
I2C2LPEN : I2C 2 clock enable during Sleep mode
bits : 22 - 22 (1 bit)
USBLPEN : USB clock enable during Sleep mode
bits : 23 - 23 (1 bit)
PWRLPEN : Power interface clock enable during Sleep mode
bits : 28 - 28 (1 bit)
DACLPEN : DAC interface clock enable during Sleep mode
bits : 29 - 29 (1 bit)
COMPLPEN : COMP interface clock enable during Sleep mode
bits : 31 - 31 (1 bit)
Control/status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSION : Internal low-speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write
LSIRDY : Internal low-speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only
LSEON : External low-speed oscillator enable
bits : 8 - 8 (1 bit)
access : read-write
LSERDY : External low-speed oscillator ready
bits : 9 - 9 (1 bit)
access : read-only
LSEBYP : External low-speed oscillator bypass
bits : 10 - 10 (1 bit)
access : read-write
LSECSSON : CSS on LSE enable
bits : 11 - 11 (1 bit)
access : read-write
LSECSSD : CSS on LSE failure Detection
bits : 12 - 12 (1 bit)
access : read-only
RTCSEL : RTC and LCD clock source selection
bits : 16 - 17 (2 bit)
access : read-write
RTCEN : RTC clock enable
bits : 22 - 22 (1 bit)
access : read-write
RTCRST : RTC software reset
bits : 23 - 23 (1 bit)
access : read-write
RMVF : Remove reset flag
bits : 24 - 24 (1 bit)
access : read-write
OBLRSTF : Options bytes loading reset flag
bits : 25 - 25 (1 bit)
access : read-write
PINRSTF : PIN reset flag
bits : 26 - 26 (1 bit)
access : read-write
PORRSTF : POR/PDR reset flag
bits : 27 - 27 (1 bit)
access : read-write
SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-write
IWDGRSTF : Independent watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-write
WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-write
LPWRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-write
Internal clock sources calibration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSICAL : nternal high speed clock calibration
bits : 0 - 7 (8 bit)
access : read-only
HSITRIM : High speed internal clock trimming
bits : 8 - 12 (5 bit)
access : read-write
MSIRANGE : MSI clock ranges
bits : 13 - 15 (3 bit)
access : read-write
MSICAL : MSI clock calibration
bits : 16 - 23 (8 bit)
access : read-only
MSITRIM : MSI clock trimming
bits : 24 - 31 (8 bit)
access : read-write
Clock configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW : System clock switch
bits : 0 - 1 (2 bit)
access : read-write
SWS : System clock switch status
bits : 2 - 3 (2 bit)
access : read-only
HPRE : AHB prescaler
bits : 4 - 7 (4 bit)
access : read-write
PPRE1 : APB low-speed prescaler (APB1)
bits : 8 - 10 (3 bit)
access : read-write
PPRE2 : APB high-speed prescaler (APB2)
bits : 11 - 13 (3 bit)
access : read-write
PLLSRC : PLL entry clock source
bits : 16 - 16 (1 bit)
access : read-write
PLLMUL : PLL multiplication factor
bits : 18 - 21 (4 bit)
access : read-write
PLLDIV : PLL output division
bits : 22 - 23 (2 bit)
access : read-write
MCOSEL : Microcontroller clock output selection
bits : 24 - 26 (3 bit)
access : read-write
MCOPRE : Microcontroller clock output prescaler
bits : 28 - 30 (3 bit)
access : read-write
Clock interrupt register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYF : LSI ready interrupt flag
bits : 0 - 0 (1 bit)
access : read-only
LSERDYF : LSE ready interrupt flag
bits : 1 - 1 (1 bit)
access : read-only
HSIRDYF : HSI ready interrupt flag
bits : 2 - 2 (1 bit)
access : read-only
HSERDYF : HSE ready interrupt flag
bits : 3 - 3 (1 bit)
access : read-only
PLLRDYF : PLL ready interrupt flag
bits : 4 - 4 (1 bit)
access : read-only
MSIRDYF : MSI ready interrupt flag
bits : 5 - 5 (1 bit)
access : read-only
LSECSSF : LSE CSS Interrupt flag
bits : 6 - 6 (1 bit)
access : read-only
CSSF : Clock security system interrupt flag
bits : 7 - 7 (1 bit)
access : read-only
LSIRDYIE : LSI ready interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
LSERDYIE : LSE ready interrupt enable
bits : 9 - 9 (1 bit)
access : read-write
HSIRDYIE : HSI ready interrupt enable
bits : 10 - 10 (1 bit)
access : read-write
HSERDYIE : HSE ready interrupt enable
bits : 11 - 11 (1 bit)
access : read-write
PLLRDYIE : PLL ready interrupt enable
bits : 12 - 12 (1 bit)
access : read-write
MSIRDYIE : MSI ready interrupt enable
bits : 13 - 13 (1 bit)
access : read-write
LSECSSIE : LSE CSS interrupt enable
bits : 14 - 14 (1 bit)
access : read-write
LSIRDYC : LSI ready interrupt clear
bits : 16 - 16 (1 bit)
access : write-only
LSERDYC : LSE ready interrupt clear
bits : 17 - 17 (1 bit)
access : write-only
HSIRDYC : HSI ready interrupt clear
bits : 18 - 18 (1 bit)
access : write-only
HSERDYC : HSE ready interrupt clear
bits : 19 - 19 (1 bit)
access : write-only
PLLRDYC : PLL ready interrupt clear
bits : 20 - 20 (1 bit)
access : write-only
MSIRDYC : MSI ready interrupt clear
bits : 21 - 21 (1 bit)
access : write-only
LSECSSC : LSE CSS interrupt clear
bits : 22 - 22 (1 bit)
access : write-only
CSSC : Clock security system interrupt clear
bits : 23 - 23 (1 bit)
access : write-only
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