\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWD : Analog watchdog flag
bits : 0 - 0 (1 bit)
access : read-write
EOC : Regular channel end of conversion
bits : 1 - 1 (1 bit)
access : read-write
JEOC : Injected channel end of conversion
bits : 2 - 2 (1 bit)
access : read-write
JSTRT : Injected channel start flag
bits : 3 - 3 (1 bit)
access : read-write
STRT : Regular channel start flag
bits : 4 - 4 (1 bit)
access : read-write
OVR : Overrun
bits : 5 - 5 (1 bit)
access : read-write
ADONS : ADC ON status
bits : 6 - 6 (1 bit)
access : read-only
RCNR : Regular channel not ready
bits : 8 - 8 (1 bit)
access : read-only
JCNR : Injected channel not ready
bits : 9 - 9 (1 bit)
access : read-only
sample time register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SampletimebitsSMPx_x : Reserved
bits : 0 - 31 (32 bit)
sample time register 3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SampletimebitsSMPx_x : Reserved
bits : 0 - 31 (32 bit)
injected channel data offset register x
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JOFFSET1 : Data offset for injected channel x
bits : 0 - 11 (12 bit)
injected channel data offset register x
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JOFFSET2 : Data offset for injected channel x
bits : 0 - 11 (12 bit)
injected channel data offset register x
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JOFFSET3 : Data offset for injected channel x
bits : 0 - 11 (12 bit)
injected channel data offset register x
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JOFFSET4 : Data offset for injected channel x
bits : 0 - 11 (12 bit)
watchdog higher threshold register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HT : Analog watchdog higher threshold
bits : 0 - 11 (12 bit)
watchdog lower threshold register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LT : Analog watchdog lower threshold
bits : 0 - 11 (12 bit)
regular sequence register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ25 : 25th conversion in regular sequence
bits : 0 - 4 (5 bit)
SQ26 : 26th conversion in regular sequence
bits : 5 - 9 (5 bit)
SQ27 : 27th conversion in regular sequence
bits : 10 - 14 (5 bit)
SQ28 : 28th conversion in regular sequence
bits : 15 - 19 (5 bit)
L : Regular channel sequence length
bits : 20 - 23 (4 bit)
regular sequence register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ19 : 19th conversion in regular sequence
bits : 0 - 4 (5 bit)
SQ20 : 20th conversion in regular sequence
bits : 5 - 9 (5 bit)
SQ21 : 21st conversion in regular sequence
bits : 10 - 14 (5 bit)
SQ22 : 22nd conversion in regular sequence
bits : 15 - 19 (5 bit)
SQ23 : 23rd conversion in regular sequence
bits : 20 - 24 (5 bit)
SQ24 : 24th conversion in regular sequence
bits : 25 - 29 (5 bit)
regular sequence register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ13 : 13th conversion in regular sequence
bits : 0 - 4 (5 bit)
SQ14 : 14th conversion in regular sequence
bits : 5 - 9 (5 bit)
SQ15 : 15th conversion in regular sequence
bits : 10 - 14 (5 bit)
SQ16 : 16th conversion in regular sequence
bits : 15 - 19 (5 bit)
SQ17 : 17th conversion in regular sequence
bits : 20 - 24 (5 bit)
SQ18 : 18th conversion in regular sequence
bits : 25 - 29 (5 bit)
regular sequence register 4
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ7 : 7th conversion in regular sequence
bits : 0 - 4 (5 bit)
SQ8 : 8th conversion in regular sequence
bits : 5 - 9 (5 bit)
SQ9 : 9th conversion in regular sequence
bits : 10 - 14 (5 bit)
SQ10 : 10th conversion in regular sequence
bits : 15 - 19 (5 bit)
SQ11 : 11th conversion in regular sequence
bits : 20 - 24 (5 bit)
SQ12 : 12th conversion in regular sequence
bits : 25 - 29 (5 bit)
control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWDCH : Analog watchdog channel select bits
bits : 0 - 4 (5 bit)
EOCIE : Interrupt enable for EOC
bits : 5 - 5 (1 bit)
AWDIE : Analog watchdog interrupt enable
bits : 6 - 6 (1 bit)
JEOCIE : Interrupt enable for injected channels
bits : 7 - 7 (1 bit)
SCAN : Scan mode
bits : 8 - 8 (1 bit)
AWDSGL : Enable the watchdog on a single channel in scan mode
bits : 9 - 9 (1 bit)
JAUTO : Automatic injected group conversion
bits : 10 - 10 (1 bit)
DISCEN : Discontinuous mode on regular channels
bits : 11 - 11 (1 bit)
JDISCEN : Discontinuous mode on injected channels
bits : 12 - 12 (1 bit)
DISCNUM : Discontinuous mode channel count
bits : 13 - 15 (3 bit)
PDD : Power down during the delay phase
bits : 16 - 16 (1 bit)
PDI : Power down during the idle phase
bits : 17 - 17 (1 bit)
JAWDEN : Analog watchdog enable on injected channels
bits : 22 - 22 (1 bit)
AWDEN : Analog watchdog enable on regular channels
bits : 23 - 23 (1 bit)
RES : Resolution
bits : 24 - 25 (2 bit)
OVRIE : Overrun interrupt enable
bits : 26 - 26 (1 bit)
regular sequence register 5
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ1 : 1st conversion in regular sequence
bits : 0 - 4 (5 bit)
SQ2 : 2nd conversion in regular sequence
bits : 5 - 9 (5 bit)
SQ3 : 3rd conversion in regular sequence
bits : 10 - 14 (5 bit)
SQ4 : 4th conversion in regular sequence
bits : 15 - 19 (5 bit)
SQ5 : 5th conversion in regular sequence
bits : 20 - 24 (5 bit)
SQ6 : 6th conversion in regular sequence
bits : 25 - 29 (5 bit)
injected sequence register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JSQ1 : 1st conversion in injected sequence
bits : 0 - 4 (5 bit)
JSQ2 : 2nd conversion in injected sequence
bits : 5 - 9 (5 bit)
JSQ3 : 3rd conversion in injected sequence
bits : 10 - 14 (5 bit)
JSQ4 : 4th conversion in injected sequence
bits : 15 - 19 (5 bit)
JL : Injected sequence length
bits : 20 - 21 (2 bit)
injected data register x
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data
bits : 0 - 15 (16 bit)
injected data register x
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data
bits : 0 - 15 (16 bit)
injected data register x
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data
bits : 0 - 15 (16 bit)
injected data register x
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data
bits : 0 - 15 (16 bit)
regular data register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RegularDATA : Regular data
bits : 0 - 15 (16 bit)
sample time register 0
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SampletimebitsSMPx_x : Reserved
bits : 0 - 31 (32 bit)
control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADON : A/D Converter ON / OFF
bits : 0 - 0 (1 bit)
CONT : Continuous conversion
bits : 1 - 1 (1 bit)
ADC_CFG : ADC configuration
bits : 2 - 2 (1 bit)
DELS : Delay selection
bits : 4 - 6 (3 bit)
DMA : Direct memory access mode
bits : 8 - 8 (1 bit)
DDS : DMA disable selection
bits : 9 - 9 (1 bit)
EOCS : End of conversion selection
bits : 10 - 10 (1 bit)
ALIGN : Data alignment
bits : 11 - 11 (1 bit)
JEXTSEL : External event select for injected group
bits : 16 - 19 (4 bit)
JEXTEN : External trigger enable for injected channels
bits : 20 - 21 (2 bit)
JSWSTART : Start conversion of injected channels
bits : 22 - 22 (1 bit)
EXTSEL : External event select for regular group
bits : 24 - 27 (4 bit)
EXTEN : External trigger enable for regular channels
bits : 28 - 29 (2 bit)
SWSTART : Start conversion of regular channels
bits : 30 - 30 (1 bit)
sample time register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SampletimebitsSMPx_x : Reserved
bits : 0 - 31 (32 bit)
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