\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSION : MSI clock enable
bits : 0 - 0 (1 bit)
access : read-write
MSIRDY : MSI clock ready flag
bits : 1 - 1 (1 bit)
access : read-only
MSIPLLEN : MSI clock PLL enable
bits : 2 - 2 (1 bit)
access : read-write
MSIRGSEL : MSI clock range selection
bits : 3 - 3 (1 bit)
access : write-only
MSIRANGE : MSI clock ranges
bits : 4 - 7 (4 bit)
access : read-write
HSION : HSI clock enable
bits : 8 - 8 (1 bit)
access : read-write
HSIKERON : HSI always enable for peripheral kernels
bits : 9 - 9 (1 bit)
access : read-write
HSIRDY : HSI clock ready flag
bits : 10 - 10 (1 bit)
access : read-only
HSIASFS : HSI automatic start from Stop
bits : 11 - 11 (1 bit)
access : read-write
HSEON : HSE clock enable
bits : 16 - 16 (1 bit)
access : read-write
HSERDY : HSE clock ready flag
bits : 17 - 17 (1 bit)
access : read-only
HSEBYP : HSE crystal oscillator bypass
bits : 18 - 18 (1 bit)
access : read-write
CSSON : Clock security system enable
bits : 19 - 19 (1 bit)
access : write-only
PLLON : Main PLL enable
bits : 24 - 24 (1 bit)
access : read-write
PLLRDY : Main PLL clock ready flag
bits : 25 - 25 (1 bit)
access : read-only
PLLSAI1ON : SAI1 PLL enable
bits : 26 - 26 (1 bit)
access : read-write
PLLSAI1RDY : SAI1 PLL clock ready flag
bits : 27 - 27 (1 bit)
access : read-only
PLLSAI2ON : SAI2 PLL enable
bits : 28 - 28 (1 bit)
access : read-write
PLLSAI2RDY : SAI2 PLL clock ready flag
bits : 29 - 29 (1 bit)
access : read-only
PLLSAI1 configuration register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLSAI1M : Division factor for PLLSAI1 input clock
bits : 4 - 7 (4 bit)
PLLSAI1N : SAI1PLL multiplication factor for VCO
bits : 8 - 14 (7 bit)
PLLSAI1PEN : SAI1PLL PLLSAI1CLK output enable
bits : 16 - 16 (1 bit)
PLLSAI1P : SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)
bits : 17 - 17 (1 bit)
PLLSAI1QEN : SAI1PLL PLLUSB2CLK output enable
bits : 20 - 20 (1 bit)
PLLSAI1Q : SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)
bits : 21 - 22 (2 bit)
PLLSAI1REN : PLLSAI1 PLLADC1CLK output enable
bits : 24 - 24 (1 bit)
PLLSAI1R : PLLSAI1 division factor for PLLADC1CLK (ADC clock)
bits : 25 - 26 (2 bit)
PLLSAI1PDIV : PLLSAI1 division factor for PLLSAI1CLK
bits : 27 - 31 (5 bit)
PLLSAI2 configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLSAI2M : Division factor for PLLSAI2 input clock
bits : 4 - 7 (4 bit)
PLLSAI2N : SAI2PLL multiplication factor for VCO
bits : 8 - 14 (7 bit)
PLLSAI2PEN : SAI2PLL PLLSAI2CLK output enable
bits : 16 - 16 (1 bit)
PLLSAI2P : SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock)
bits : 17 - 17 (1 bit)
PLLSAI2QEN : PLLSAI2 division factor for PLLDISCLK
bits : 20 - 20 (1 bit)
PLLSAI2Q : SAI2PLL PLLSAI2CLK output enable
bits : 21 - 22 (2 bit)
PLLSAI2REN : PLLSAI2 PLLADC2CLK output enable
bits : 24 - 24 (1 bit)
PLLSAI2R : PLLSAI2 division factor for PLLADC2CLK (ADC clock)
bits : 25 - 26 (2 bit)
PLLSAI2PDIV : PLLSAI2 division factor for PLLSAI2CLK
bits : 27 - 31 (5 bit)
Clock interrupt enable register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYIE : LSI ready interrupt enable
bits : 0 - 0 (1 bit)
LSERDYIE : LSE ready interrupt enable
bits : 1 - 1 (1 bit)
MSIRDYIE : MSI ready interrupt enable
bits : 2 - 2 (1 bit)
HSIRDYIE : HSI ready interrupt enable
bits : 3 - 3 (1 bit)
HSERDYIE : HSE ready interrupt enable
bits : 4 - 4 (1 bit)
PLLRDYIE : PLL ready interrupt enable
bits : 5 - 5 (1 bit)
PLLSAI1RDYIE : PLLSAI1 ready interrupt enable
bits : 6 - 6 (1 bit)
PLLSAI2RDYIE : PLLSAI2 ready interrupt enable
bits : 7 - 7 (1 bit)
LSECSSIE : LSE clock security system interrupt enable
bits : 9 - 9 (1 bit)
HSI48RDYIE : HSI48 ready interrupt enable
bits : 10 - 10 (1 bit)
Clock interrupt flag register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LSIRDYF : LSI ready interrupt flag
bits : 0 - 0 (1 bit)
LSERDYF : LSE ready interrupt flag
bits : 1 - 1 (1 bit)
MSIRDYF : MSI ready interrupt flag
bits : 2 - 2 (1 bit)
HSIRDYF : HSI ready interrupt flag
bits : 3 - 3 (1 bit)
HSERDYF : HSE ready interrupt flag
bits : 4 - 4 (1 bit)
PLLRDYF : PLL ready interrupt flag
bits : 5 - 5 (1 bit)
PLLSAI1RDYF : PLLSAI1 ready interrupt flag
bits : 6 - 6 (1 bit)
PLLSAI2RDYF : PLLSAI2 ready interrupt flag
bits : 7 - 7 (1 bit)
CSSF : Clock security system interrupt flag
bits : 8 - 8 (1 bit)
LSECSSF : LSE Clock security system interrupt flag
bits : 9 - 9 (1 bit)
HSI48RDYF : HSI48 ready interrupt flag
bits : 10 - 10 (1 bit)
Clock interrupt clear register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LSIRDYC : LSI ready interrupt clear
bits : 0 - 0 (1 bit)
LSERDYC : LSE ready interrupt clear
bits : 1 - 1 (1 bit)
MSIRDYC : MSI ready interrupt clear
bits : 2 - 2 (1 bit)
HSIRDYC : HSI ready interrupt clear
bits : 3 - 3 (1 bit)
HSERDYC : HSE ready interrupt clear
bits : 4 - 4 (1 bit)
PLLRDYC : PLL ready interrupt clear
bits : 5 - 5 (1 bit)
PLLSAI1RDYC : PLLSAI1 ready interrupt clear
bits : 6 - 6 (1 bit)
PLLSAI2RDYC : PLLSAI2 ready interrupt clear
bits : 7 - 7 (1 bit)
CSSC : Clock security system interrupt clear
bits : 8 - 8 (1 bit)
LSECSSC : LSE Clock security system interrupt clear
bits : 9 - 9 (1 bit)
HSI48RDYC : HSI48 oscillator ready interrupt clear
bits : 10 - 10 (1 bit)
AHB1 peripheral reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1RST : DMA1 reset
bits : 0 - 0 (1 bit)
DMA2RST : DMA2 reset
bits : 1 - 1 (1 bit)
DMAMUX1RST : DMAMUXRST
bits : 2 - 2 (1 bit)
FLASHRST : Flash memory interface reset
bits : 8 - 8 (1 bit)
CRCRST : CRC reset
bits : 12 - 12 (1 bit)
TSCRST : Touch Sensing Controller reset
bits : 16 - 16 (1 bit)
DMA2DRST : DMA2D reset
bits : 17 - 17 (1 bit)
GFXMMURST : GFXMMU reset
bits : 18 - 18 (1 bit)
AHB2 peripheral reset register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOARST : IO port A reset
bits : 0 - 0 (1 bit)
GPIOBRST : IO port B reset
bits : 1 - 1 (1 bit)
GPIOCRST : IO port C reset
bits : 2 - 2 (1 bit)
GPIODRST : IO port D reset
bits : 3 - 3 (1 bit)
GPIOERST : IO port E reset
bits : 4 - 4 (1 bit)
GPIOFRST : IO port F reset
bits : 5 - 5 (1 bit)
GPIOGRST : IO port G reset
bits : 6 - 6 (1 bit)
GPIOHRST : IO port H reset
bits : 7 - 7 (1 bit)
GPIOIRST : IO port I reset
bits : 8 - 8 (1 bit)
OTGFSRST : USB OTG FS reset
bits : 12 - 12 (1 bit)
ADCRST : ADC reset
bits : 13 - 13 (1 bit)
DCMIRST : Digital Camera Interface reset
bits : 14 - 14 (1 bit)
AESRST : AES hardware accelerator reset
bits : 16 - 16 (1 bit)
HASHRST : Hash reset
bits : 17 - 17 (1 bit)
RNGRST : Random number generator reset
bits : 18 - 18 (1 bit)
OSPIMRST : OCTOSPI IO manager reset
bits : 20 - 20 (1 bit)
SDMMC1RST : SDMMC1 reset
bits : 22 - 22 (1 bit)
AHB3 peripheral reset register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMCRST : Flexible memory controller reset
bits : 0 - 0 (1 bit)
OSPI2RST : OctOSPI2 memory interface reset
bits : 9 - 9 (1 bit)
APB1 peripheral reset register 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2RST : TIM2 timer reset
bits : 0 - 0 (1 bit)
TIM3RST : TIM3 timer reset
bits : 1 - 1 (1 bit)
TIM4RST : TIM3 timer reset
bits : 2 - 2 (1 bit)
TIM5RST : TIM5 timer reset
bits : 3 - 3 (1 bit)
TIM6RST : TIM6 timer reset
bits : 4 - 4 (1 bit)
TIM7RST : TIM7 timer reset
bits : 5 - 5 (1 bit)
SPI2RST : SPI2 reset
bits : 14 - 14 (1 bit)
SPI3RST : SPI3 reset
bits : 15 - 15 (1 bit)
USART2RST : USART2 reset
bits : 17 - 17 (1 bit)
USART3RST : USART3 reset
bits : 18 - 18 (1 bit)
UART4RST : UART4 reset
bits : 19 - 19 (1 bit)
UART5RST : UART5 reset
bits : 20 - 20 (1 bit)
I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)
I2C2RST : I2C2 reset
bits : 22 - 22 (1 bit)
I2C3RST : I2C3 reset
bits : 23 - 23 (1 bit)
CRSRST : CRS reset
bits : 24 - 24 (1 bit)
CAN1RST : CAN1 reset
bits : 25 - 25 (1 bit)
PWRRST : Power interface reset
bits : 28 - 28 (1 bit)
DAC1RST : DAC1 interface reset
bits : 29 - 29 (1 bit)
OPAMPRST : OPAMP interface reset
bits : 30 - 30 (1 bit)
LPTIM1RST : Low Power Timer 1 reset
bits : 31 - 31 (1 bit)
APB1 peripheral reset register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPUART1RST : Low-power UART 1 reset
bits : 0 - 0 (1 bit)
I2C4RST : I2C4 reset
bits : 1 - 1 (1 bit)
LPTIM2RST : Low-power timer 2 reset
bits : 5 - 5 (1 bit)
Internal clock sources calibration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSICAL : MSI clock calibration
bits : 0 - 7 (8 bit)
access : read-only
MSITRIM : MSI clock trimming
bits : 8 - 15 (8 bit)
access : read-write
HSICAL : HSI clock calibration
bits : 16 - 23 (8 bit)
access : read-only
HSITRIM : HSI clock trimming
bits : 24 - 30 (7 bit)
access : read-write
APB2 peripheral reset register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGRST : System configuration (SYSCFG) reset
bits : 0 - 0 (1 bit)
TIM1RST : TIM1 timer reset
bits : 11 - 11 (1 bit)
SPI1RST : SPI1 reset
bits : 12 - 12 (1 bit)
TIM8RST : TIM8 timer reset
bits : 13 - 13 (1 bit)
USART1RST : USART1 reset
bits : 14 - 14 (1 bit)
TIM15RST : TIM15 timer reset
bits : 16 - 16 (1 bit)
TIM16RST : TIM16 timer reset
bits : 17 - 17 (1 bit)
TIM17RST : TIM17 timer reset
bits : 18 - 18 (1 bit)
SAI1RST : Serial audio interface 1 (SAI1) reset
bits : 21 - 21 (1 bit)
SAI2RST : Serial audio interface 2 (SAI2) reset
bits : 22 - 22 (1 bit)
DFSDM1RST : Digital filters for sigma-delata modulators (DFSDM) reset
bits : 24 - 24 (1 bit)
LTDCRST : LCD-TFT reset
bits : 26 - 26 (1 bit)
DSIRST : DSI reset
bits : 27 - 27 (1 bit)
AHB1 peripheral clock enable register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1EN : DMA1 clock enable
bits : 0 - 0 (1 bit)
DMA2EN : DMA2 clock enable
bits : 1 - 1 (1 bit)
DMAMUX1EN : DMAMUX clock enable
bits : 2 - 2 (1 bit)
FLASHEN : Flash memory interface clock enable
bits : 8 - 8 (1 bit)
CRCEN : CRC clock enable
bits : 12 - 12 (1 bit)
TSCEN : Touch Sensing Controller clock enable
bits : 16 - 16 (1 bit)
DMA2DEN : DMA2D clock enable
bits : 17 - 17 (1 bit)
GFXMMUEN : Graphic MMU clock enable
bits : 18 - 18 (1 bit)
AHB2 peripheral clock enable register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOAEN : IO port A clock enable
bits : 0 - 0 (1 bit)
GPIOBEN : IO port B clock enable
bits : 1 - 1 (1 bit)
GPIOCEN : IO port C clock enable
bits : 2 - 2 (1 bit)
GPIODEN : IO port D clock enable
bits : 3 - 3 (1 bit)
GPIOEEN : IO port E clock enable
bits : 4 - 4 (1 bit)
GPIOFEN : IO port F clock enable
bits : 5 - 5 (1 bit)
GPIOGEN : IO port G clock enable
bits : 6 - 6 (1 bit)
GPIOHEN : IO port H clock enable
bits : 7 - 7 (1 bit)
GPIOIEN : IO port I clock enable
bits : 8 - 8 (1 bit)
OTGFSEN : OTG full speed clock enable
bits : 12 - 12 (1 bit)
ADCEN : ADC clock enable
bits : 13 - 13 (1 bit)
DCMIEN : DCMI clock enable
bits : 14 - 14 (1 bit)
AESEN : AES accelerator clock enable
bits : 16 - 16 (1 bit)
HASHEN : HASH clock enable
bits : 17 - 17 (1 bit)
RNGEN : Random Number Generator clock enable
bits : 18 - 18 (1 bit)
OSPIMEN : OctoSPI IO manager clock enable
bits : 20 - 20 (1 bit)
SDMMC1EN : SDMMC1 clock enable
bits : 22 - 22 (1 bit)
AHB3 peripheral clock enable register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMCEN : Flexible memory controller clock enable
bits : 0 - 0 (1 bit)
OSPI2EN : OSPI2EN memory interface clock enable
bits : 9 - 9 (1 bit)
APB1ENR1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2EN : TIM2 timer clock enable
bits : 0 - 0 (1 bit)
TIM3EN : TIM3 timer clock enable
bits : 1 - 1 (1 bit)
TIM4EN : TIM4 timer clock enable
bits : 2 - 2 (1 bit)
TIM5EN : TIM5 timer clock enable
bits : 3 - 3 (1 bit)
TIM6EN : TIM6 timer clock enable
bits : 4 - 4 (1 bit)
TIM7EN : TIM7 timer clock enable
bits : 5 - 5 (1 bit)
RTCAPBEN : RTC APB clock enable
bits : 10 - 10 (1 bit)
WWDGEN : Window watchdog clock enable
bits : 11 - 11 (1 bit)
SPI2EN : SPI2 clock enable
bits : 14 - 14 (1 bit)
SP3EN : SPI3 clock enable
bits : 15 - 15 (1 bit)
USART2EN : USART2 clock enable
bits : 17 - 17 (1 bit)
USART3EN : USART3 clock enable
bits : 18 - 18 (1 bit)
UART4EN : UART4 clock enable
bits : 19 - 19 (1 bit)
UART5EN : UART5 clock enable
bits : 20 - 20 (1 bit)
I2C1EN : I2C1 clock enable
bits : 21 - 21 (1 bit)
I2C2EN : I2C2 clock enable
bits : 22 - 22 (1 bit)
I2C3EN : I2C3 clock enable
bits : 23 - 23 (1 bit)
CRSEN : Clock Recovery System clock enable
bits : 24 - 24 (1 bit)
CAN1EN : CAN1 clock enable
bits : 25 - 25 (1 bit)
PWREN : Power interface clock enable
bits : 28 - 28 (1 bit)
DAC1EN : DAC1 interface clock enable
bits : 29 - 29 (1 bit)
OPAMPEN : OPAMP interface clock enable
bits : 30 - 30 (1 bit)
LPTIM1EN : Low power timer 1 clock enable
bits : 31 - 31 (1 bit)
APB1 peripheral clock enable register 2
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPUART1EN : Low power UART 1 clock enable
bits : 0 - 0 (1 bit)
I2C4EN : I2C4 clock enable
bits : 1 - 1 (1 bit)
LPTIM2EN : LPTIM2EN
bits : 5 - 5 (1 bit)
APB2ENR
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGEN : SYSCFG clock enable
bits : 0 - 0 (1 bit)
FWEN : Firewall clock enable
bits : 7 - 7 (1 bit)
TIM1EN : TIM1 timer clock enable
bits : 11 - 11 (1 bit)
SPI1EN : SPI1 clock enable
bits : 12 - 12 (1 bit)
TIM8EN : TIM8 timer clock enable
bits : 13 - 13 (1 bit)
USART1EN : USART1clock enable
bits : 14 - 14 (1 bit)
TIM15EN : TIM15 timer clock enable
bits : 16 - 16 (1 bit)
TIM16EN : TIM16 timer clock enable
bits : 17 - 17 (1 bit)
TIM17EN : TIM17 timer clock enable
bits : 18 - 18 (1 bit)
SAI1EN : SAI1 clock enable
bits : 21 - 21 (1 bit)
SAI2EN : SAI2 clock enable
bits : 22 - 22 (1 bit)
DFSDM1EN : DFSDM timer clock enable
bits : 24 - 24 (1 bit)
LTDCEN : LCD-TFT clock enable
bits : 26 - 26 (1 bit)
DSIEN : DSI clock enable
bits : 27 - 27 (1 bit)
AHB1 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1SMEN : DMA1 clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)
DMA2SMEN : DMA2 clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)
DMAMUX1SMEN : DMAMUX clock enable during Sleep and Stop modes
bits : 2 - 2 (1 bit)
FLASHSMEN : Flash memory interface clocks enable during Sleep and Stop modes
bits : 8 - 8 (1 bit)
SRAM1SMEN : SRAM1 interface clocks enable during Sleep and Stop modes
bits : 9 - 9 (1 bit)
CRCSMEN : CRCSMEN
bits : 12 - 12 (1 bit)
TSCSMEN : Touch Sensing Controller clocks enable during Sleep and Stop modes
bits : 16 - 16 (1 bit)
DMA2DSMEN : DMA2D clock enable during Sleep and Stop modes
bits : 17 - 17 (1 bit)
GFXMMUSMEN : GFXMMU clock enable during Sleep and Stop modes
bits : 18 - 18 (1 bit)
AHB2 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOASMEN : IO port A clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)
GPIOBSMEN : IO port B clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)
GPIOCSMEN : IO port C clocks enable during Sleep and Stop modes
bits : 2 - 2 (1 bit)
GPIODSMEN : IO port D clocks enable during Sleep and Stop modes
bits : 3 - 3 (1 bit)
GPIOESMEN : IO port E clocks enable during Sleep and Stop modes
bits : 4 - 4 (1 bit)
GPIOFSMEN : IO port F clocks enable during Sleep and Stop modes
bits : 5 - 5 (1 bit)
GPIOGSMEN : IO port G clocks enable during Sleep and Stop modes
bits : 6 - 6 (1 bit)
GPIOHSMEN : IO port H clocks enable during Sleep and Stop modes
bits : 7 - 7 (1 bit)
GPIOISMEN : IO port I clocks enable during Sleep and Stop modes
bits : 8 - 8 (1 bit)
SRAM2SMEN : SRAM2 interface clocks enable during Sleep and Stop modes
bits : 9 - 9 (1 bit)
SRAM3SMEN : SRAM2 interface clocks enable during Sleep and Stop modes
bits : 10 - 10 (1 bit)
OTGFSSMEN : OTG full speed clocks enable during Sleep and Stop modes
bits : 12 - 12 (1 bit)
ADCFSSMEN : ADC clocks enable during Sleep and Stop modes
bits : 13 - 13 (1 bit)
DCMISMEN : DCMI clock enable during Sleep and Stop modes
bits : 14 - 14 (1 bit)
AESSMEN : AES accelerator clocks enable during Sleep and Stop modes
bits : 16 - 16 (1 bit)
HASHSMEN : HASH clock enable during Sleep and Stop modes
bits : 17 - 17 (1 bit)
RNGSMEN : Random Number Generator clocks enable during Sleep and Stop modes
bits : 18 - 18 (1 bit)
OSPIMSMEN : OctoSPI IO manager clocks enable during Sleep and Stop modes
bits : 20 - 20 (1 bit)
SDMMC1SMEN : SDMMC1 clocks enable during Sleep and Stop modes
bits : 22 - 22 (1 bit)
AHB3 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMCSMEN : Flexible memory controller clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)
OCTOSPI2 : OctoSPI2 memory interface clocks enable during Sleep and Stop modes
bits : 9 - 9 (1 bit)
APB1SMENR1
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2SMEN : TIM2 timer clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)
TIM3SMEN : TIM3 timer clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)
TIM4SMEN : TIM4 timer clocks enable during Sleep and Stop modes
bits : 2 - 2 (1 bit)
TIM5SMEN : TIM5 timer clocks enable during Sleep and Stop modes
bits : 3 - 3 (1 bit)
TIM6SMEN : TIM6 timer clocks enable during Sleep and Stop modes
bits : 4 - 4 (1 bit)
TIM7SMEN : TIM7 timer clocks enable during Sleep and Stop modes
bits : 5 - 5 (1 bit)
RTCAPBSMEN : RTC APB clock enable during Sleep and Stop modes
bits : 10 - 10 (1 bit)
WWDGSMEN : Window watchdog clocks enable during Sleep and Stop modes
bits : 11 - 11 (1 bit)
SPI2SMEN : SPI2 clocks enable during Sleep and Stop modes
bits : 14 - 14 (1 bit)
SP3SMEN : SPI3 clocks enable during Sleep and Stop modes
bits : 15 - 15 (1 bit)
USART2SMEN : USART2 clocks enable during Sleep and Stop modes
bits : 17 - 17 (1 bit)
USART3SMEN : USART3 clocks enable during Sleep and Stop modes
bits : 18 - 18 (1 bit)
UART4SMEN : UART4 clocks enable during Sleep and Stop modes
bits : 19 - 19 (1 bit)
UART5SMEN : UART5 clocks enable during Sleep and Stop modes
bits : 20 - 20 (1 bit)
I2C1SMEN : I2C1 clocks enable during Sleep and Stop modes
bits : 21 - 21 (1 bit)
I2C2SMEN : I2C2 clocks enable during Sleep and Stop modes
bits : 22 - 22 (1 bit)
I2C3SMEN : I2C3 clocks enable during Sleep and Stop modes
bits : 23 - 23 (1 bit)
CRSSMEN : CRS clock enable during Sleep and Stop modes
bits : 24 - 24 (1 bit)
CAN1SMEN : CAN1 clocks enable during Sleep and Stop modes
bits : 25 - 25 (1 bit)
PWRSMEN : Power interface clocks enable during Sleep and Stop modes
bits : 28 - 28 (1 bit)
DAC1SMEN : DAC1 interface clocks enable during Sleep and Stop modes
bits : 29 - 29 (1 bit)
OPAMPSMEN : OPAMP interface clocks enable during Sleep and Stop modes
bits : 30 - 30 (1 bit)
LPTIM1SMEN : Low power timer 1 clocks enable during Sleep and Stop modes
bits : 31 - 31 (1 bit)
APB1 peripheral clocks enable in Sleep and Stop modes register 2
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPUART1SMEN : Low power UART 1 clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)
I2C4SMEN : I2C4 clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)
LPTIM2SMEN : LPTIM2SMEN
bits : 5 - 5 (1 bit)
Clock configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW : System clock switch
bits : 0 - 1 (2 bit)
access : read-write
SWS : System clock switch status
bits : 2 - 3 (2 bit)
access : read-only
HPRE : AHB prescaler
bits : 4 - 7 (4 bit)
access : read-write
PPRE1 : PB low-speed prescaler (APB1)
bits : 8 - 10 (3 bit)
access : read-write
PPRE2 : APB high-speed prescaler (APB2)
bits : 11 - 13 (3 bit)
access : read-write
STOPWUCK : Wakeup from Stop and CSS backup clock selection
bits : 15 - 15 (1 bit)
access : read-write
MCOSEL : Microcontroller clock output
bits : 24 - 26 (3 bit)
access : read-write
MCOPRE : Microcontroller clock output prescaler
bits : 28 - 30 (3 bit)
access : read-only
APB2SMENR
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGSMEN : SYSCFG clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)
TIM1SMEN : TIM1 timer clocks enable during Sleep and Stop modes
bits : 11 - 11 (1 bit)
SPI1SMEN : SPI1 clocks enable during Sleep and Stop modes
bits : 12 - 12 (1 bit)
TIM8SMEN : TIM8 timer clocks enable during Sleep and Stop modes
bits : 13 - 13 (1 bit)
USART1SMEN : USART1clocks enable during Sleep and Stop modes
bits : 14 - 14 (1 bit)
TIM15SMEN : TIM15 timer clocks enable during Sleep and Stop modes
bits : 16 - 16 (1 bit)
TIM16SMEN : TIM16 timer clocks enable during Sleep and Stop modes
bits : 17 - 17 (1 bit)
TIM17SMEN : TIM17 timer clocks enable during Sleep and Stop modes
bits : 18 - 18 (1 bit)
SAI1SMEN : SAI1 clocks enable during Sleep and Stop modes
bits : 21 - 21 (1 bit)
SAI2SMEN : SAI2 clocks enable during Sleep and Stop modes
bits : 22 - 22 (1 bit)
DFSDM1SMEN : DFSDM timer clocks enable during Sleep and Stop modes
bits : 24 - 24 (1 bit)
LTDCSMEN : LCD-TFT timer clocks enable during Sleep and Stop modes
bits : 26 - 26 (1 bit)
DSISMEN : DSI clocks enable during Sleep and Stop modes
bits : 27 - 27 (1 bit)
CCIPR
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USART1SEL : USART1 clock source selection
bits : 0 - 1 (2 bit)
USART2SEL : USART2 clock source selection
bits : 2 - 3 (2 bit)
USART3SEL : USART3 clock source selection
bits : 4 - 5 (2 bit)
UART4SEL : UART4 clock source selection
bits : 6 - 7 (2 bit)
UART5SEL : UART5 clock source selection
bits : 8 - 9 (2 bit)
LPUART1SEL : LPUART1 clock source selection
bits : 10 - 11 (2 bit)
I2C1SEL : I2C1 clock source selection
bits : 12 - 13 (2 bit)
I2C2SEL : I2C2 clock source selection
bits : 14 - 15 (2 bit)
I2C3SEL : I2C3 clock source selection
bits : 16 - 17 (2 bit)
LPTIM1SEL : Low power timer 1 clock source selection
bits : 18 - 19 (2 bit)
LPTIM2SEL : Low power timer 2 clock source selection
bits : 20 - 21 (2 bit)
SAI1SEL : SAI1 clock source selection
bits : 22 - 23 (2 bit)
SAI2SEL : SAI2 clock source selection
bits : 24 - 25 (2 bit)
CLK48SEL : 48 MHz clock source selection
bits : 26 - 27 (2 bit)
ADCSEL : ADCs clock source selection
bits : 28 - 29 (2 bit)
BDCR
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSEON : LSE oscillator enable
bits : 0 - 0 (1 bit)
access : read-write
LSERDY : LSE oscillator ready
bits : 1 - 1 (1 bit)
access : read-only
LSEBYP : LSE oscillator bypass
bits : 2 - 2 (1 bit)
access : read-write
LSEDRV : SE oscillator drive capability
bits : 3 - 4 (2 bit)
access : read-write
LSECSSON : LSECSSON
bits : 5 - 5 (1 bit)
access : read-write
LSECSSD : LSECSSD
bits : 6 - 6 (1 bit)
access : read-only
RTCSEL : RTC clock source selection
bits : 8 - 9 (2 bit)
access : read-write
RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write
BDRST : Backup domain software reset
bits : 16 - 16 (1 bit)
access : read-write
LSCOEN : Low speed clock output enable
bits : 24 - 24 (1 bit)
access : read-write
LSCOSEL : Low speed clock output selection
bits : 25 - 25 (1 bit)
access : read-write
CSR
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSION : LSI oscillator enable
bits : 0 - 0 (1 bit)
access : read-write
LSIRDY : LSI oscillator ready
bits : 1 - 1 (1 bit)
access : read-only
MSISRANGE : SI range after Standby mode
bits : 8 - 11 (4 bit)
access : read-write
RMVF : Remove reset flag
bits : 23 - 23 (1 bit)
access : read-write
FWRSTF : Firewall reset flag
bits : 24 - 24 (1 bit)
access : read-only
OBLRSTF : Option byte loader reset flag
bits : 25 - 25 (1 bit)
access : read-only
PINRSTF : Pin reset flag
bits : 26 - 26 (1 bit)
access : read-only
BORRSTF : BOR flag
bits : 27 - 27 (1 bit)
access : read-only
SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-only
IWDGRSTF : Independent window watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-only
WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-only
LPWRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-only
Clock recovery RC register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSI48ON : HSI48 clock enable
bits : 0 - 0 (1 bit)
access : read-write
HSI48RDY : HSI48 clock ready flag
bits : 1 - 1 (1 bit)
access : read-only
HSI48CAL : HSI48 clock calibration
bits : 7 - 15 (9 bit)
access : read-only
Peripherals independent clock configuration register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C4SEL : I2C4 clock source selection
bits : 0 - 1 (2 bit)
DFSDMSEL : Digital filter for sigma delta modulator kernel clock source selection
bits : 2 - 2 (1 bit)
ADFSDMSEL : Digital filter for sigma delta modulator audio clock source selection
bits : 3 - 4 (2 bit)
SAI1SEL : SAI1 clock source selection
bits : 5 - 7 (3 bit)
SAI2SEL : SAI2 clock source selection
bits : 8 - 10 (3 bit)
DSISEL : clock selection
bits : 12 - 12 (1 bit)
SDMMCSEL : SDMMC clock selection
bits : 14 - 14 (1 bit)
PLLSAI2DIVR : division factor for LTDC clock
bits : 16 - 17 (2 bit)
OSPISEL : Octospi clock source selection
bits : 20 - 21 (2 bit)
PLL configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLSRC : Main PLL, PLLSAI1 and PLLSAI2 entry clock source
bits : 0 - 1 (2 bit)
PLLM : Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
bits : 4 - 7 (4 bit)
PLLN : Main PLL multiplication factor for VCO
bits : 8 - 14 (7 bit)
PLLPEN : Main PLL PLLSAI3CLK output enable
bits : 16 - 16 (1 bit)
PLLP : Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
bits : 17 - 17 (1 bit)
PLLQEN : Main PLL PLLUSB1CLK output enable
bits : 20 - 20 (1 bit)
PLLQ : Main PLL division factor for PLLUSB1CLK(48 MHz clock)
bits : 21 - 22 (2 bit)
PLLREN : Main PLL PLLCLK output enable
bits : 24 - 24 (1 bit)
PLLR : Main PLL division factor for PLLCLK (system clock)
bits : 25 - 26 (2 bit)
PLLPDIV : Main PLL division factor for PLLSAI2CLK
bits : 27 - 31 (5 bit)
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