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SWPMI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

ICR

IER

RFL

TDR

RDR

BRR

ISR


CR

SWPMI Configuration/Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDMA TXDMA RXMODE TXMODE LPBK SWPME DEACT

RXDMA : Reception DMA enable
bits : 0 - 0 (1 bit)

TXDMA : Transmission DMA enable
bits : 1 - 1 (1 bit)

RXMODE : Reception buffering mode
bits : 2 - 2 (1 bit)

TXMODE : Transmission buffering mode
bits : 3 - 3 (1 bit)

LPBK : Loopback mode enable
bits : 4 - 4 (1 bit)

SWPME : Single wire protocol master interface enable
bits : 5 - 5 (1 bit)

DEACT : Single wire protocol master interface deactivate
bits : 10 - 10 (1 bit)


ICR

SWPMI Interrupt Flag Clear register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRXBFF CTXBEF CRXBERF CRXOVRF CTXUNRF CTCF CSRF

CRXBFF : Clear receive buffer full flag
bits : 0 - 0 (1 bit)

CTXBEF : Clear transmit buffer empty flag
bits : 1 - 1 (1 bit)

CRXBERF : Clear receive CRC error flag
bits : 2 - 2 (1 bit)

CRXOVRF : Clear receive overrun error flag
bits : 3 - 3 (1 bit)

CTXUNRF : Clear transmit underrun error flag
bits : 4 - 4 (1 bit)

CTCF : Clear transfer complete flag
bits : 7 - 7 (1 bit)

CSRF : Clear slave resume flag
bits : 8 - 8 (1 bit)


IER

SWPMI Interrupt Enable register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXBFIE TXBEIE RXBERIE RXOVRIE TXUNRIE RIE TIE TCIE SRIE

RXBFIE : Receive buffer full interrupt enable
bits : 0 - 0 (1 bit)

TXBEIE : Transmit buffer empty interrupt enable
bits : 1 - 1 (1 bit)

RXBERIE : Receive CRC error interrupt enable
bits : 2 - 2 (1 bit)

RXOVRIE : Receive overrun error interrupt enable
bits : 3 - 3 (1 bit)

TXUNRIE : Transmit underrun error interrupt enable
bits : 4 - 4 (1 bit)

RIE : Receive interrupt enable
bits : 5 - 5 (1 bit)

TIE : Transmit interrupt enable
bits : 6 - 6 (1 bit)

TCIE : Transmit complete interrupt enable
bits : 7 - 7 (1 bit)

SRIE : Slave resume interrupt enable
bits : 8 - 8 (1 bit)


RFL

SWPMI Receive Frame Length register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RFL RFL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFL

RFL : Receive frame length
bits : 0 - 4 (5 bit)


TDR

SWPMI Transmit data register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TDR TDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TD

TD : Transmit data
bits : 0 - 31 (32 bit)


RDR

SWPMI Receive data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDR RDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD

RD : received data
bits : 0 - 31 (32 bit)


BRR

SWPMI Bitrate register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRR BRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BR

BR : Bitrate prescaler
bits : 0 - 5 (6 bit)


ISR

SWPMI Interrupt and Status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXBFF TXBEF RXBERF RXOVRF TXUNRF RXNE TXE TCF SRF SUSP DEACTF

RXBFF : Receive buffer full flag
bits : 0 - 0 (1 bit)

TXBEF : Transmit buffer empty flag
bits : 1 - 1 (1 bit)

RXBERF : Receive CRC error flag
bits : 2 - 2 (1 bit)

RXOVRF : Receive overrun error flag
bits : 3 - 3 (1 bit)

TXUNRF : Transmit underrun error flag
bits : 4 - 4 (1 bit)

RXNE : Receive data register not empty
bits : 5 - 5 (1 bit)

TXE : Transmit data register empty
bits : 6 - 6 (1 bit)

TCF : Transfer complete flag
bits : 7 - 7 (1 bit)

SRF : Slave resume flag
bits : 8 - 8 (1 bit)

SUSP : SUSPEND flag
bits : 9 - 9 (1 bit)

DEACTF : DEACTIVATED flag
bits : 10 - 10 (1 bit)



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