\n

FMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WS

CTL

PID

ADDR

OBSTAT

WP

KEY

OBKEY

STAT


WS

wait state register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WS WS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WSCNT PFEN ICEN DCEN ICRST DCRST PGW

WSCNT : wait state counter register
bits : 0 - 2 (3 bit)

PFEN : Pre-fetch enable
bits : 4 - 4 (1 bit)

ICEN : IBUS cache enable
bits : 9 - 9 (1 bit)

DCEN : DBUS cache enable
bits : 10 - 10 (1 bit)

ICRST : IBUS cache reset
bits : 11 - 11 (1 bit)

DCRST : DBUS cache reset
bits : 12 - 12 (1 bit)

PGW : Program width to flash memory
bits : 15 - 15 (1 bit)


CTL

Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG PER MER OBPG OBER START LK OBWEN ERRIE ENDIE

PG : Main flash program for bank0 command bit
bits : 0 - 0 (1 bit)

PER : Main flash page erase for bank0 command bit
bits : 1 - 1 (1 bit)

MER : Main flash mass erase for bank0 command bit
bits : 2 - 2 (1 bit)

OBPG : Option bytes program command bit
bits : 4 - 4 (1 bit)

OBER : Option bytes erase command bit
bits : 5 - 5 (1 bit)

START : Send erase command to FMC bit
bits : 6 - 6 (1 bit)

LK : FMC_CTL lock bit
bits : 7 - 7 (1 bit)

OBWEN : Option byte erase/program enable bit
bits : 9 - 9 (1 bit)

ERRIE : Error interrupt enable bit
bits : 10 - 10 (1 bit)

ENDIE : End of operation interrupt enable bit
bits : 12 - 12 (1 bit)


PID

Product ID register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID PID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Product reserved ID code register
bits : 0 - 31 (32 bit)


ADDR

Address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADDR ADDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Flash erase/program command address bits
bits : 0 - 31 (32 bit)


OBSTAT

Option byte control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OBSTAT OBSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OBERR SPC USER DATA

OBERR : Option bytes read error bit
bits : 0 - 0 (1 bit)

SPC : Option bytes security protection code
bits : 1 - 1 (1 bit)

USER : Store USER of option bytes block after system reset
bits : 2 - 9 (8 bit)

DATA : Store DATA[15:0] of option bytes block after system reset
bits : 10 - 25 (16 bit)


WP

Erase/Program Protection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WP WP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WP

WP : Store WP[31:0] of option bytes block after system reset
bits : 0 - 31 (32 bit)


KEY

Unlock key register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY KEY write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : FMC_CTL unlock register
bits : 0 - 31 (32 bit)


OBKEY

Option byte unlock key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OBKEY OBKEY write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OBKEY

OBKEY : FMC_ CTL option bytes operation unlock register
bits : 0 - 31 (32 bit)


STAT

Status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY PGERR PGAERR WPERR ENDF

BUSY : The flash is busy bit
bits : 0 - 0 (1 bit)
access : read-only

PGERR : Program error flag bit
bits : 2 - 2 (1 bit)
access : read-write

PGAERR : Program alignment error flag bit
bits : 3 - 3 (1 bit)
access : read-write

WPERR : Erase/Program protection error flag bit
bits : 4 - 4 (1 bit)
access : read-write

ENDF : End of operation flag bit
bits : 5 - 5 (1 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.