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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ADC_LST0 (LST0)

ADC_TCR (TCR)

ADC_TSR (TSR)

ADC_HTCR (HTCR)

ADC_HTSR (HTSR)

ADC_WCR (WCR)

ADC_LTR (LTR)

ADC_UTR (UTR)

ADC_IMR (IMR)

ADC_IRAW (IRAW)

ADC_IMASK (IMASK)

ADC_ICLR (ICLR)

ADC_LST1 (LST1)

ADC_DMAR (DMAR)

ADC_LST2 (LST2)

ADC_LST3 (LST3)

ADC_HLST (HLST)

ADC_OFR0 (OFR0)

ADC_OFR1 (OFR1)

ADC_OFR2 (OFR2)

ADC_OFR3 (OFR3)

ADC_RST (RST)

ADC_OFR4 (OFR4)

ADC_OFR5 (OFR5)

ADC_OFR6 (OFR6)

ADC_OFR7 (OFR7)

ADC_OFR8 (OFR8)

ADC_OFR9 (OFR9)

ADC_OFR10 (OFR10)

ADC_OFR11 (OFR11)

ADC_OFR12 (OFR12)

ADC_OFR13 (OFR13)

ADC_OFR14 (OFR14)

ADC_OFR15 (OFR15)

ADC_STR0 (STR0)

ADC_STR1 (STR1)

ADC_STR2 (STR2)

ADC_STR3 (STR3)

ADC_CONV (CONV)

ADC_STR4 (STR4)

ADC_STR5 (STR5)

ADC_STR6 (STR6)

ADC_STR7 (STR7)

ADC_STR8 (STR8)

ADC_STR9 (STR9)

ADC_STR10 (STR10)

ADC_STR11 (STR11)

ADC_STR12 (STR12)

ADC_STR13 (STR13)

ADC_STR14 (STR14)

ADC_STR15 (STR15)

ADC_DR0 (DR0)

ADC_DR1 (DR1)

ADC_DR2 (DR2)

ADC_DR3 (DR3)

ADC_HCONV (HCONV)

ADC_DR4 (DR4)

ADC_DR5 (DR5)

ADC_DR6 (DR6)

ADC_DR7 (DR7)

ADC_DR8 (DR8)

ADC_DR9 (DR9)

ADC_DR10 (DR10)

ADC_DR11 (DR11)

ADC_DR12 (DR12)

ADC_DR13 (DR13)

ADC_DR14 (DR14)

ADC_DR15 (DR15)

ADC_HDR0 (HDR0)

ADC_HDR1 (HDR1)

ADC_HDR2 (HDR2)

ADC_HDR3 (HDR3)


ADC_LST0 (LST0)

ADC_LST0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_LST0 ADC_LST0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSEQ0 ADSEQ1 ADSEQ2 ADSEQ3

ADSEQ0 : ADSEQ0
bits : 0 - 4 (5 bit)
access : read-write

ADSEQ1 : ADSEQ1
bits : 8 - 20 (13 bit)
access : read-write

ADSEQ2 : ADSEQ2
bits : 16 - 36 (21 bit)
access : read-write

ADSEQ3 : ADSEQ3
bits : 24 - 52 (29 bit)
access : read-write


ADC_TCR (TCR)

ADC_TCR
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_TCR ADC_TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSW ADEXTI TM BFTM CMP

ADSW : ADSW
bits : 0 - 0 (1 bit)
access : read-write

ADEXTI : ADEXTI
bits : 1 - 2 (2 bit)
access : read-write

TM : TM
bits : 2 - 4 (3 bit)
access : read-write

BFTM : BFTM
bits : 3 - 6 (4 bit)
access : read-write

CMP : CMP
bits : 4 - 8 (5 bit)
access : read-write


ADC_TSR (TSR)

ADC_TSR
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_TSR ADC_TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSC ADEXTIS TMS BFTMS CMPS TME

ADSC : ADSC
bits : 0 - 0 (1 bit)
access : read-write

ADEXTIS : ADEXTIS
bits : 8 - 19 (12 bit)
access : read-write

TMS : TMS
bits : 16 - 34 (19 bit)
access : read-write

BFTMS : BFTMS
bits : 19 - 38 (20 bit)
access : read-write

CMPS : CMPS
bits : 20 - 40 (21 bit)
access : read-write

TME : TME
bits : 24 - 50 (27 bit)
access : read-write


ADC_HTCR (HTCR)

ADC_HTCR
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_HTCR ADC_HTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADHSW ADHEXTI HTM HBFTM

ADHSW : ADHSW
bits : 0 - 0 (1 bit)
access : read-write

ADHEXTI : ADHEXTI
bits : 1 - 2 (2 bit)
access : read-write

HTM : HTM
bits : 2 - 4 (3 bit)
access : read-write

HBFTM : HBFTM
bits : 3 - 6 (4 bit)
access : read-write


ADC_HTSR (HTSR)

ADC_HTSR
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_HTSR ADC_HTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADHSC ADHEXTIS HTMS HBFTMS HTME

ADHSC : ADHSC
bits : 0 - 0 (1 bit)
access : read-write

ADHEXTIS : ADHEXTIS
bits : 8 - 19 (12 bit)
access : read-write

HTMS : HTMS
bits : 16 - 34 (19 bit)
access : read-write

HBFTMS : HBFTMS
bits : 19 - 38 (20 bit)
access : read-write

HTME : HTME
bits : 24 - 50 (27 bit)
access : read-write


ADC_WCR (WCR)

ADC_WCR
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_WCR ADC_WCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADWLE ADWUE ADWALL ADWCH ADLCH ADUCH

ADWLE : ADWLE
bits : 0 - 0 (1 bit)
access : read-write

ADWUE : ADWUE
bits : 1 - 2 (2 bit)
access : read-write

ADWALL : ADWALL
bits : 2 - 4 (3 bit)
access : read-write

ADWCH : ADWCH
bits : 8 - 19 (12 bit)
access : read-write

ADLCH : ADLCH
bits : 16 - 35 (20 bit)
access : read-write

ADUCH : ADUCH
bits : 24 - 51 (28 bit)
access : read-write


ADC_LTR (LTR)

ADC_LTR
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_LTR ADC_LTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADLT

ADLT : ADLT
bits : 0 - 11 (12 bit)
access : read-write


ADC_UTR (UTR)

ADC_UTR
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_UTR ADC_UTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADUT

ADUT : ADUT
bits : 0 - 11 (12 bit)
access : read-write


ADC_IMR (IMR)

ADC_IMR
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_IMR ADC_IMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADIMS ADIMG ADIMC ADIMHS ADIMHG ADIMHC ADIML ADIMU ADIMO ADIMHO

ADIMS : ADIMS
bits : 0 - 0 (1 bit)
access : read-write

ADIMG : ADIMG
bits : 1 - 2 (2 bit)
access : read-write

ADIMC : ADIMC
bits : 2 - 4 (3 bit)
access : read-write

ADIMHS : ADIMHS
bits : 8 - 16 (9 bit)
access : read-write

ADIMHG : ADIMHG
bits : 9 - 18 (10 bit)
access : read-write

ADIMHC : ADIMC
bits : 10 - 20 (11 bit)
access : read-write

ADIML : ADIML
bits : 16 - 32 (17 bit)
access : read-write

ADIMU : ADIMU
bits : 17 - 34 (18 bit)
access : read-write

ADIMO : ADIMO
bits : 24 - 48 (25 bit)
access : read-write

ADIMHO : ADIMHO
bits : 25 - 50 (26 bit)
access : read-write


ADC_IRAW (IRAW)

ADC_IRAW
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_IRAW ADC_IRAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADIRAWS ADIRAWG ADIRAWC ADIRAWHS ADIRAWHG ADIRAWHC ADIRAWL ADIRAWU ADIRAWO ADIRAWHO

ADIRAWS : ADIRAWS
bits : 0 - 0 (1 bit)
access : read-write

ADIRAWG : ADIRAWG
bits : 1 - 2 (2 bit)
access : read-write

ADIRAWC : ADIRAWC
bits : 2 - 4 (3 bit)
access : read-write

ADIRAWHS : ADIRAWHS
bits : 8 - 16 (9 bit)
access : read-write

ADIRAWHG : ADIRAWHG
bits : 9 - 18 (10 bit)
access : read-write

ADIRAWHC : ADIRAWHC
bits : 10 - 20 (11 bit)
access : read-write

ADIRAWL : ADIRAWL
bits : 16 - 32 (17 bit)
access : read-write

ADIRAWU : ADIRAWU
bits : 17 - 34 (18 bit)
access : read-write

ADIRAWO : ADIRAWO
bits : 24 - 48 (25 bit)
access : read-write

ADIRAWHO : ADIRAWHO
bits : 25 - 50 (26 bit)
access : read-write


ADC_IMASK (IMASK)

ADC_IMASK
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_IMASK ADC_IMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADIMASKS ADIMASKG ADIMASKC ADIMASKHS ADIMASKHG ADIMASKHC ADIMASKL ADIMASKU ADIMASKO ADIMASKHO

ADIMASKS : ADIMASKS
bits : 0 - 0 (1 bit)
access : read-write

ADIMASKG : ADIMASKG
bits : 1 - 2 (2 bit)
access : read-write

ADIMASKC : ADIMASKC
bits : 2 - 4 (3 bit)
access : read-write

ADIMASKHS : ADIMASKHS
bits : 8 - 16 (9 bit)
access : read-write

ADIMASKHG : ADIMASKHG
bits : 9 - 18 (10 bit)
access : read-write

ADIMASKHC : ADIMASKHC
bits : 10 - 20 (11 bit)
access : read-write

ADIMASKL : ADIMASKL
bits : 16 - 32 (17 bit)
access : read-write

ADIMASKU : ADIMASKU
bits : 17 - 34 (18 bit)
access : read-write

ADIMASKO : ADIMASKO
bits : 24 - 48 (25 bit)
access : read-write

ADIMASKHO : ADIMASKHO
bits : 25 - 50 (26 bit)
access : read-write


ADC_ICLR (ICLR)

ADC_ICLR
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_ICLR ADC_ICLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADICLRS ADICLRG ADICLRC ADICLRHS ADICLRHG ADICLRHC ADICLRL ADICLRU ADICLRO ADICLRHO

ADICLRS : ADICLRS
bits : 0 - 0 (1 bit)
access : read-write

ADICLRG : ADICLRG
bits : 1 - 2 (2 bit)
access : read-write

ADICLRC : ADICLRC
bits : 2 - 4 (3 bit)
access : read-write

ADICLRHS : ADICLRHS
bits : 8 - 16 (9 bit)
access : read-write

ADICLRHG : ADICLRHG
bits : 9 - 18 (10 bit)
access : read-write

ADICLRHC : ADICLRHC
bits : 10 - 20 (11 bit)
access : read-write

ADICLRL : ADICLRL
bits : 16 - 32 (17 bit)
access : read-write

ADICLRU : ADICLRU
bits : 17 - 34 (18 bit)
access : read-write

ADICLRO : ADICLRO
bits : 24 - 48 (25 bit)
access : read-write

ADICLRHO : ADICLRHO
bits : 25 - 50 (26 bit)
access : read-write


ADC_LST1 (LST1)

ADC_LST1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_LST1 ADC_LST1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSEQ4 ADSEQ5 ADSEQ6 ADSEQ7

ADSEQ4 : ADSEQ4
bits : 0 - 4 (5 bit)
access : read-write

ADSEQ5 : ADSEQ5
bits : 8 - 20 (13 bit)
access : read-write

ADSEQ6 : ADSEQ6
bits : 16 - 36 (21 bit)
access : read-write

ADSEQ7 : ADSEQ7
bits : 24 - 52 (29 bit)
access : read-write


ADC_DMAR (DMAR)

ADC_DMAR
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DMAR ADC_DMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDMAS ADDMAG ADDMAC ADDMAHS ADDMAHG ADDMAHC

ADDMAS : ADDMAS
bits : 0 - 0 (1 bit)
access : read-write

ADDMAG : ADDMAG
bits : 1 - 2 (2 bit)
access : read-write

ADDMAC : ADDMAC
bits : 2 - 4 (3 bit)
access : read-write

ADDMAHS : ADDMAHS
bits : 8 - 16 (9 bit)
access : read-write

ADDMAHG : ADDMAHG
bits : 9 - 18 (10 bit)
access : read-write

ADDMAHC : ADDMAHC
bits : 10 - 20 (11 bit)
access : read-write


ADC_LST2 (LST2)

ADC_LST2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_LST2 ADC_LST2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSEQ8 ADSEQ9 ADSEQ10 ADSEQ11

ADSEQ8 : ADSEQ8
bits : 0 - 4 (5 bit)
access : read-write

ADSEQ9 : ADSEQ9
bits : 8 - 20 (13 bit)
access : read-write

ADSEQ10 : ADSEQ10
bits : 16 - 36 (21 bit)
access : read-write

ADSEQ11 : ADSEQ11
bits : 24 - 52 (29 bit)
access : read-write


ADC_LST3 (LST3)

ADC_LST3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_LST3 ADC_LST3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSEQ12 ADSEQ13 ADSEQ14 ADSEQ15

ADSEQ12 : ADSEQ12
bits : 0 - 4 (5 bit)
access : read-write

ADSEQ13 : ADSEQ13
bits : 8 - 20 (13 bit)
access : read-write

ADSEQ14 : ADSEQ14
bits : 16 - 36 (21 bit)
access : read-write

ADSEQ15 : ADSEQ15
bits : 24 - 52 (29 bit)
access : read-write


ADC_HLST (HLST)

ADC_HLST
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_HLST ADC_HLST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADHSEQ0 ADHSEQ1 ADHSEQ2 ADHSEQ3

ADHSEQ0 : ADHSEQ0
bits : 0 - 4 (5 bit)
access : read-write

ADHSEQ1 : ADHSEQ1
bits : 8 - 20 (13 bit)
access : read-write

ADHSEQ2 : ADHSEQ2
bits : 16 - 36 (21 bit)
access : read-write

ADHSEQ3 : ADHSEQ3
bits : 24 - 52 (29 bit)
access : read-write


ADC_OFR0 (OFR0)

ADC_OFR0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR0 ADC_OFR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF0 ADAL0 ADOFE0

ADOF0 : ADOF0
bits : 0 - 11 (12 bit)
access : read-write

ADAL0 : ADAL0
bits : 14 - 28 (15 bit)
access : read-write

ADOFE0 : ADOFE0
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR1 (OFR1)

ADC_OFR1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR1 ADC_OFR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF1 ADAL1 ADOFE1

ADOF1 : ADOF1
bits : 0 - 11 (12 bit)
access : read-write

ADAL1 : ADAL1
bits : 14 - 28 (15 bit)
access : read-write

ADOFE1 : ADOFE1
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR2 (OFR2)

ADC_OFR2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR2 ADC_OFR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF2 ADAL2 ADOFE2

ADOF2 : ADOF2
bits : 0 - 11 (12 bit)
access : read-write

ADAL2 : ADAL2
bits : 14 - 28 (15 bit)
access : read-write

ADOFE2 : ADOFE2
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR3 (OFR3)

ADC_OFR3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR3 ADC_OFR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF3 ADAL3 ADOFE3

ADOF3 : ADOF3
bits : 0 - 11 (12 bit)
access : read-write

ADAL3 : ADAL3
bits : 14 - 28 (15 bit)
access : read-write

ADOFE3 : ADOFE3
bits : 15 - 30 (16 bit)
access : read-write


ADC_RST (RST)

ADC_RST
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_RST ADC_RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRST

ADRST : ADRST
bits : 0 - 0 (1 bit)
access : read-write


ADC_OFR4 (OFR4)

ADC_OFR4
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR4 ADC_OFR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF4 ADAL4 ADOFE4

ADOF4 : ADOF4
bits : 0 - 11 (12 bit)
access : read-write

ADAL4 : ADAL4
bits : 14 - 28 (15 bit)
access : read-write

ADOFE4 : ADOFE4
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR5 (OFR5)

ADC_OFR5
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR5 ADC_OFR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF5 ADAL5 ADOFE5

ADOF5 : ADOF5
bits : 0 - 11 (12 bit)
access : read-write

ADAL5 : ADAL5
bits : 14 - 28 (15 bit)
access : read-write

ADOFE5 : ADOFE5
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR6 (OFR6)

ADC_OFR6
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR6 ADC_OFR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF6 ADAL6 ADOFE6

ADOF6 : ADOF6
bits : 0 - 11 (12 bit)
access : read-write

ADAL6 : ADAL6
bits : 14 - 28 (15 bit)
access : read-write

ADOFE6 : ADOFE6
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR7 (OFR7)

ADC_OFR7
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR7 ADC_OFR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF7 ADAL7 ADOFE7

ADOF7 : ADOF7
bits : 0 - 11 (12 bit)
access : read-write

ADAL7 : ADAL7
bits : 14 - 28 (15 bit)
access : read-write

ADOFE7 : ADOFE7
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR8 (OFR8)

ADC_OFR8
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR8 ADC_OFR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF8 ADAL8 ADOFE8

ADOF8 : ADOF8
bits : 0 - 11 (12 bit)
access : read-write

ADAL8 : ADAL8
bits : 14 - 28 (15 bit)
access : read-write

ADOFE8 : ADOFE8
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR9 (OFR9)

ADC_OFR9
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR9 ADC_OFR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF9 ADAL9 ADOFE9

ADOF9 : ADOF9
bits : 0 - 11 (12 bit)
access : read-write

ADAL9 : ADAL9
bits : 14 - 28 (15 bit)
access : read-write

ADOFE9 : ADOFE9
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR10 (OFR10)

ADC_OFR10
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR10 ADC_OFR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF10 ADAL10 ADOFE10

ADOF10 : ADOF10
bits : 0 - 11 (12 bit)
access : read-write

ADAL10 : ADAL10
bits : 14 - 28 (15 bit)
access : read-write

ADOFE10 : ADOFE10
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR11 (OFR11)

ADC_OFR11
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR11 ADC_OFR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF11 ADAL11 ADOFE11

ADOF11 : ADOF11
bits : 0 - 11 (12 bit)
access : read-write

ADAL11 : ADAL11
bits : 14 - 28 (15 bit)
access : read-write

ADOFE11 : ADOFE11
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR12 (OFR12)

ADC_OFR12
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR12 ADC_OFR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF12 ADAL12 ADOFE12

ADOF12 : ADOF12
bits : 0 - 11 (12 bit)
access : read-write

ADAL12 : ADAL12
bits : 14 - 28 (15 bit)
access : read-write

ADOFE12 : ADOFE12
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR13 (OFR13)

ADC_OFR13
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR13 ADC_OFR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF13 ADAL13 ADOFE13

ADOF13 : ADOF13
bits : 0 - 11 (12 bit)
access : read-write

ADAL13 : ADAL13
bits : 14 - 28 (15 bit)
access : read-write

ADOFE13 : ADOFE13
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR14 (OFR14)

ADC_OFR14
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR14 ADC_OFR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF14 ADAL14 ADOFE14

ADOF14 : ADOF14
bits : 0 - 11 (12 bit)
access : read-write

ADAL14 : ADAL14
bits : 14 - 28 (15 bit)
access : read-write

ADOFE14 : ADOFE14
bits : 15 - 30 (16 bit)
access : read-write


ADC_OFR15 (OFR15)

ADC_OFR15
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR15 ADC_OFR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOF15 ADAL15 ADOFE15

ADOF15 : ADOF15
bits : 0 - 11 (12 bit)
access : read-write

ADAL15 : ADAL15
bits : 14 - 28 (15 bit)
access : read-write

ADOFE15 : ADOFE15
bits : 15 - 30 (16 bit)
access : read-write


ADC_STR0 (STR0)

ADC_STR0
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR0 ADC_STR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST0

ADST0 : ADST0
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR1 (STR1)

ADC_STR1
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR1 ADC_STR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST1

ADST1 : ADST1
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR2 (STR2)

ADC_STR2
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR2 ADC_STR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST2

ADST2 : ADST2
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR3 (STR3)

ADC_STR3
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR3 ADC_STR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST3

ADST3 : ADST3
bits : 0 - 7 (8 bit)
access : read-write


ADC_CONV (CONV)

ADC_CONV
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CONV ADC_CONV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADMODE ADSEQL ADSUBL

ADMODE : ADMODE
bits : 0 - 1 (2 bit)
access : read-write

ADSEQL : ADSEQL
bits : 8 - 19 (12 bit)
access : read-write

ADSUBL : ADSUBL
bits : 16 - 35 (20 bit)
access : read-write


ADC_STR4 (STR4)

ADC_STR4
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR4 ADC_STR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST4

ADST4 : ADST4
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR5 (STR5)

ADC_STR5
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR5 ADC_STR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST5

ADST5 : ADST5
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR6 (STR6)

ADC_STR6
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR6 ADC_STR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST6

ADST6 : ADST6
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR7 (STR7)

ADC_STR7
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR7 ADC_STR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST7

ADST7 : ADST7
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR8 (STR8)

ADC_STR8
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR8 ADC_STR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST8

ADST8 : ADST8
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR9 (STR9)

ADC_STR9
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR9 ADC_STR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST9

ADST9 : ADST9
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR10 (STR10)

ADC_STR10
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR10 ADC_STR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST10

ADST10 : ADST10
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR11 (STR11)

ADC_STR11
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR11 ADC_STR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST11

ADST11 : ADST11
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR12 (STR12)

ADC_STR12
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR12 ADC_STR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST12

ADST12 : ADST12
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR13 (STR13)

ADC_STR13
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR13 ADC_STR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST13

ADST13 : ADST13
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR14 (STR14)

ADC_STR14
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR14 ADC_STR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST14

ADST14 : ADST14
bits : 0 - 7 (8 bit)
access : read-write


ADC_STR15 (STR15)

ADC_STR15
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR15 ADC_STR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST15

ADST15 : ADST15
bits : 0 - 7 (8 bit)
access : read-write


ADC_DR0 (DR0)

ADC_DR0
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR0 ADC_DR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD0 ADVLD0

ADD0 : ADD0
bits : 0 - 15 (16 bit)
access : read-write

ADVLD0 : ADVLD0
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR1 (DR1)

ADC_DR1
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR1 ADC_DR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD1 ADVLD1

ADD1 : ADD1
bits : 0 - 15 (16 bit)
access : read-write

ADVLD1 : ADVLD1
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR2 (DR2)

ADC_DR2
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR2 ADC_DR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD2 ADVLD2

ADD2 : ADD2
bits : 0 - 15 (16 bit)
access : read-write

ADVLD2 : ADVLD2
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR3 (DR3)

ADC_DR3
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR3 ADC_DR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD3 ADVLD3

ADD3 : ADD3
bits : 0 - 15 (16 bit)
access : read-write

ADVLD3 : ADVLD3
bits : 31 - 62 (32 bit)
access : read-write


ADC_HCONV (HCONV)

ADC_HCONV
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_HCONV ADC_HCONV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADHMODE ADHSEQL ADHSUBL

ADHMODE : ADHMODE
bits : 0 - 1 (2 bit)
access : read-write

ADHSEQL : ADHSEQL
bits : 8 - 17 (10 bit)
access : read-write

ADHSUBL : ADHSUBL
bits : 16 - 33 (18 bit)
access : read-write


ADC_DR4 (DR4)

ADC_DR4
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR4 ADC_DR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD4 ADVLD4

ADD4 : ADD4
bits : 0 - 15 (16 bit)
access : read-write

ADVLD4 : ADVLD4
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR5 (DR5)

ADC_DR5
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR5 ADC_DR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD5 ADVLD5

ADD5 : ADD5
bits : 0 - 15 (16 bit)
access : read-write

ADVLD5 : ADVLD5
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR6 (DR6)

ADC_DR6
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR6 ADC_DR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD6 ADVLD6

ADD6 : ADD6
bits : 0 - 15 (16 bit)
access : read-write

ADVLD6 : ADVLD6
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR7 (DR7)

ADC_DR7
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR7 ADC_DR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD7 ADVLD7

ADD7 : ADD7
bits : 0 - 15 (16 bit)
access : read-write

ADVLD7 : ADVLD7
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR8 (DR8)

ADC_DR8
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR8 ADC_DR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD8 ADVLD8

ADD8 : ADD8
bits : 0 - 15 (16 bit)
access : read-write

ADVLD8 : ADVLD8
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR9 (DR9)

ADC_DR9
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR9 ADC_DR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD9 ADVLD9

ADD9 : ADD9
bits : 0 - 15 (16 bit)
access : read-write

ADVLD9 : ADVLD9
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR10 (DR10)

ADC_DR10
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR10 ADC_DR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD10 ADVLD10

ADD10 : ADD10
bits : 0 - 15 (16 bit)
access : read-write

ADVLD10 : ADVLD10
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR11 (DR11)

ADC_DR11
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR11 ADC_DR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD11 ADVLD11

ADD11 : ADD11
bits : 0 - 15 (16 bit)
access : read-write

ADVLD11 : ADVLD11
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR12 (DR12)

ADC_DR12
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR12 ADC_DR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD12 ADVLD12

ADD12 : ADD12
bits : 0 - 15 (16 bit)
access : read-write

ADVLD12 : ADVLD12
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR13 (DR13)

ADC_DR13
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR13 ADC_DR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD13 ADVLD13

ADD13 : ADD13
bits : 0 - 15 (16 bit)
access : read-write

ADVLD13 : ADVLD13
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR14 (DR14)

ADC_DR14
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR14 ADC_DR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD14 ADVLD14

ADD14 : ADD14
bits : 0 - 15 (16 bit)
access : read-write

ADVLD14 : ADVLD14
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR15 (DR15)

ADC_DR15
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR15 ADC_DR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD15 ADVLD15

ADD15 : ADD15
bits : 0 - 15 (16 bit)
access : read-write

ADVLD15 : ADVLD15
bits : 31 - 62 (32 bit)
access : read-write


ADC_HDR0 (HDR0)

ADC_HDR0
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_HDR0 ADC_HDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADHD0 ADHVLD0

ADHD0 : ADHD0
bits : 0 - 15 (16 bit)
access : read-write

ADHVLD0 : ADHVLD0
bits : 31 - 62 (32 bit)
access : read-write


ADC_HDR1 (HDR1)

ADC_HDR1
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_HDR1 ADC_HDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADHD1 ADHVLD1

ADHD1 : ADHD1
bits : 0 - 15 (16 bit)
access : read-write

ADHVLD1 : ADHVLD1
bits : 31 - 62 (32 bit)
access : read-write


ADC_HDR2 (HDR2)

ADC_HDR2
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_HDR2 ADC_HDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADHD2 ADHVLD2

ADHD2 : ADHD2
bits : 0 - 15 (16 bit)
access : read-write

ADHVLD2 : ADHVLD2
bits : 31 - 62 (32 bit)
access : read-write


ADC_HDR3 (HDR3)

ADC_HDR3
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_HDR3 ADC_HDR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADHD3 ADHVLD3

ADHD3 : ADHD3
bits : 0 - 15 (16 bit)
access : read-write

ADHVLD3 : ADHVLD3
bits : 31 - 62 (32 bit)
access : read-write



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