\n

SCI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SCI_CR (CR)

SCI_GT (GT)

SCI_WT (WT)

SCI_IER (IER)

SCI_IPR (IPR)

SCI_TXB (TXB)

SCI_RXB (RXB)

SCI_PSC (PSC)

SCI_SR (SR)

SCI_CCR (CCR)

SCI_ETU (ETU)


SCI_CR (CR)

SCI_CR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCI_CR SCI_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONV CREP WTEN SCIM RETRY4_5 ENSCI DETCNF TXDMA RXDMA

CONV : CONV
bits : 0 - 0 (1 bit)
access : read-write

CREP : CREP
bits : 1 - 2 (2 bit)
access : read-write

WTEN : WTEN
bits : 2 - 4 (3 bit)
access : read-write

SCIM : SCIM
bits : 3 - 6 (4 bit)
access : read-write

RETRY4_5 : RETRY4_5
bits : 4 - 8 (5 bit)
access : read-write

ENSCI : ENSCI
bits : 5 - 10 (6 bit)
access : read-write

DETCNF : DETCNF
bits : 6 - 12 (7 bit)
access : read-write

TXDMA : TXDMA
bits : 8 - 16 (9 bit)
access : read-write

RXDMA : RXDMA
bits : 9 - 18 (10 bit)
access : read-write


SCI_GT (GT)

SCI_GT
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCI_GT SCI_GT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GT

GT : GT
bits : 0 - 8 (9 bit)
access : read-write


SCI_WT (WT)

SCI_WT
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCI_WT SCI_WT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WT

WT : WT
bits : 0 - 23 (24 bit)
access : read-write


SCI_IER (IER)

SCI_IER
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCI_IER SCI_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARE RXCE TXCE WTE CARDIRE TXBEE

PARE : PARE
bits : 0 - 0 (1 bit)
access : read-write

RXCE : RXCE
bits : 1 - 2 (2 bit)
access : read-write

TXCE : TXCE
bits : 2 - 4 (3 bit)
access : read-write

WTE : WTE
bits : 3 - 6 (4 bit)
access : read-write

CARDIRE : CARDIRE
bits : 6 - 12 (7 bit)
access : read-write

TXBEE : TXBEE
bits : 7 - 14 (8 bit)
access : read-write


SCI_IPR (IPR)

SCI_IPR
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCI_IPR SCI_IPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARP RXCP TXCP WTP CARDIRP TXBEP

PARP : PARP
bits : 0 - 0 (1 bit)
access : read-write

RXCP : RXCP
bits : 1 - 2 (2 bit)
access : read-write

TXCP : TXCP
bits : 2 - 4 (3 bit)
access : read-write

WTP : WTP
bits : 3 - 6 (4 bit)
access : read-write

CARDIRP : CARDIRP
bits : 6 - 12 (7 bit)
access : read-write

TXBEP : TXBEP
bits : 7 - 14 (8 bit)
access : read-write


SCI_TXB (TXB)

SCI_TXB
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCI_TXB SCI_TXB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TB

TB : TB
bits : 0 - 7 (8 bit)
access : read-write


SCI_RXB (RXB)

SCI_RXB
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCI_RXB SCI_RXB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB

RB : RB
bits : 0 - 7 (8 bit)
access : read-write


SCI_PSC (PSC)

SCI_PSC
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCI_PSC SCI_PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : PSC
bits : 0 - 5 (6 bit)
access : read-write


SCI_SR (SR)

SCI_SR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCI_SR SCI_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARF RXCF TXCF WTF CPREF TXBEF

PARF : PARF
bits : 0 - 0 (1 bit)
access : read-write

RXCF : RXCF
bits : 1 - 2 (2 bit)
access : read-write

TXCF : TXCF
bits : 2 - 4 (3 bit)
access : read-write

WTF : WTF
bits : 3 - 6 (4 bit)
access : read-write

CPREF : CPREF
bits : 6 - 12 (7 bit)
access : read-write

TXBEF : TXBEF
bits : 7 - 14 (8 bit)
access : read-write


SCI_CCR (CCR)

SCI_CCR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCI_CCR SCI_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCLK CDIO CLKSEL

CCLK : CCLK
bits : 2 - 4 (3 bit)
access : read-write

CDIO : CDIO
bits : 3 - 6 (4 bit)
access : read-write

CLKSEL : CLKSEL
bits : 7 - 14 (8 bit)
access : read-write


SCI_ETU (ETU)

SCI_ETU
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCI_ETU SCI_ETU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETU COMP

ETU : ETU
bits : 0 - 10 (11 bit)
access : read-write

COMP : COMP
bits : 15 - 30 (16 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.