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FMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FMC_TADR (TADR)

FMC_OPCR (OPCR)

FMC_VMCR (VMCR)

FMC_OIER (OIER)

FMC_OISR (OISR)

FMC_PPSR0 (PPSR0)

FMC_CFCR (CFCR)

FMC_PPSR1 (PPSR1)

FMC_PPSR2 (PPSR2)

FMC_PPSR3 (PPSR3)

FMC_CPSR (CPSR)

FMC_SBVT0 (SBVT0)

FMC_SBVT1 (SBVT1)

FMC_SBVT2 (SBVT2)

FMC_SBVT3 (SBVT3)

FMC_WRDR (WRDR)

FMC_OCMR (OCMR)


FMC_TADR (TADR)

FMC_TADR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_TADR FMC_TADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TADB

TADB : TADB
bits : 0 - 31 (32 bit)
access : read-write


FMC_OPCR (OPCR)

FMC_OPCR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_OPCR FMC_OPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPM

OPM : OPM
bits : 1 - 5 (5 bit)
access : read-write


FMC_VMCR (VMCR)

FMC_VMCR
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_VMCR FMC_VMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMCB

VMCB : VMCB
bits : 0 - 1 (2 bit)
access : read-write


FMC_OIER (OIER)

FMC_OIER
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_OIER FMC_OIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ORFIEN ITADIEN OBEIEN IOCMIEN OREIEN

ORFIEN : ORFIEN
bits : 0 - 0 (1 bit)
access : read-write

ITADIEN : ITADIEN
bits : 1 - 2 (2 bit)
access : read-write

OBEIEN : OBEIEN
bits : 2 - 4 (3 bit)
access : read-write

IOCMIEN : IOCMIEN
bits : 3 - 6 (4 bit)
access : read-write

OREIEN : OREIEN
bits : 4 - 8 (5 bit)
access : read-write


FMC_OISR (OISR)

FMC_OISR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_OISR FMC_OISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ORFF ITADF OBEF IOCMF OREF RORFF PPEF

ORFF : ORFF
bits : 0 - 0 (1 bit)
access : read-write

ITADF : ITADF
bits : 1 - 2 (2 bit)
access : read-write

OBEF : OBEF
bits : 2 - 4 (3 bit)
access : read-write

IOCMF : IOCMF
bits : 3 - 6 (4 bit)
access : read-write

OREF : OREF
bits : 4 - 8 (5 bit)
access : read-write

RORFF : RORFF
bits : 16 - 32 (17 bit)
access : read-write

PPEF : PPEF
bits : 17 - 34 (18 bit)
access : read-write


FMC_PPSR0 (PPSR0)

FMC_PPSR0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_PPSR0 FMC_PPSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPSB

PPSB : PPSB
bits : 0 - 31 (32 bit)
access : read-write


FMC_CFCR (CFCR)

FMC_CFCR
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_CFCR FMC_CFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAIT PFBE DCDB CE FHLAEN FZWPSEN

WAIT : WAIT
bits : 0 - 2 (3 bit)
access : read-write

PFBE : PFBE
bits : 4 - 8 (5 bit)
access : read-write

DCDB : DCDB
bits : 7 - 14 (8 bit)
access : read-write

CE : CE
bits : 12 - 24 (13 bit)
access : read-write

FHLAEN : FHLAEN
bits : 15 - 30 (16 bit)
access : read-write

FZWPSEN : FZWPSEN
bits : 16 - 32 (17 bit)
access : read-write


FMC_PPSR1 (PPSR1)

FMC_PPSR1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_PPSR1 FMC_PPSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPSB

PPSB : PPSB
bits : 0 - 31 (32 bit)
access : read-write


FMC_PPSR2 (PPSR2)

FMC_PPSR2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_PPSR2 FMC_PPSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPSB

PPSB : PPSB
bits : 0 - 31 (32 bit)
access : read-write


FMC_PPSR3 (PPSR3)

FMC_PPSR3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_PPSR3 FMC_PPSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPSB

PPSB : PPSB
bits : 0 - 31 (32 bit)
access : read-write


FMC_CPSR (CPSR)

FMC_CPSR
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_CPSR FMC_CPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPSB OBPSB

CPSB : CPSB
bits : 0 - 0 (1 bit)
access : read-write

OBPSB : OBPSB
bits : 1 - 2 (2 bit)
access : read-write


FMC_SBVT0 (SBVT0)

FMC_SBVT0
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_SBVT0 FMC_SBVT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBVT

SBVT : SBVT
bits : 0 - 31 (32 bit)
access : read-write


FMC_SBVT1 (SBVT1)

FMC_SBVT1
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_SBVT1 FMC_SBVT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBVT

SBVT : SBVT
bits : 0 - 31 (32 bit)
access : read-write


FMC_SBVT2 (SBVT2)

FMC_SBVT2
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_SBVT2 FMC_SBVT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBVT

SBVT : SBVT
bits : 0 - 31 (32 bit)
access : read-write


FMC_SBVT3 (SBVT3)

FMC_SBVT3
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_SBVT3 FMC_SBVT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBVT

SBVT : SBVT
bits : 0 - 31 (32 bit)
access : read-write


FMC_WRDR (WRDR)

FMC_WRDR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_WRDR FMC_WRDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRDB

WRDB : WRDB
bits : 0 - 31 (32 bit)
access : read-write


FMC_OCMR (OCMR)

FMC_OCMR
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_OCMR FMC_OCMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD

CMD : CMD
bits : 0 - 3 (4 bit)
access : read-write



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