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UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

UART1_RBR (RBR)

UART1_TBR (TBR)

UART1_LCR (LCR)

UART1_LSR (LSR)

UART1_TPR (TPR)

UART1_MDR (MDR)

UART1_FSR (FSR)

UART1_DLR (DLR)

UART1_IER (IER)

UART1_DEGTSTR (DEGTSTR)

UART1_IIR (IIR)

UART1_FCR (FCR)


UART1_RBR (RBR)

UART1_RBR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART1_RBR UART1_RBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD

RD : RD
bits : 0 - 8 (9 bit)
access : read-write


UART1_TBR (TBR)

UART1_TBR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : UART1
reset_Mask : 0x0

UART1_TBR UART1_TBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TD

TD : TD
bits : 0 - 8 (9 bit)
access : read-write


UART1_LCR (LCR)

UART1_LCR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART1_LCR UART1_LCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLS NSB PBE EPE SPE BCB

WLS : WLS
bits : 0 - 1 (2 bit)
access : read-write

NSB : NSB
bits : 2 - 4 (3 bit)
access : read-write

PBE : PBE
bits : 3 - 6 (4 bit)
access : read-write

EPE : EPE
bits : 4 - 8 (5 bit)
access : read-write

SPE : SPE
bits : 5 - 10 (6 bit)
access : read-write

BCB : BCB
bits : 6 - 12 (7 bit)
access : read-write


UART1_LSR (LSR)

UART1_LSR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART1_LSR UART1_LSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFDR OEI PEI FEI BII TXFEMPT TXEMPT ERRRX

RFDR : RFDR
bits : 0 - 0 (1 bit)
access : read-write

OEI : OEI
bits : 1 - 2 (2 bit)
access : read-write

PEI : PEI
bits : 2 - 4 (3 bit)
access : read-write

FEI : FEI
bits : 3 - 6 (4 bit)
access : read-write

BII : BII
bits : 4 - 8 (5 bit)
access : read-write

TXFEMPT : TXFEMPT
bits : 5 - 10 (6 bit)
access : read-write

TXEMPT : TXEMPT
bits : 6 - 12 (7 bit)
access : read-write

ERRRX : ERRRX
bits : 7 - 14 (8 bit)
access : read-write


UART1_TPR (TPR)

UART1_TPR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART1_TPR UART1_TPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTOIC RTOIE TG

RTOIC : RTOIC
bits : 0 - 6 (7 bit)
access : read-write

RTOIE : RTOIE
bits : 7 - 14 (8 bit)
access : read-write

TG : TG
bits : 8 - 23 (16 bit)
access : read-write


UART1_MDR (MDR)

UART1_MDR
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART1_MDR UART1_MDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE TRSM TXDMAEN RXDMAEN

MODE : MODE
bits : 0 - 1 (2 bit)
access : read-write

TRSM : TRSM
bits : 2 - 4 (3 bit)
access : read-write

TXDMAEN : TXDMAEN
bits : 4 - 8 (5 bit)
access : read-write

RXDMAEN : RXDMAEN
bits : 5 - 10 (6 bit)
access : read-write


UART1_FSR (FSR)

UART1_FSR
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART1_FSR UART1_FSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFS RXFS

TXFS : TXFS
bits : 0 - 4 (5 bit)
access : read-write

RXFS : RXFS
bits : 8 - 20 (13 bit)
access : read-write


UART1_DLR (DLR)

UART1_DLR
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART1_DLR UART1_DLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRD

BRD : BRD
bits : 0 - 15 (16 bit)
access : read-write


UART1_IER (IER)

UART1_IER
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART1_IER UART1_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFTLI_RTOIE TFTLIE RLSIE

RFTLI_RTOIE : RFTLI_RTOIE
bits : 0 - 0 (1 bit)
access : read-write

TFTLIE : TFTLIE
bits : 1 - 2 (2 bit)
access : read-write

RLSIE : RLSIE
bits : 2 - 4 (3 bit)
access : read-write


UART1_DEGTSTR (DEGTSTR)

UART1_DEGTSTR
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART1_DEGTSTR UART1_DEGTSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBM

LBM : LBM
bits : 0 - 1 (2 bit)
access : read-write


UART1_IIR (IIR)

UART1_IIR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART1_IIR UART1_IIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NIP IID

NIP : NIP
bits : 0 - 0 (1 bit)
access : read-write

IID : IID
bits : 1 - 4 (4 bit)
access : read-write


UART1_FCR (FCR)

UART1_FCR
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART1_FCR UART1_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FME RFR TFR TFTL RFTL URTXEN URRXEN

FME : FME
bits : 0 - 0 (1 bit)
access : read-write

RFR : RFR
bits : 1 - 2 (2 bit)
access : read-write

TFR : TFR
bits : 2 - 4 (3 bit)
access : read-write

TFTL : TFTL
bits : 4 - 9 (6 bit)
access : read-write

RFTL : RFTL
bits : 6 - 13 (8 bit)
access : read-write

URTXEN : URTXEN
bits : 8 - 16 (9 bit)
access : read-write

URRXEN : URRXEN
bits : 9 - 18 (10 bit)
access : read-write



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