\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
PDMA_CH0CR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : CHEN
bits : 0 - 0 (1 bit)
access : read-write
SWTRIG : SWTRIG
bits : 1 - 2 (2 bit)
access : read-write
DWIDTH : DWIDTH
bits : 2 - 5 (4 bit)
access : read-write
DSTAINC : DSTAINC
bits : 4 - 8 (5 bit)
access : read-write
DSTAMOD : DSTAMOD
bits : 5 - 10 (6 bit)
access : read-write
SRCAINC : SRCAINC
bits : 6 - 12 (7 bit)
access : read-write
SRCAMOD : SRCAMOD
bits : 7 - 14 (8 bit)
access : read-write
CHPRI : CHPRI
bits : 8 - 17 (10 bit)
access : read-write
FIXAEN : FIXAEN
bits : 10 - 20 (11 bit)
access : read-write
AUTORL : AUTORL
bits : 11 - 22 (12 bit)
access : read-write
PDMA_CH0TSR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLKLEN : BLKLEN
bits : 0 - 7 (8 bit)
access : read-write
BLKCNT : BLKCNT
bits : 16 - 47 (32 bit)
access : read-write
PDMA_ISR
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEISTA0 : GEISTA0
bits : 0 - 0 (1 bit)
access : read-write
BEISTA0 : BEISTA0
bits : 1 - 2 (2 bit)
access : read-write
HTISTA0 : HTISTA0
bits : 2 - 4 (3 bit)
access : read-write
TCISTA0 : TCISTA0
bits : 3 - 6 (4 bit)
access : read-write
TEISTA0 : TEISTA0
bits : 4 - 8 (5 bit)
access : read-write
GEISTA1 : GEISTA1
bits : 5 - 10 (6 bit)
access : read-write
BEISTA1 : BEISTA1
bits : 6 - 12 (7 bit)
access : read-write
HTISTA1 : HTISTA1
bits : 7 - 14 (8 bit)
access : read-write
TCISTA1 : TCISTA1
bits : 8 - 16 (9 bit)
access : read-write
TEISTA1 : TEISTA1
bits : 9 - 18 (10 bit)
access : read-write
GEISTA2 : GEISTA2
bits : 10 - 20 (11 bit)
access : read-write
BEISTA2 : BEISTA2
bits : 11 - 22 (12 bit)
access : read-write
HTISTA2 : HTISTA2
bits : 12 - 24 (13 bit)
access : read-write
TCISTA2 : TCISTA2
bits : 13 - 26 (14 bit)
access : read-write
TEISTA2 : TEISTA2
bits : 14 - 28 (15 bit)
access : read-write
GEISTA3 : GEISTA3
bits : 15 - 30 (16 bit)
access : read-write
BEISTA3 : BEISTA3
bits : 16 - 32 (17 bit)
access : read-write
HTISTA3 : HTISTA3
bits : 17 - 34 (18 bit)
access : read-write
TCISTA3 : TCISTA3
bits : 18 - 36 (19 bit)
access : read-write
TEISTA3 : TEISTA3
bits : 19 - 38 (20 bit)
access : read-write
GEISTA4 : GEISTA4
bits : 20 - 40 (21 bit)
access : read-write
BEISTA4 : BEISTA4
bits : 21 - 42 (22 bit)
access : read-write
HTISTA4 : HTISTA4
bits : 22 - 44 (23 bit)
access : read-write
TCISTA4 : TCISTA4
bits : 23 - 46 (24 bit)
access : read-write
TEISTA4 : TEISTA4
bits : 24 - 48 (25 bit)
access : read-write
GEISTA5 : GEISTA5
bits : 25 - 50 (26 bit)
access : read-write
BEISTA5 : BEISTA5
bits : 26 - 52 (27 bit)
access : read-write
HTISTA5 : HTISTA5
bits : 27 - 54 (28 bit)
access : read-write
TCISTA5 : TCISTA5
bits : 28 - 56 (29 bit)
access : read-write
TEISTA5 : TEISTA5
bits : 29 - 58 (30 bit)
access : read-write
PDMA_ISCR
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEICLR0 : GEICLR0
bits : 0 - 0 (1 bit)
access : read-write
BEICLR0 : BEICLR0
bits : 1 - 2 (2 bit)
access : read-write
HTICLR0 : HTICLR0
bits : 2 - 4 (3 bit)
access : read-write
TCICLR0 : TCICLR0
bits : 3 - 6 (4 bit)
access : read-write
TEICLR0 : TEICLR0
bits : 4 - 8 (5 bit)
access : read-write
GEICLR1 : GEICLR1
bits : 5 - 10 (6 bit)
access : read-write
BEICLR1 : BEICLR1
bits : 6 - 12 (7 bit)
access : read-write
HTICLR1 : HTICLR1
bits : 7 - 14 (8 bit)
access : read-write
TCICLR1 : TCICLR1
bits : 8 - 16 (9 bit)
access : read-write
TEICLR1 : TEICLR1
bits : 9 - 18 (10 bit)
access : read-write
GEICLR2 : GEICLR2
bits : 10 - 20 (11 bit)
access : read-write
BEICLR2 : BEICLR2
bits : 11 - 22 (12 bit)
access : read-write
HTICLR2 : HTICLR2
bits : 12 - 24 (13 bit)
access : read-write
TCICLR2 : TCICLR2
bits : 13 - 26 (14 bit)
access : read-write
TEICLR2 : TEICLR2
bits : 14 - 28 (15 bit)
access : read-write
GEICLR3 : GEICLR3
bits : 15 - 30 (16 bit)
access : read-write
BEICLR3 : BEICLR3
bits : 16 - 32 (17 bit)
access : read-write
HTICLR3 : HTICLR3
bits : 17 - 34 (18 bit)
access : read-write
TCICLR3 : TCICLR3
bits : 18 - 36 (19 bit)
access : read-write
TEICLR3 : TEICLR3
bits : 19 - 38 (20 bit)
access : read-write
GEICLR4 : GEICLR4
bits : 20 - 40 (21 bit)
access : read-write
BEICLR4 : BEICLR4
bits : 21 - 42 (22 bit)
access : read-write
HTICLR4 : HTICLR4
bits : 22 - 44 (23 bit)
access : read-write
TCICLR4 : TCICLR4
bits : 23 - 46 (24 bit)
access : read-write
TEICLR4 : TEICLR4
bits : 24 - 48 (25 bit)
access : read-write
GEICLR5 : GEICLR5
bits : 25 - 50 (26 bit)
access : read-write
BEICLR5 : BEICLR5
bits : 26 - 52 (27 bit)
access : read-write
HTICLR5 : HTICLR5
bits : 27 - 54 (28 bit)
access : read-write
TCICLR5 : TCICLR5
bits : 28 - 56 (29 bit)
access : read-write
TEICLR5 : TEICLR5
bits : 29 - 58 (30 bit)
access : read-write
PDMA_IER
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEIE0 : GEIE0
bits : 0 - 0 (1 bit)
access : read-write
BEIE0 : BEIE0
bits : 1 - 2 (2 bit)
access : read-write
HTIE0 : HTIE0
bits : 2 - 4 (3 bit)
access : read-write
TCIE0 : TCIE0
bits : 3 - 6 (4 bit)
access : read-write
TEIE0 : TEIE0
bits : 4 - 8 (5 bit)
access : read-write
GEIE1 : GEIE1
bits : 5 - 10 (6 bit)
access : read-write
BEIE1 : BEIE1
bits : 6 - 12 (7 bit)
access : read-write
HTIE1 : HTIE1
bits : 7 - 14 (8 bit)
access : read-write
TCIE1 : TCIE1
bits : 8 - 16 (9 bit)
access : read-write
TEIE1 : TEIE1
bits : 9 - 18 (10 bit)
access : read-write
GEIE2 : GEIE2
bits : 10 - 20 (11 bit)
access : read-write
BEIE2 : BEIE2
bits : 11 - 22 (12 bit)
access : read-write
HTIE2 : HTIE2
bits : 12 - 24 (13 bit)
access : read-write
TCIE2 : TCIE2
bits : 13 - 26 (14 bit)
access : read-write
TEIE2 : TEIE2
bits : 14 - 28 (15 bit)
access : read-write
GEIE3 : GEIE3
bits : 15 - 30 (16 bit)
access : read-write
BEIE3 : BEIE3
bits : 16 - 32 (17 bit)
access : read-write
HTIE3 : HTIE3
bits : 17 - 34 (18 bit)
access : read-write
TCIE3 : TCIE3
bits : 18 - 36 (19 bit)
access : read-write
TEIE3 : TEIE3
bits : 19 - 38 (20 bit)
access : read-write
GEIE4 : GEIE4
bits : 20 - 40 (21 bit)
access : read-write
BEIE4 : BEIE4
bits : 21 - 42 (22 bit)
access : read-write
HTIE4 : HTIE4
bits : 22 - 44 (23 bit)
access : read-write
TCIE4 : TCIE4
bits : 23 - 46 (24 bit)
access : read-write
TEIE4 : TEIE4
bits : 24 - 48 (25 bit)
access : read-write
GEIE5 : GEIE5
bits : 25 - 50 (26 bit)
access : read-write
BEIE5 : BEIE5
bits : 26 - 52 (27 bit)
access : read-write
HTIE5 : HTIE5
bits : 27 - 54 (28 bit)
access : read-write
TCIE5 : TCIE5
bits : 28 - 56 (29 bit)
access : read-write
TEIE5 : TEIE5
bits : 29 - 58 (30 bit)
access : read-write
PDMA_CH0CTSR
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBLKCNT : CBLKCNT
bits : 16 - 47 (32 bit)
access : read-write
PDMA_CH1CR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : CHEN
bits : 0 - 0 (1 bit)
access : read-write
SWTRIG : SWTRIG
bits : 1 - 2 (2 bit)
access : read-write
DWIDTH : DWIDTH
bits : 2 - 5 (4 bit)
access : read-write
DSTAINC : DSTAINC
bits : 4 - 8 (5 bit)
access : read-write
DSTAMOD : DSTAMOD
bits : 5 - 10 (6 bit)
access : read-write
SRCAINC : SRCAINC
bits : 6 - 12 (7 bit)
access : read-write
SRCAMOD : SRCAMOD
bits : 7 - 14 (8 bit)
access : read-write
CHPRI : CHPRI
bits : 8 - 17 (10 bit)
access : read-write
FIXAEN : FIXAEN
bits : 10 - 20 (11 bit)
access : read-write
AUTORL : AUTORL
bits : 11 - 22 (12 bit)
access : read-write
PDMA_CH1SADR
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : SADR
bits : 0 - 31 (32 bit)
access : read-write
PDMA_CH1DADR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADR : DADR
bits : 0 - 31 (32 bit)
access : read-write
PDMA_CH1TSR
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLKLEN : BLKLEN
bits : 0 - 7 (8 bit)
access : read-write
BLKCNT : BLKCNT
bits : 16 - 47 (32 bit)
access : read-write
PDMA_CH1CTSR
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBLKLEN : CBLKLEN
bits : 0 - 15 (16 bit)
access : read-write
CBLKCNT : CBLKCNT
bits : 16 - 47 (32 bit)
access : read-write
PDMA_CH2CR
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : CHEN
bits : 0 - 0 (1 bit)
access : read-write
SWTRIG : SWTRIG
bits : 1 - 2 (2 bit)
access : read-write
DWIDTH : DWIDTH
bits : 2 - 5 (4 bit)
access : read-write
DSTAINC : DSTAINC
bits : 4 - 8 (5 bit)
access : read-write
DSTAMOD : DSTAMOD
bits : 5 - 10 (6 bit)
access : read-write
SRCAINC : SRCAINC
bits : 6 - 12 (7 bit)
access : read-write
SRCAMOD : SRCAMOD
bits : 7 - 14 (8 bit)
access : read-write
CHPRI : CHPRI
bits : 8 - 17 (10 bit)
access : read-write
FIXAEN : FIXAEN
bits : 10 - 20 (11 bit)
access : read-write
AUTORL : AUTORL
bits : 11 - 22 (12 bit)
access : read-write
PDMA_CH2SADR
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : SADR
bits : 0 - 31 (32 bit)
access : read-write
PDMA_CH2DADR
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADR : DADR
bits : 0 - 31 (32 bit)
access : read-write
PDMA_CH0SADR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : SADR
bits : 0 - 31 (32 bit)
access : read-write
PDMA_CH2TSR
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLKLEN : BLKLEN
bits : 0 - 7 (8 bit)
access : read-write
BLKCNT : BLKCNT
bits : 16 - 47 (32 bit)
access : read-write
PDMA_CH2CTSR
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBLKLEN : CBLKLEN
bits : 0 - 15 (16 bit)
access : read-write
CBLKCNT : CBLKCNT
bits : 16 - 47 (32 bit)
access : read-write
PDMA_CH3CR
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : CHEN
bits : 0 - 0 (1 bit)
access : read-write
SWTRIG : SWTRIG
bits : 1 - 2 (2 bit)
access : read-write
DWIDTH : DWIDTH
bits : 2 - 5 (4 bit)
access : read-write
DSTAINC : DSTAINC
bits : 4 - 8 (5 bit)
access : read-write
DSTAMOD : DSTAMOD
bits : 5 - 10 (6 bit)
access : read-write
SRCAINC : SRCAINC
bits : 6 - 12 (7 bit)
access : read-write
SRCAMOD : SRCAMOD
bits : 7 - 14 (8 bit)
access : read-write
CHPRI : CHPRI
bits : 8 - 17 (10 bit)
access : read-write
FIXAEN : FIXAEN
bits : 10 - 20 (11 bit)
access : read-write
AUTORL : AUTORL
bits : 11 - 22 (12 bit)
access : read-write
PDMA_CH3SADR
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : SADR
bits : 0 - 31 (32 bit)
access : read-write
PDMA_CH3DADR
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADR : DADR
bits : 0 - 31 (32 bit)
access : read-write
PDMA_CH3TSR
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLKLEN : BLKLEN
bits : 0 - 7 (8 bit)
access : read-write
BLKCNT : BLKCNT
bits : 16 - 47 (32 bit)
access : read-write
PDMA_CH3CTSR
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBLKLEN : CBLKLEN
bits : 0 - 15 (16 bit)
access : read-write
CBLKCNT : CBLKCNT
bits : 16 - 47 (32 bit)
access : read-write
PDMA_CH4CR
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : CHEN
bits : 0 - 0 (1 bit)
access : read-write
SWTRIG : SWTRIG
bits : 1 - 2 (2 bit)
access : read-write
DWIDTH : DWIDTH
bits : 2 - 5 (4 bit)
access : read-write
DSTAINC : DSTAINC
bits : 4 - 8 (5 bit)
access : read-write
DSTAMOD : DSTAMOD
bits : 5 - 10 (6 bit)
access : read-write
SRCAINC : SRCAINC
bits : 6 - 12 (7 bit)
access : read-write
SRCAMOD : SRCAMOD
bits : 7 - 14 (8 bit)
access : read-write
CHPRI : CHPRI
bits : 8 - 17 (10 bit)
access : read-write
FIXAEN : FIXAEN
bits : 10 - 20 (11 bit)
access : read-write
AUTORL : AUTORL
bits : 11 - 22 (12 bit)
access : read-write
PDMA_CH4SADR
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : SADR
bits : 0 - 31 (32 bit)
access : read-write
PDMA_CH4DADR
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADR : DADR
bits : 0 - 31 (32 bit)
access : read-write
PDMA_CH4TSR
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLKLEN : BLKLEN
bits : 0 - 7 (8 bit)
access : read-write
BLKCNT : BLKCNT
bits : 16 - 47 (32 bit)
access : read-write
PDMA_CH4CTSR
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBLKLEN : CBLKLEN
bits : 0 - 15 (16 bit)
access : read-write
CBLKCNT : CBLKCNT
bits : 16 - 47 (32 bit)
access : read-write
PDMA_CH5CR
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : CHEN
bits : 0 - 0 (1 bit)
access : read-write
SWTRIG : SWTRIG
bits : 1 - 2 (2 bit)
access : read-write
DWIDTH : DWIDTH
bits : 2 - 5 (4 bit)
access : read-write
DSTAINC : DSTAINC
bits : 4 - 8 (5 bit)
access : read-write
DSTAMOD : DSTAMOD
bits : 5 - 10 (6 bit)
access : read-write
SRCAINC : SRCAINC
bits : 6 - 12 (7 bit)
access : read-write
SRCAMOD : SRCAMOD
bits : 7 - 14 (8 bit)
access : read-write
CHPRI : CHPRI
bits : 8 - 17 (10 bit)
access : read-write
FIXAEN : FIXAEN
bits : 10 - 20 (11 bit)
access : read-write
AUTORL : AUTORL
bits : 11 - 22 (12 bit)
access : read-write
PDMA_CH5SADR
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : SADR
bits : 0 - 31 (32 bit)
access : read-write
PDMA_CH0DADR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADR : DADR
bits : 0 - 31 (32 bit)
access : read-write
PDMA_CH5DADR
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADR : DADR
bits : 0 - 31 (32 bit)
access : read-write
PDMA_CH5TSR
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLKLEN : BLKLEN
bits : 0 - 7 (8 bit)
access : read-write
BLKCNT : BLKCNT
bits : 16 - 47 (32 bit)
access : read-write
PDMA_CH5CTSR
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBLKLEN : CBLKLEN
bits : 0 - 15 (16 bit)
access : read-write
CBLKCNT : CBLKCNT
bits : 16 - 47 (32 bit)
access : read-write
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