\n

ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xB1 byte (0x0)
mem_usage : registers
protection : not protected

Registers

STR

CHSELRB0

EXCHSELR

CR0

SSTR

CR1

ISR

ICR

ISCLRR

DR0

DR1

DR2

DR3

DR4

DR5

DR6

DR7

DR8

DR9

DR10

DR11

TRGSR

AWDCR

AWDSR

AWDSCLRR

AWD0DR0

AWD0DR1

AWD0CHSR

AWD1DR0

AWD1DR1

AWD1CHSR

CHSELRA0


STR

desc STR
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STR STR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STRT

STRT : desc STRT
bits : 0 - -1 (0 bit)
access : read-write


CHSELRB0

desc CHSELRB0
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSELRB0 CHSELRB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSELB

CHSELB : desc CHSELB
bits : 0 - 10 (11 bit)
access : read-write


EXCHSELR

desc EXCHSELR
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXCHSELR EXCHSELR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EXCHSEL

EXCHSEL : desc EXCHSEL
bits : 0 - -1 (0 bit)
access : read-write


CR0

desc CR0
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MS ACCSEL CLREN DFMT

MS : desc MS
bits : 0 - 0 (1 bit)
access : read-write

ACCSEL : desc ACCSEL
bits : 4 - 4 (1 bit)
access : read-write

CLREN : desc CLREN
bits : 6 - 5 (0 bit)
access : read-write

DFMT : desc DFMT
bits : 7 - 6 (0 bit)
access : read-write


SSTR

desc SSTR
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSTR SSTR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CR1

desc CR1
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSCHSEL

RSCHSEL : desc RSCHSEL
bits : 2 - 1 (0 bit)
access : read-write


ISR

desc ISR
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EOCAF EOCBF

EOCAF : desc EOCAF
bits : 0 - -1 (0 bit)
access : read-only

EOCBF : desc EOCBF
bits : 1 - 0 (0 bit)
access : read-only


ICR

desc ICR
address_offset : 0x45 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICR ICR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EOCAIEN EOCBIEN

EOCAIEN : desc EOCAIEN
bits : 0 - -1 (0 bit)
access : read-write

EOCBIEN : desc EOCBIEN
bits : 1 - 0 (0 bit)
access : read-write


ISCLRR

desc ISCLRR
address_offset : 0x46 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ISCLRR ISCLRR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CLREOCAF CLREOCBF

CLREOCAF : desc CLREOCAF
bits : 0 - -1 (0 bit)
access : write-only

CLREOCBF : desc CLREOCBF
bits : 1 - 0 (0 bit)
access : write-only


DR0

desc DR0
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR0 DR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR1

desc DR1
address_offset : 0x52 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR1 DR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR2

desc DR2
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR2 DR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR3

desc DR3
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR3 DR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR4

desc DR4
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR4 DR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR5

desc DR5
address_offset : 0x5A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR5 DR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR6

desc DR6
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR6 DR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR7

desc DR7
address_offset : 0x5E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR7 DR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR8

desc DR8
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR8 DR8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR9

desc DR9
address_offset : 0x62 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR9 DR9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR10

desc DR10
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR10 DR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR11

desc DR11
address_offset : 0x66 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR11 DR11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRGSR

desc TRGSR
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGSR TRGSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGSELA TRGENA TRGSELB TRGENB

TRGSELA : desc TRGSELA
bits : 0 - 0 (1 bit)
access : read-write

TRGENA : desc TRGENA
bits : 7 - 6 (0 bit)
access : read-write

TRGSELB : desc TRGSELB
bits : 8 - 8 (1 bit)
access : read-write

TRGENB : desc TRGENB
bits : 15 - 14 (0 bit)
access : read-write


AWDCR

desc AWDCR
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWDCR AWDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD0EN AWD0IEN AWD0MD AWD1EN AWD1IEN AWD1MD AWDCM

AWD0EN : desc AWD0EN
bits : 0 - -1 (0 bit)
access : read-write

AWD0IEN : desc AWD0IEN
bits : 1 - 0 (0 bit)
access : read-write

AWD0MD : desc AWD0MD
bits : 2 - 1 (0 bit)
access : read-write

AWD1EN : desc AWD1EN
bits : 4 - 3 (0 bit)
access : read-write

AWD1IEN : desc AWD1IEN
bits : 5 - 4 (0 bit)
access : read-write

AWD1MD : desc AWD1MD
bits : 6 - 5 (0 bit)
access : read-write

AWDCM : desc AWDCM
bits : 8 - 8 (1 bit)
access : read-write


AWDSR

desc AWDSR
address_offset : 0xA2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AWDSR AWDSR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AWD0F AWD1F AWDCMF

AWD0F : desc AWD0F
bits : 0 - -1 (0 bit)
access : read-only

AWD1F : desc AWD1F
bits : 1 - 0 (0 bit)
access : read-only

AWDCMF : desc AWDCMF
bits : 4 - 3 (0 bit)
access : read-only


AWDSCLRR

desc AWDSCLRR
address_offset : 0xA3 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AWDSCLRR AWDSCLRR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CLRAWD0F CLRAWD1F CLRAWDCMF

CLRAWD0F : desc CLRAWD0F
bits : 0 - -1 (0 bit)
access : write-only

CLRAWD1F : desc CLRAWD1F
bits : 1 - 0 (0 bit)
access : write-only

CLRAWDCMF : desc CLRAWDCMF
bits : 4 - 3 (0 bit)
access : write-only


AWD0DR0

desc AWD0DR0
address_offset : 0xA4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD0DR0 AWD0DR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AWD0DR1

desc AWD0DR1
address_offset : 0xA6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD0DR1 AWD0DR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AWD0CHSR

desc AWD0CHSR
address_offset : 0xA8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD0CHSR AWD0CHSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AWDCH

AWDCH : desc AWDCH
bits : 0 - 3 (4 bit)
access : read-write


AWD1DR0

desc AWD1DR0
address_offset : 0xAC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD1DR0 AWD1DR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AWD1DR1

desc AWD1DR1
address_offset : 0xAE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD1DR1 AWD1DR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AWD1CHSR

desc AWD1CHSR
address_offset : 0xB0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD1CHSR AWD1CHSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AWDCH

AWDCH : desc AWDCH
bits : 0 - 3 (4 bit)
access : read-write


CHSELRA0

desc CHSELRA0
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSELRA0 CHSELRA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSELA

CHSELA : desc CHSELA
bits : 0 - 10 (11 bit)
access : read-write



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