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USART1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SR

CR2

CR3

PR

DR

BRR

CR1


SR

desc SR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE FE ORE RXNE TC TXE MPB

PE : desc PE
bits : 0 - -1 (0 bit)
access : read-only

FE : desc FE
bits : 1 - 0 (0 bit)
access : read-only

ORE : desc ORE
bits : 3 - 2 (0 bit)
access : read-only

RXNE : desc RXNE
bits : 5 - 4 (0 bit)
access : read-only

TC : desc TC
bits : 6 - 5 (0 bit)
access : read-only

TXE : desc TXE
bits : 7 - 6 (0 bit)
access : read-only

MPB : desc MPB
bits : 16 - 15 (0 bit)
access : read-only


CR2

desc CR2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPE CLKC STOP LINEN

MPE : desc MPE
bits : 0 - -1 (0 bit)
access : read-write

CLKC : desc CLKC
bits : 11 - 11 (1 bit)
access : read-write

STOP : desc STOP
bits : 13 - 12 (0 bit)
access : read-write

LINEN : desc LINEN
bits : 14 - 13 (0 bit)
access : read-write


CR3

desc CR3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR3 CR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HDSEL CTSE

HDSEL : desc HDSEL
bits : 3 - 2 (0 bit)
access : read-write

CTSE : desc CTSE
bits : 9 - 8 (0 bit)
access : read-write


PR

desc PR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PR PR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : desc PSC
bits : 0 - 0 (1 bit)
access : read-write


DR

desc DR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDR MPID RDR

TDR : desc TDR
bits : 0 - 7 (8 bit)
access : read-write

MPID : desc MPID
bits : 9 - 8 (0 bit)
access : read-write

RDR : desc RDR
bits : 16 - 23 (8 bit)
access : read-write


BRR

desc BRR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRR BRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_INTEGER

DIV_INTEGER : desc DIV_INTEGER
bits : 8 - 14 (7 bit)
access : read-write


CR1

desc CR1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RE TE SLME RIE TCIE TXEIE PS PCE M OVER8 CPE CFE CORE MS ML NFE SBS

RE : desc RE
bits : 2 - 1 (0 bit)
access : read-write

TE : desc TE
bits : 3 - 2 (0 bit)
access : read-write

SLME : desc SLME
bits : 4 - 3 (0 bit)
access : read-write

RIE : desc RIE
bits : 5 - 4 (0 bit)
access : read-write

TCIE : desc TCIE
bits : 6 - 5 (0 bit)
access : read-write

TXEIE : desc TXEIE
bits : 7 - 6 (0 bit)
access : read-write

PS : desc PS
bits : 9 - 8 (0 bit)
access : read-write

PCE : desc PCE
bits : 10 - 9 (0 bit)
access : read-write

M : desc M
bits : 12 - 11 (0 bit)
access : read-write

OVER8 : desc OVER8
bits : 15 - 14 (0 bit)
access : read-write

CPE : desc CPE
bits : 16 - 15 (0 bit)
access : write-only

CFE : desc CFE
bits : 17 - 16 (0 bit)
access : write-only

CORE : desc CORE
bits : 19 - 18 (0 bit)
access : write-only

MS : desc MS
bits : 24 - 23 (0 bit)
access : read-write

ML : desc ML
bits : 28 - 27 (0 bit)
access : read-write

NFE : desc NFE
bits : 30 - 29 (0 bit)
access : read-write

SBS : desc SBS
bits : 31 - 30 (0 bit)
access : read-write



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