\n
address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected
desc INTC_STRGCR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
STRG : desc STRG
bits : 0 - -1 (0 bit)
access : write-only
desc TMR0_HTSSR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write
desc TMR2_HTSSR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write
desc EVPRT_CR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVP1FEE : desc EVP1FEE
bits : 0 - -1 (0 bit)
access : read-write
EVP2FEE : desc EVP2FEE
bits : 1 - 0 (0 bit)
access : read-write
EVP3FEE : desc EVP3FEE
bits : 2 - 1 (0 bit)
access : read-write
EVP4FEE : desc EVP4FEE
bits : 3 - 2 (0 bit)
access : read-write
EVP1REE : desc EVP1REE
bits : 4 - 3 (0 bit)
access : read-write
EVP2REE : desc EVP2REE
bits : 5 - 4 (0 bit)
access : read-write
EVP3REE : desc EVP3REE
bits : 6 - 5 (0 bit)
access : read-write
EVP4REE : desc EVP4REE
bits : 7 - 6 (0 bit)
access : read-write
EVPDIVS : desc EVPDIVS
bits : 8 - 8 (1 bit)
access : read-write
EVPNFE : desc EVPNFE
bits : 10 - 9 (0 bit)
access : read-write
desc TMRA_HTSSR
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write
desc TMRB_HTSSR
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write
desc ADC_ITRGSELR0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write
desc ADC_ITRGSELR1
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write
desc EVPRT_SR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PTSTS0 : desc PTSTS0
bits : 0 - 2 (3 bit)
access : read-only
PTSTS1 : desc PTSTS1
bits : 4 - 6 (3 bit)
access : read-only
PTSTS2 : desc PTSTS2
bits : 8 - 10 (3 bit)
access : read-only
PTSTS3 : desc PTSTS3
bits : 12 - 14 (3 bit)
access : read-only
desc DMA0_TRGSEL
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write
desc DMA1_TRGSEL
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write
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