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AOS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected

Registers

INTC_STRGCR

TMR0_HTSSR

TMR2_HTSSR

EVPRT_CR

TMRA_HTSSR

TMRB_HTSSR

ADC_ITRGSELR0

ADC_ITRGSELR1

EVPRT_SR

DMA0_TRGSEL

DMA1_TRGSEL


INTC_STRGCR

desc INTC_STRGCR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INTC_STRGCR INTC_STRGCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRG

STRG : desc STRG
bits : 0 - -1 (0 bit)
access : write-only


TMR0_HTSSR

desc TMR0_HTSSR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR0_HTSSR TMR0_HTSSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGSEL

TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write


TMR2_HTSSR

desc TMR2_HTSSR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR2_HTSSR TMR2_HTSSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGSEL

TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write


EVPRT_CR

desc EVPRT_CR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVPRT_CR EVPRT_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVP1FEE EVP2FEE EVP3FEE EVP4FEE EVP1REE EVP2REE EVP3REE EVP4REE EVPDIVS EVPNFE

EVP1FEE : desc EVP1FEE
bits : 0 - -1 (0 bit)
access : read-write

EVP2FEE : desc EVP2FEE
bits : 1 - 0 (0 bit)
access : read-write

EVP3FEE : desc EVP3FEE
bits : 2 - 1 (0 bit)
access : read-write

EVP4FEE : desc EVP4FEE
bits : 3 - 2 (0 bit)
access : read-write

EVP1REE : desc EVP1REE
bits : 4 - 3 (0 bit)
access : read-write

EVP2REE : desc EVP2REE
bits : 5 - 4 (0 bit)
access : read-write

EVP3REE : desc EVP3REE
bits : 6 - 5 (0 bit)
access : read-write

EVP4REE : desc EVP4REE
bits : 7 - 6 (0 bit)
access : read-write

EVPDIVS : desc EVPDIVS
bits : 8 - 8 (1 bit)
access : read-write

EVPNFE : desc EVPNFE
bits : 10 - 9 (0 bit)
access : read-write


TMRA_HTSSR

desc TMRA_HTSSR
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMRA_HTSSR TMRA_HTSSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGSEL

TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write


TMRB_HTSSR

desc TMRB_HTSSR
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMRB_HTSSR TMRB_HTSSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGSEL

TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write


ADC_ITRGSELR0

desc ADC_ITRGSELR0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_ITRGSELR0 ADC_ITRGSELR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGSEL

TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write


ADC_ITRGSELR1

desc ADC_ITRGSELR1
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_ITRGSELR1 ADC_ITRGSELR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGSEL

TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write


EVPRT_SR

desc EVPRT_SR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EVPRT_SR EVPRT_SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTSTS0 PTSTS1 PTSTS2 PTSTS3

PTSTS0 : desc PTSTS0
bits : 0 - 2 (3 bit)
access : read-only

PTSTS1 : desc PTSTS1
bits : 4 - 6 (3 bit)
access : read-only

PTSTS2 : desc PTSTS2
bits : 8 - 10 (3 bit)
access : read-only

PTSTS3 : desc PTSTS3
bits : 12 - 14 (3 bit)
access : read-only


DMA0_TRGSEL

desc DMA0_TRGSEL
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA0_TRGSEL DMA0_TRGSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGSEL

TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write


DMA1_TRGSEL

desc DMA1_TRGSEL
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA1_TRGSEL DMA1_TRGSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGSEL

TRGSEL : desc TRGSEL
bits : 0 - 5 (6 bit)
access : read-write



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