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CMP1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x6 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MDR

FIR

OCR

VSR

TWR1

TWR2


MDR

desc MDR
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDR MDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CENB CWDE CMON

CENB : desc CENB
bits : 0 - -1 (0 bit)
access : read-write

CWDE : desc CWDE
bits : 1 - 0 (0 bit)
access : read-write

CMON : desc CMON
bits : 7 - 6 (0 bit)
access : read-only


FIR

desc FIR
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIR FIR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FCKS EDGS CIEN

FCKS : desc FCKS
bits : 0 - 0 (1 bit)
access : read-write

EDGS : desc EDGS
bits : 4 - 4 (1 bit)
access : read-write

CIEN : desc CIEN
bits : 6 - 5 (0 bit)
access : read-write


OCR

desc OCR
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCR OCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 COEN COPS CPOE TWOE TWOL

COEN : desc COEN
bits : 0 - -1 (0 bit)
access : read-write

COPS : desc COPS
bits : 1 - 0 (0 bit)
access : read-write

CPOE : desc CPOE
bits : 2 - 1 (0 bit)
access : read-write

TWOE : desc TWOE
bits : 3 - 2 (0 bit)
access : read-write

TWOL : desc TWOL
bits : 4 - 3 (0 bit)
access : read-write


VSR

desc VSR
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VSR VSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RVSL CVSL

RVSL : desc RVSL
bits : 0 - 1 (2 bit)
access : read-write

CVSL : desc CVSL
bits : 4 - 5 (2 bit)
access : read-write


TWR1

desc TWR1
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWR1 TWR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CTWS0 CTWS1 CTWS2 CTWS3 CTWS4 CTWS5 CTWS6 CTWS7

CTWS0 : desc CTWS0
bits : 0 - -1 (0 bit)
access : read-write

CTWS1 : desc CTWS1
bits : 1 - 0 (0 bit)
access : read-write

CTWS2 : desc CTWS2
bits : 2 - 1 (0 bit)
access : read-write

CTWS3 : desc CTWS3
bits : 3 - 2 (0 bit)
access : read-write

CTWS4 : desc CTWS4
bits : 4 - 3 (0 bit)
access : read-write

CTWS5 : desc CTWS5
bits : 5 - 4 (0 bit)
access : read-write

CTWS6 : desc CTWS6
bits : 6 - 5 (0 bit)
access : read-write

CTWS7 : desc CTWS7
bits : 7 - 6 (0 bit)
access : read-write


TWR2

desc TWR2
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWR2 TWR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CTWP0 CTWP1 CTWP2 CTWP3 CTWP4 CTWP5 CTWP6 CTWP7

CTWP0 : desc CTWP0
bits : 0 - -1 (0 bit)
access : read-write

CTWP1 : desc CTWP1
bits : 1 - 0 (0 bit)
access : read-write

CTWP2 : desc CTWP2
bits : 2 - 1 (0 bit)
access : read-write

CTWP3 : desc CTWP3
bits : 3 - 2 (0 bit)
access : read-write

CTWP4 : desc CTWP4
bits : 4 - 3 (0 bit)
access : read-write

CTWP5 : desc CTWP5
bits : 5 - 4 (0 bit)
access : read-write

CTWP6 : desc CTWP6
bits : 6 - 5 (0 bit)
access : read-write

CTWP7 : desc CTWP7
bits : 7 - 6 (0 bit)
access : read-write



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