\n

DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EN

INTMASK1

INTCLR0

INTCLR1

CHEN

CHSTAT

CHENCLR

INTSTAT0

SAR0

DAR0

CH0CTL0

CH0CTL1

INTSTAT1

SAR1

DAR1

CH1CTL0

CH1CTL1

INTMASK0


EN

desc EN
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : desc EN
bits : 0 - -1 (0 bit)
access : read-write


INTMASK1

desc INTMASK1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTMASK1 INTMASK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSKTC MSKBTC

MSKTC : desc MSKTC
bits : 0 - 0 (1 bit)
access : read-write

MSKBTC : desc MSKBTC
bits : 16 - 16 (1 bit)
access : read-write


INTCLR0

desc INTCLR0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INTCLR0 INTCLR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRTRNERR CLRREQERR

CLRTRNERR : desc CLRTRNERR
bits : 0 - 0 (1 bit)
access : write-only

CLRREQERR : desc CLRREQERR
bits : 16 - 16 (1 bit)
access : write-only


INTCLR1

desc INTCLR1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INTCLR1 INTCLR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRTC CLRBTC

CLRTC : desc CLRTC
bits : 0 - 0 (1 bit)
access : write-only

CLRBTC : desc CLRBTC
bits : 16 - 16 (1 bit)
access : write-only


CHEN

desc CHEN
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEN CHEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN

CHEN : desc CHEN
bits : 0 - 0 (1 bit)
access : read-write


CHSTAT

desc CHSTAT
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTAT CHSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAACT CHACT

DMAACT : desc DMAACT
bits : 0 - -1 (0 bit)
access : read-only

CHACT : desc CHACT
bits : 16 - 16 (1 bit)
access : read-only


CHENCLR

desc CHENCLR
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHENCLR CHENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHENCLR

CHENCLR : desc CHENCLR
bits : 0 - 0 (1 bit)
access : read-write


INTSTAT0

desc INTSTAT0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTAT0 INTSTAT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRNERR REQERR

TRNERR : desc TRNERR
bits : 0 - 0 (1 bit)
access : read-only

REQERR : desc REQERR
bits : 16 - 16 (1 bit)
access : read-only


SAR0

desc SAR0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAR0 SAR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAR0

desc DAR0
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAR0 DAR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CH0CTL0

desc CH0CTL0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CTL0 CH0CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLKSIZE CNT LLP LLPEN LLPRUN HSIZE

BLKSIZE : desc BLKSIZE
bits : 0 - 6 (7 bit)
access : read-write

CNT : desc CNT
bits : 8 - 16 (9 bit)
access : read-write

LLP : desc LLP
bits : 18 - 26 (9 bit)
access : read-write

LLPEN : desc LLPEN
bits : 28 - 27 (0 bit)
access : read-write

LLPRUN : desc LLPRUN
bits : 29 - 28 (0 bit)
access : read-write

HSIZE : desc HSIZE
bits : 30 - 30 (1 bit)
access : read-write


CH0CTL1

desc CH0CTL1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CTL1 CH0CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET RPTNSCNT RPTNSEN RPTNSSEL SINC DINC

OFFSET : desc OFFSET
bits : 0 - 14 (15 bit)
access : read-write

RPTNSCNT : desc RPTNSCNT
bits : 16 - 22 (7 bit)
access : read-write

RPTNSEN : desc RPTNSEN
bits : 24 - 23 (0 bit)
access : read-write

RPTNSSEL : desc RPTNSSEL
bits : 25 - 25 (1 bit)
access : read-write

SINC : desc SINC
bits : 28 - 28 (1 bit)
access : read-write

DINC : desc DINC
bits : 30 - 30 (1 bit)
access : read-write


INTSTAT1

desc INTSTAT1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTAT1 INTSTAT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC BTC

TC : desc TC
bits : 0 - 0 (1 bit)
access : read-only

BTC : desc BTC
bits : 16 - 16 (1 bit)
access : read-only


SAR1

desc SAR1
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAR1 SAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAR1

desc DAR1
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAR1 DAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CH1CTL0

desc CH1CTL0
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CTL0 CH1CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLKSIZE CNT LLP LLPEN LLPRUN HSIZE

BLKSIZE : desc BLKSIZE
bits : 0 - 6 (7 bit)
access : read-write

CNT : desc CNT
bits : 8 - 16 (9 bit)
access : read-write

LLP : desc LLP
bits : 18 - 26 (9 bit)
access : read-write

LLPEN : desc LLPEN
bits : 28 - 27 (0 bit)
access : read-write

LLPRUN : desc LLPRUN
bits : 29 - 28 (0 bit)
access : read-write

HSIZE : desc HSIZE
bits : 30 - 30 (1 bit)
access : read-write


CH1CTL1

desc CH1CTL1
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CTL1 CH1CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET RPTNSCNT RPTNSEN RPTNSSEL SINC DINC

OFFSET : desc OFFSET
bits : 0 - 14 (15 bit)
access : read-write

RPTNSCNT : desc RPTNSCNT
bits : 16 - 22 (7 bit)
access : read-write

RPTNSEN : desc RPTNSEN
bits : 24 - 23 (0 bit)
access : read-write

RPTNSSEL : desc RPTNSSEL
bits : 25 - 25 (1 bit)
access : read-write

SINC : desc SINC
bits : 28 - 28 (1 bit)
access : read-write

DINC : desc DINC
bits : 30 - 30 (1 bit)
access : read-write


INTMASK0

desc INTMASK0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTMASK0 INTMASK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSKTRNERR MSKREQERR

MSKTRNERR : desc MSKTRNERR
bits : 0 - 0 (1 bit)
access : read-write

MSKREQERR : desc MSKREQERR
bits : 16 - 16 (1 bit)
access : read-write



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