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TMR4

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x41C byte (0x0)
mem_usage : registers
protection : not protected

Registers

OCCRWH

OCCRWL

OCSRU

OCERU

OCSRV

OCERV

OCCRUH

OCSRW

OCERW

OCMRHUH

OCMRLUL

OCMRHVH

OCMRLVL

OCMRHWH

OCMRLWL

ECSR

CPSR

CNTR

CCSR

CVPR

OCCRUL

PFSRU

PDARU

PDBRU

PFSRV

PDARV

PDBRV

PFSRW

PDARW

PDBRW

POCRU

POCRV

OCCRVH

POCRW

RCSR

SCCRUH

SCCRUL

SCCRVH

SCCRVL

SCCRWH

SCCRWL

SCSRUH

SCMRUH

SCSRUL

SCMRUL

SCSRVH

SCMRVH

SCSRVL

SCMRVL

SCSRWH

SCMRWH

SCSRWL

SCMRWL

OCCRVL


OCCRWH

desc OCCRWH
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCCRWH OCCRWH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCCRWL

desc OCCRWL
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCCRWL OCCRWL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCSRU

desc OCSRU
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCSRU OCSRU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCEH OCEL OCPH OCPL OCIEH OCIEL OCFH OCFL

OCEH : desc OCEH
bits : 0 - -1 (0 bit)
access : read-write

OCEL : desc OCEL
bits : 1 - 0 (0 bit)
access : read-write

OCPH : desc OCPH
bits : 2 - 1 (0 bit)
access : read-write

OCPL : desc OCPL
bits : 3 - 2 (0 bit)
access : read-write

OCIEH : desc OCIEH
bits : 4 - 3 (0 bit)
access : read-write

OCIEL : desc OCIEL
bits : 5 - 4 (0 bit)
access : read-write

OCFH : desc OCFH
bits : 6 - 5 (0 bit)
access : read-write

OCFL : desc OCFL
bits : 7 - 6 (0 bit)
access : read-write


OCERU

desc OCERU
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCERU OCERU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHBUFEN CLBUFEN MHBUFEN MLBUFEN LMCH LMCL LMMH LMML MCECH MCECL

CHBUFEN : desc CHBUFEN
bits : 0 - 0 (1 bit)
access : read-write

CLBUFEN : desc CLBUFEN
bits : 2 - 2 (1 bit)
access : read-write

MHBUFEN : desc MHBUFEN
bits : 4 - 4 (1 bit)
access : read-write

MLBUFEN : desc MLBUFEN
bits : 6 - 6 (1 bit)
access : read-write

LMCH : desc LMCH
bits : 8 - 7 (0 bit)
access : read-write

LMCL : desc LMCL
bits : 9 - 8 (0 bit)
access : read-write

LMMH : desc LMMH
bits : 10 - 9 (0 bit)
access : read-write

LMML : desc LMML
bits : 11 - 10 (0 bit)
access : read-write

MCECH : desc MCECH
bits : 12 - 11 (0 bit)
access : read-write

MCECL : desc MCECL
bits : 13 - 12 (0 bit)
access : read-write


OCSRV

desc OCSRV
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCSRV OCSRV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCEH OCEL OCPH OCPL OCIEH OCIEL OCFH OCFL

OCEH : desc OCEH
bits : 0 - -1 (0 bit)
access : read-write

OCEL : desc OCEL
bits : 1 - 0 (0 bit)
access : read-write

OCPH : desc OCPH
bits : 2 - 1 (0 bit)
access : read-write

OCPL : desc OCPL
bits : 3 - 2 (0 bit)
access : read-write

OCIEH : desc OCIEH
bits : 4 - 3 (0 bit)
access : read-write

OCIEL : desc OCIEL
bits : 5 - 4 (0 bit)
access : read-write

OCFH : desc OCFH
bits : 6 - 5 (0 bit)
access : read-write

OCFL : desc OCFL
bits : 7 - 6 (0 bit)
access : read-write


OCERV

desc OCERV
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCERV OCERV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHBUFEN CLBUFEN MHBUFEN MLBUFEN LMCH LMCL LMMH LMML MCECH MCECL

CHBUFEN : desc CHBUFEN
bits : 0 - 0 (1 bit)
access : read-write

CLBUFEN : desc CLBUFEN
bits : 2 - 2 (1 bit)
access : read-write

MHBUFEN : desc MHBUFEN
bits : 4 - 4 (1 bit)
access : read-write

MLBUFEN : desc MLBUFEN
bits : 6 - 6 (1 bit)
access : read-write

LMCH : desc LMCH
bits : 8 - 7 (0 bit)
access : read-write

LMCL : desc LMCL
bits : 9 - 8 (0 bit)
access : read-write

LMMH : desc LMMH
bits : 10 - 9 (0 bit)
access : read-write

LMML : desc LMML
bits : 11 - 10 (0 bit)
access : read-write

MCECH : desc MCECH
bits : 12 - 11 (0 bit)
access : read-write

MCECL : desc MCECL
bits : 13 - 12 (0 bit)
access : read-write


OCCRUH

desc OCCRUH
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCCRUH OCCRUH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCSRW

desc OCSRW
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCSRW OCSRW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCEH OCEL OCPH OCPL OCIEH OCIEL OCFH OCFL

OCEH : desc OCEH
bits : 0 - -1 (0 bit)
access : read-write

OCEL : desc OCEL
bits : 1 - 0 (0 bit)
access : read-write

OCPH : desc OCPH
bits : 2 - 1 (0 bit)
access : read-write

OCPL : desc OCPL
bits : 3 - 2 (0 bit)
access : read-write

OCIEH : desc OCIEH
bits : 4 - 3 (0 bit)
access : read-write

OCIEL : desc OCIEL
bits : 5 - 4 (0 bit)
access : read-write

OCFH : desc OCFH
bits : 6 - 5 (0 bit)
access : read-write

OCFL : desc OCFL
bits : 7 - 6 (0 bit)
access : read-write


OCERW

desc OCERW
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCERW OCERW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHBUFEN CLBUFEN MHBUFEN MLBUFEN LMCH LMCL LMMH LMML MCECH MCECL

CHBUFEN : desc CHBUFEN
bits : 0 - 0 (1 bit)
access : read-write

CLBUFEN : desc CLBUFEN
bits : 2 - 2 (1 bit)
access : read-write

MHBUFEN : desc MHBUFEN
bits : 4 - 4 (1 bit)
access : read-write

MLBUFEN : desc MLBUFEN
bits : 6 - 6 (1 bit)
access : read-write

LMCH : desc LMCH
bits : 8 - 7 (0 bit)
access : read-write

LMCL : desc LMCL
bits : 9 - 8 (0 bit)
access : read-write

LMMH : desc LMMH
bits : 10 - 9 (0 bit)
access : read-write

LMML : desc LMML
bits : 11 - 10 (0 bit)
access : read-write

MCECH : desc MCECH
bits : 12 - 11 (0 bit)
access : read-write

MCECL : desc MCECL
bits : 13 - 12 (0 bit)
access : read-write


OCMRHUH

desc OCMRHUH
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCMRHUH OCMRHUH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCFDCH OCFPKH OCFUCH OCFZRH OPDCH OPPKH OPUCH OPZRH OPNPKH OPNZRH

OCFDCH : desc OCFDCH
bits : 0 - -1 (0 bit)
access : read-write

OCFPKH : desc OCFPKH
bits : 1 - 0 (0 bit)
access : read-write

OCFUCH : desc OCFUCH
bits : 2 - 1 (0 bit)
access : read-write

OCFZRH : desc OCFZRH
bits : 3 - 2 (0 bit)
access : read-write

OPDCH : desc OPDCH
bits : 4 - 4 (1 bit)
access : read-write

OPPKH : desc OPPKH
bits : 6 - 6 (1 bit)
access : read-write

OPUCH : desc OPUCH
bits : 8 - 8 (1 bit)
access : read-write

OPZRH : desc OPZRH
bits : 10 - 10 (1 bit)
access : read-write

OPNPKH : desc OPNPKH
bits : 12 - 12 (1 bit)
access : read-write

OPNZRH : desc OPNZRH
bits : 14 - 14 (1 bit)
access : read-write


OCMRLUL

desc OCMRLUL
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCMRLUL OCMRLUL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCFDCL OCFPKL OCFUCL OCFZRL OPDCL OPPKL OPUCL OPZRL OPNPKL OPNZRL EOPNDCL EOPNUCL EOPDCL EOPPKL EOPUCL EOPZRL EOPNPKL EOPNZRL

OCFDCL : desc OCFDCL
bits : 0 - -1 (0 bit)
access : read-write

OCFPKL : desc OCFPKL
bits : 1 - 0 (0 bit)
access : read-write

OCFUCL : desc OCFUCL
bits : 2 - 1 (0 bit)
access : read-write

OCFZRL : desc OCFZRL
bits : 3 - 2 (0 bit)
access : read-write

OPDCL : desc OPDCL
bits : 4 - 4 (1 bit)
access : read-write

OPPKL : desc OPPKL
bits : 6 - 6 (1 bit)
access : read-write

OPUCL : desc OPUCL
bits : 8 - 8 (1 bit)
access : read-write

OPZRL : desc OPZRL
bits : 10 - 10 (1 bit)
access : read-write

OPNPKL : desc OPNPKL
bits : 12 - 12 (1 bit)
access : read-write

OPNZRL : desc OPNZRL
bits : 14 - 14 (1 bit)
access : read-write

EOPNDCL : desc EOPNDCL
bits : 16 - 16 (1 bit)
access : read-write

EOPNUCL : desc EOPNUCL
bits : 18 - 18 (1 bit)
access : read-write

EOPDCL : desc EOPDCL
bits : 20 - 20 (1 bit)
access : read-write

EOPPKL : desc EOPPKL
bits : 22 - 22 (1 bit)
access : read-write

EOPUCL : desc EOPUCL
bits : 24 - 24 (1 bit)
access : read-write

EOPZRL : desc EOPZRL
bits : 26 - 26 (1 bit)
access : read-write

EOPNPKL : desc EOPNPKL
bits : 28 - 28 (1 bit)
access : read-write

EOPNZRL : desc EOPNZRL
bits : 30 - 30 (1 bit)
access : read-write


OCMRHVH

desc OCMRHVH
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCMRHVH OCMRHVH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCFDCH OCFPKH OCFUCH OCFZRH OPDCH OPPKH OPUCH OPZRH OPNPKH OPNZRH

OCFDCH : desc OCFDCH
bits : 0 - -1 (0 bit)
access : read-write

OCFPKH : desc OCFPKH
bits : 1 - 0 (0 bit)
access : read-write

OCFUCH : desc OCFUCH
bits : 2 - 1 (0 bit)
access : read-write

OCFZRH : desc OCFZRH
bits : 3 - 2 (0 bit)
access : read-write

OPDCH : desc OPDCH
bits : 4 - 4 (1 bit)
access : read-write

OPPKH : desc OPPKH
bits : 6 - 6 (1 bit)
access : read-write

OPUCH : desc OPUCH
bits : 8 - 8 (1 bit)
access : read-write

OPZRH : desc OPZRH
bits : 10 - 10 (1 bit)
access : read-write

OPNPKH : desc OPNPKH
bits : 12 - 12 (1 bit)
access : read-write

OPNZRH : desc OPNZRH
bits : 14 - 14 (1 bit)
access : read-write


OCMRLVL

desc OCMRLVL
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCMRLVL OCMRLVL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCFDCL OCFPKL OCFUCL OCFZRL OPDCL OPPKL OPUCL OPZRL OPNPKL OPNZRL EOPNDCL EOPNUCL EOPDCL EOPPKL EOPUCL EOPZRL EOPNPKL EOPNZRL

OCFDCL : desc OCFDCL
bits : 0 - -1 (0 bit)
access : read-write

OCFPKL : desc OCFPKL
bits : 1 - 0 (0 bit)
access : read-write

OCFUCL : desc OCFUCL
bits : 2 - 1 (0 bit)
access : read-write

OCFZRL : desc OCFZRL
bits : 3 - 2 (0 bit)
access : read-write

OPDCL : desc OPDCL
bits : 4 - 4 (1 bit)
access : read-write

OPPKL : desc OPPKL
bits : 6 - 6 (1 bit)
access : read-write

OPUCL : desc OPUCL
bits : 8 - 8 (1 bit)
access : read-write

OPZRL : desc OPZRL
bits : 10 - 10 (1 bit)
access : read-write

OPNPKL : desc OPNPKL
bits : 12 - 12 (1 bit)
access : read-write

OPNZRL : desc OPNZRL
bits : 14 - 14 (1 bit)
access : read-write

EOPNDCL : desc EOPNDCL
bits : 16 - 16 (1 bit)
access : read-write

EOPNUCL : desc EOPNUCL
bits : 18 - 18 (1 bit)
access : read-write

EOPDCL : desc EOPDCL
bits : 20 - 20 (1 bit)
access : read-write

EOPPKL : desc EOPPKL
bits : 22 - 22 (1 bit)
access : read-write

EOPUCL : desc EOPUCL
bits : 24 - 24 (1 bit)
access : read-write

EOPZRL : desc EOPZRL
bits : 26 - 26 (1 bit)
access : read-write

EOPNPKL : desc EOPNPKL
bits : 28 - 28 (1 bit)
access : read-write

EOPNZRL : desc EOPNZRL
bits : 30 - 30 (1 bit)
access : read-write


OCMRHWH

desc OCMRHWH
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCMRHWH OCMRHWH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCFDCH OCFPKH OCFUCH OCFZRH OPDCH OPPKH OPUCH OPZRH OPNPKH OPNZRH

OCFDCH : desc OCFDCH
bits : 0 - -1 (0 bit)
access : read-write

OCFPKH : desc OCFPKH
bits : 1 - 0 (0 bit)
access : read-write

OCFUCH : desc OCFUCH
bits : 2 - 1 (0 bit)
access : read-write

OCFZRH : desc OCFZRH
bits : 3 - 2 (0 bit)
access : read-write

OPDCH : desc OPDCH
bits : 4 - 4 (1 bit)
access : read-write

OPPKH : desc OPPKH
bits : 6 - 6 (1 bit)
access : read-write

OPUCH : desc OPUCH
bits : 8 - 8 (1 bit)
access : read-write

OPZRH : desc OPZRH
bits : 10 - 10 (1 bit)
access : read-write

OPNPKH : desc OPNPKH
bits : 12 - 12 (1 bit)
access : read-write

OPNZRH : desc OPNZRH
bits : 14 - 14 (1 bit)
access : read-write


OCMRLWL

desc OCMRLWL
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCMRLWL OCMRLWL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCFDCL OCFPKL OCFUCL OCFZRL OPDCL OPPKL OPUCL OPZRL OPNPKL OPNZRL EOPNDCL EOPNUCL EOPDCL EOPPKL EOPUCL EOPZRL EOPNPKL EOPNZRL

OCFDCL : desc OCFDCL
bits : 0 - -1 (0 bit)
access : read-write

OCFPKL : desc OCFPKL
bits : 1 - 0 (0 bit)
access : read-write

OCFUCL : desc OCFUCL
bits : 2 - 1 (0 bit)
access : read-write

OCFZRL : desc OCFZRL
bits : 3 - 2 (0 bit)
access : read-write

OPDCL : desc OPDCL
bits : 4 - 4 (1 bit)
access : read-write

OPPKL : desc OPPKL
bits : 6 - 6 (1 bit)
access : read-write

OPUCL : desc OPUCL
bits : 8 - 8 (1 bit)
access : read-write

OPZRL : desc OPZRL
bits : 10 - 10 (1 bit)
access : read-write

OPNPKL : desc OPNPKL
bits : 12 - 12 (1 bit)
access : read-write

OPNZRL : desc OPNZRL
bits : 14 - 14 (1 bit)
access : read-write

EOPNDCL : desc EOPNDCL
bits : 16 - 16 (1 bit)
access : read-write

EOPNUCL : desc EOPNUCL
bits : 18 - 18 (1 bit)
access : read-write

EOPDCL : desc EOPDCL
bits : 20 - 20 (1 bit)
access : read-write

EOPPKL : desc EOPPKL
bits : 22 - 22 (1 bit)
access : read-write

EOPUCL : desc EOPUCL
bits : 24 - 24 (1 bit)
access : read-write

EOPZRL : desc EOPZRL
bits : 26 - 26 (1 bit)
access : read-write

EOPNPKL : desc EOPNPKL
bits : 28 - 28 (1 bit)
access : read-write

EOPNZRL : desc EOPNZRL
bits : 30 - 30 (1 bit)
access : read-write


ECSR

desc ECSR
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECSR ECSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EMBVAL

EMBVAL : desc EMBVAL
bits : 0 - 1 (2 bit)
access : read-write


CPSR

desc CPSR
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPSR CPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CNTR

desc CNTR
address_offset : 0x46 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR CNTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCSR

desc CCSR
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCSR CCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKDIV CLEAR MODE STOP BUFEN IRQPEN IRQPF IRQZEN IRQZF ECKEN

CKDIV : desc CKDIV
bits : 0 - 2 (3 bit)
access : read-write

CLEAR : desc CLEAR
bits : 4 - 3 (0 bit)
access : read-write

MODE : desc MODE
bits : 5 - 4 (0 bit)
access : read-write

STOP : desc STOP
bits : 6 - 5 (0 bit)
access : read-write

BUFEN : desc BUFEN
bits : 7 - 6 (0 bit)
access : read-write

IRQPEN : desc IRQPEN
bits : 8 - 7 (0 bit)
access : read-write

IRQPF : desc IRQPF
bits : 9 - 8 (0 bit)
access : read-write

IRQZEN : desc IRQZEN
bits : 13 - 12 (0 bit)
access : read-write

IRQZF : desc IRQZF
bits : 14 - 13 (0 bit)
access : read-write

ECKEN : desc ECKEN
bits : 15 - 14 (0 bit)
access : read-write


CVPR

desc CVPR
address_offset : 0x4A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CVPR CVPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZIM PIM ZIC PIC

ZIM : desc ZIM
bits : 0 - 2 (3 bit)
access : read-write

PIM : desc PIM
bits : 4 - 6 (3 bit)
access : read-write

ZIC : desc ZIC
bits : 8 - 10 (3 bit)
access : read-only

PIC : desc PIC
bits : 12 - 14 (3 bit)
access : read-only


OCCRUL

desc OCCRUL
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCCRUL OCCRUL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PFSRU

desc PFSRU
address_offset : 0x82 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFSRU PFSRU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDARU

desc PDARU
address_offset : 0x84 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDARU PDARU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDBRU

desc PDBRU
address_offset : 0x86 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDBRU PDBRU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PFSRV

desc PFSRV
address_offset : 0x8A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFSRV PFSRV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDARV

desc PDARV
address_offset : 0x8C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDARV PDARV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDBRV

desc PDBRV
address_offset : 0x8E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDBRV PDBRV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PFSRW

desc PFSRW
address_offset : 0x92 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFSRW PFSRW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDARW

desc PDARW
address_offset : 0x94 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDARW PDARW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDBRW

desc PDBRW
address_offset : 0x96 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDBRW PDBRW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

POCRU

desc POCRU
address_offset : 0x98 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POCRU POCRU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVCK PWMMD LVLS

DIVCK : desc DIVCK
bits : 0 - 1 (2 bit)
access : read-write

PWMMD : desc PWMMD
bits : 4 - 4 (1 bit)
access : read-write

LVLS : desc LVLS
bits : 6 - 6 (1 bit)
access : read-write


POCRV

desc POCRV
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POCRV POCRV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVCK PWMMD LVLS

DIVCK : desc DIVCK
bits : 0 - 1 (2 bit)
access : read-write

PWMMD : desc PWMMD
bits : 4 - 4 (1 bit)
access : read-write

LVLS : desc LVLS
bits : 6 - 6 (1 bit)
access : read-write


OCCRVH

desc OCCRVH
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCCRVH OCCRVH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

POCRW

desc POCRW
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POCRW POCRW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVCK PWMMD LVLS

DIVCK : desc DIVCK
bits : 0 - 1 (2 bit)
access : read-write

PWMMD : desc PWMMD
bits : 4 - 4 (1 bit)
access : read-write

LVLS : desc LVLS
bits : 6 - 6 (1 bit)
access : read-write


RCSR

desc RCSR
address_offset : 0xA4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCSR RCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTIDU RTIDV RTIDW RTIFU RTICU RTEU RTSU RTIFV RTICV RTEV RTSV RTIFW RTICW RTEW RTSW

RTIDU : desc RTIDU
bits : 0 - -1 (0 bit)
access : read-write

RTIDV : desc RTIDV
bits : 1 - 0 (0 bit)
access : read-write

RTIDW : desc RTIDW
bits : 2 - 1 (0 bit)
access : read-write

RTIFU : desc RTIFU
bits : 4 - 3 (0 bit)
access : read-only

RTICU : desc RTICU
bits : 5 - 4 (0 bit)
access : read-write

RTEU : desc RTEU
bits : 6 - 5 (0 bit)
access : read-write

RTSU : desc RTSU
bits : 7 - 6 (0 bit)
access : read-write

RTIFV : desc RTIFV
bits : 8 - 7 (0 bit)
access : read-only

RTICV : desc RTICV
bits : 9 - 8 (0 bit)
access : read-write

RTEV : desc RTEV
bits : 10 - 9 (0 bit)
access : read-write

RTSV : desc RTSV
bits : 11 - 10 (0 bit)
access : read-write

RTIFW : desc RTIFW
bits : 12 - 11 (0 bit)
access : read-only

RTICW : desc RTICW
bits : 13 - 12 (0 bit)
access : read-write

RTEW : desc RTEW
bits : 14 - 13 (0 bit)
access : read-write

RTSW : desc RTSW
bits : 15 - 14 (0 bit)
access : read-write


SCCRUH

desc SCCRUH
address_offset : 0xB2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCCRUH SCCRUH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCCRUL

desc SCCRUL
address_offset : 0xB6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCCRUL SCCRUL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCCRVH

desc SCCRVH
address_offset : 0xBA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCCRVH SCCRVH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCCRVL

desc SCCRVL
address_offset : 0xBE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCCRVL SCCRVL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCCRWH

desc SCCRWH
address_offset : 0xC2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCCRWH SCCRWH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCCRWL

desc SCCRWL
address_offset : 0xC6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCCRWL SCCRWL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCSRUH

desc SCSRUH
address_offset : 0xC8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSRUH SCSRUH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFEN EVTOS LMC EVTMS EVTDS DEN PEN UEN ZEN

BUFEN : desc BUFEN
bits : 0 - 0 (1 bit)
access : read-write

EVTOS : desc EVTOS
bits : 2 - 3 (2 bit)
access : read-write

LMC : desc LMC
bits : 5 - 4 (0 bit)
access : read-write

EVTMS : desc EVTMS
bits : 8 - 7 (0 bit)
access : read-write

EVTDS : desc EVTDS
bits : 9 - 8 (0 bit)
access : read-write

DEN : desc DEN
bits : 12 - 11 (0 bit)
access : read-write

PEN : desc PEN
bits : 13 - 12 (0 bit)
access : read-write

UEN : desc UEN
bits : 14 - 13 (0 bit)
access : read-write

ZEN : desc ZEN
bits : 15 - 14 (0 bit)
access : read-write


SCMRUH

desc SCMRUH
address_offset : 0xCA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMRUH SCMRUH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMC MZCE MPCE

AMC : desc AMC
bits : 0 - 2 (3 bit)
access : read-write

MZCE : desc MZCE
bits : 6 - 5 (0 bit)
access : read-write

MPCE : desc MPCE
bits : 7 - 6 (0 bit)
access : read-write


SCSRUL

desc SCSRUL
address_offset : 0xCC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSRUL SCSRUL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFEN EVTOS LMC EVTMS EVTDS DEN PEN UEN ZEN

BUFEN : desc BUFEN
bits : 0 - 0 (1 bit)
access : read-write

EVTOS : desc EVTOS
bits : 2 - 3 (2 bit)
access : read-write

LMC : desc LMC
bits : 5 - 4 (0 bit)
access : read-write

EVTMS : desc EVTMS
bits : 8 - 7 (0 bit)
access : read-write

EVTDS : desc EVTDS
bits : 9 - 8 (0 bit)
access : read-write

DEN : desc DEN
bits : 12 - 11 (0 bit)
access : read-write

PEN : desc PEN
bits : 13 - 12 (0 bit)
access : read-write

UEN : desc UEN
bits : 14 - 13 (0 bit)
access : read-write

ZEN : desc ZEN
bits : 15 - 14 (0 bit)
access : read-write


SCMRUL

desc SCMRUL
address_offset : 0xCE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMRUL SCMRUL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMC MZCE MPCE

AMC : desc AMC
bits : 0 - 2 (3 bit)
access : read-write

MZCE : desc MZCE
bits : 6 - 5 (0 bit)
access : read-write

MPCE : desc MPCE
bits : 7 - 6 (0 bit)
access : read-write


SCSRVH

desc SCSRVH
address_offset : 0xD0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSRVH SCSRVH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFEN EVTOS LMC EVTMS EVTDS DEN PEN UEN ZEN

BUFEN : desc BUFEN
bits : 0 - 0 (1 bit)
access : read-write

EVTOS : desc EVTOS
bits : 2 - 3 (2 bit)
access : read-write

LMC : desc LMC
bits : 5 - 4 (0 bit)
access : read-write

EVTMS : desc EVTMS
bits : 8 - 7 (0 bit)
access : read-write

EVTDS : desc EVTDS
bits : 9 - 8 (0 bit)
access : read-write

DEN : desc DEN
bits : 12 - 11 (0 bit)
access : read-write

PEN : desc PEN
bits : 13 - 12 (0 bit)
access : read-write

UEN : desc UEN
bits : 14 - 13 (0 bit)
access : read-write

ZEN : desc ZEN
bits : 15 - 14 (0 bit)
access : read-write


SCMRVH

desc SCMRVH
address_offset : 0xD2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMRVH SCMRVH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMC MZCE MPCE

AMC : desc AMC
bits : 0 - 2 (3 bit)
access : read-write

MZCE : desc MZCE
bits : 6 - 5 (0 bit)
access : read-write

MPCE : desc MPCE
bits : 7 - 6 (0 bit)
access : read-write


SCSRVL

desc SCSRVL
address_offset : 0xD4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSRVL SCSRVL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFEN EVTOS LMC EVTMS EVTDS DEN PEN UEN ZEN

BUFEN : desc BUFEN
bits : 0 - 0 (1 bit)
access : read-write

EVTOS : desc EVTOS
bits : 2 - 3 (2 bit)
access : read-write

LMC : desc LMC
bits : 5 - 4 (0 bit)
access : read-write

EVTMS : desc EVTMS
bits : 8 - 7 (0 bit)
access : read-write

EVTDS : desc EVTDS
bits : 9 - 8 (0 bit)
access : read-write

DEN : desc DEN
bits : 12 - 11 (0 bit)
access : read-write

PEN : desc PEN
bits : 13 - 12 (0 bit)
access : read-write

UEN : desc UEN
bits : 14 - 13 (0 bit)
access : read-write

ZEN : desc ZEN
bits : 15 - 14 (0 bit)
access : read-write


SCMRVL

desc SCMRVL
address_offset : 0xD6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMRVL SCMRVL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMC MZCE MPCE

AMC : desc AMC
bits : 0 - 2 (3 bit)
access : read-write

MZCE : desc MZCE
bits : 6 - 5 (0 bit)
access : read-write

MPCE : desc MPCE
bits : 7 - 6 (0 bit)
access : read-write


SCSRWH

desc SCSRWH
address_offset : 0xD8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSRWH SCSRWH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFEN EVTOS LMC EVTMS EVTDS DEN PEN UEN ZEN

BUFEN : desc BUFEN
bits : 0 - 0 (1 bit)
access : read-write

EVTOS : desc EVTOS
bits : 2 - 3 (2 bit)
access : read-write

LMC : desc LMC
bits : 5 - 4 (0 bit)
access : read-write

EVTMS : desc EVTMS
bits : 8 - 7 (0 bit)
access : read-write

EVTDS : desc EVTDS
bits : 9 - 8 (0 bit)
access : read-write

DEN : desc DEN
bits : 12 - 11 (0 bit)
access : read-write

PEN : desc PEN
bits : 13 - 12 (0 bit)
access : read-write

UEN : desc UEN
bits : 14 - 13 (0 bit)
access : read-write

ZEN : desc ZEN
bits : 15 - 14 (0 bit)
access : read-write


SCMRWH

desc SCMRWH
address_offset : 0xDA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMRWH SCMRWH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMC MZCE MPCE

AMC : desc AMC
bits : 0 - 2 (3 bit)
access : read-write

MZCE : desc MZCE
bits : 6 - 5 (0 bit)
access : read-write

MPCE : desc MPCE
bits : 7 - 6 (0 bit)
access : read-write


SCSRWL

desc SCSRWL
address_offset : 0xDC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSRWL SCSRWL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFEN EVTOS LMC EVTMS EVTDS DEN PEN UEN ZEN

BUFEN : desc BUFEN
bits : 0 - 0 (1 bit)
access : read-write

EVTOS : desc EVTOS
bits : 2 - 3 (2 bit)
access : read-write

LMC : desc LMC
bits : 5 - 4 (0 bit)
access : read-write

EVTMS : desc EVTMS
bits : 8 - 7 (0 bit)
access : read-write

EVTDS : desc EVTDS
bits : 9 - 8 (0 bit)
access : read-write

DEN : desc DEN
bits : 12 - 11 (0 bit)
access : read-write

PEN : desc PEN
bits : 13 - 12 (0 bit)
access : read-write

UEN : desc UEN
bits : 14 - 13 (0 bit)
access : read-write

ZEN : desc ZEN
bits : 15 - 14 (0 bit)
access : read-write


SCMRWL

desc SCMRWL
address_offset : 0xDE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMRWL SCMRWL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMC MZCE MPCE

AMC : desc AMC
bits : 0 - 2 (3 bit)
access : read-write

MZCE : desc MZCE
bits : 6 - 5 (0 bit)
access : read-write

MPCE : desc MPCE
bits : 7 - 6 (0 bit)
access : read-write


OCCRVL

desc OCCRVL
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCCRVL OCCRVL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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