\n

EMB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTL

STATCLR

INTEN

PWMLV

SOE

STAT


CTL

desc CTL
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTINEN CMPEN OSCSTPEN PWMSEL NFSEL NFEN INVSEL

PORTINEN : desc PORTINEN
bits : 0 - -1 (0 bit)
access : read-write

CMPEN : desc CMPEN
bits : 1 - 1 (1 bit)
access : read-write

OSCSTPEN : desc OSCSTPEN
bits : 5 - 4 (0 bit)
access : read-write

PWMSEL : desc PWMSEL
bits : 6 - 7 (2 bit)
access : read-write

NFSEL : desc NFSEL
bits : 28 - 28 (1 bit)
access : read-write

NFEN : desc NFEN
bits : 30 - 29 (0 bit)
access : read-write

INVSEL : desc INVSEL
bits : 31 - 30 (0 bit)
access : read-write


STATCLR

desc STATCLR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

STATCLR STATCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTINFCLR PWMSFCLR CMPFCLR OSFCLR

PORTINFCLR : desc PORTINFCLR
bits : 0 - -1 (0 bit)
access : write-only

PWMSFCLR : desc PWMSFCLR
bits : 1 - 0 (0 bit)
access : write-only

CMPFCLR : desc CMPFCLR
bits : 2 - 1 (0 bit)
access : write-only

OSFCLR : desc OSFCLR
bits : 3 - 2 (0 bit)
access : write-only


INTEN

desc INTEN
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTINTEN PWMINTEN CMPINTEN OSINTEN

PORTINTEN : desc PORTINTEN
bits : 0 - -1 (0 bit)
access : read-write

PWMINTEN : desc PWMINTEN
bits : 1 - 0 (0 bit)
access : read-write

CMPINTEN : desc CMPINTEN
bits : 2 - 1 (0 bit)
access : read-write

OSINTEN : desc OSINTEN
bits : 3 - 2 (0 bit)
access : read-write


PWMLV

desc PWMLV
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMLV PWMLV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMLV

PWMLV : desc PWMLV
bits : 0 - 1 (2 bit)
access : read-write


SOE

desc SOE
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOE SOE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOE

SOE : desc SOE
bits : 0 - -1 (0 bit)
access : read-write


STAT

desc STAT
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTINF PWMSF CMPF OSF PORTINST PWMST

PORTINF : desc PORTINF
bits : 0 - -1 (0 bit)
access : read-only

PWMSF : desc PWMSF
bits : 1 - 0 (0 bit)
access : read-only

CMPF : desc CMPF
bits : 2 - 1 (0 bit)
access : read-only

OSF : desc OSF
bits : 3 - 2 (0 bit)
access : read-only

PORTINST : desc PORTINST
bits : 4 - 3 (0 bit)
access : read-only

PWMST : desc PWMST
bits : 5 - 4 (0 bit)
access : read-only



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