\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
desc CR1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE : desc PE
bits : 0 - -1 (0 bit)
access : read-write
SMBUS : desc SMBUS
bits : 1 - 0 (0 bit)
access : read-write
SMBALRTEN : desc SMBALRTEN
bits : 2 - 1 (0 bit)
access : read-write
SMBDEFAULTEN : desc SMBDEFAULTEN
bits : 3 - 2 (0 bit)
access : read-write
SMBHOSTEN : desc SMBHOSTEN
bits : 4 - 3 (0 bit)
access : read-write
FACKEN : desc FACKEN
bits : 5 - 4 (0 bit)
access : read-write
GCEN : desc GCEN
bits : 6 - 5 (0 bit)
access : read-write
RESTART : desc RESTART
bits : 7 - 6 (0 bit)
access : read-write
START : desc START
bits : 8 - 7 (0 bit)
access : read-write
STOP : desc STOP
bits : 9 - 8 (0 bit)
access : read-write
ACK : desc ACK
bits : 10 - 9 (0 bit)
access : read-write
SWRST : desc SWRST
bits : 15 - 14 (0 bit)
access : read-write
desc SLR0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLADDR0 : desc SLADDR0
bits : 0 - 8 (9 bit)
access : read-write
SLADDR0EN : desc SLADDR0EN
bits : 12 - 11 (0 bit)
access : read-write
ADDRMOD0 : desc ADDRMOD0
bits : 15 - 14 (0 bit)
access : read-write
desc SLR1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLADDR1 : desc SLADDR1
bits : 0 - 8 (9 bit)
access : read-write
SLADDR1EN : desc SLADDR1EN
bits : 12 - 11 (0 bit)
access : read-write
ADDRMOD1 : desc ADDRMOD1
bits : 15 - 14 (0 bit)
access : read-write
desc SR
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STARTF : desc STARTF
bits : 0 - -1 (0 bit)
access : read-only
SLADDR0F : desc SLADDR0F
bits : 1 - 0 (0 bit)
access : read-only
SLADDR1F : desc SLADDR1F
bits : 2 - 1 (0 bit)
access : read-only
TENDF : desc TENDF
bits : 3 - 2 (0 bit)
access : read-only
STOPF : desc STOPF
bits : 4 - 3 (0 bit)
access : read-only
RFULLF : desc RFULLF
bits : 6 - 5 (0 bit)
access : read-only
TEMPTYF : desc TEMPTYF
bits : 7 - 6 (0 bit)
access : read-only
ARLOF : desc ARLOF
bits : 9 - 8 (0 bit)
access : read-only
ACKRF : desc ACKRF
bits : 10 - 9 (0 bit)
access : read-only
NACKF : desc NACKF
bits : 12 - 11 (0 bit)
access : read-only
MSL : desc MSL
bits : 16 - 15 (0 bit)
access : read-write
BUSY : desc BUSY
bits : 17 - 16 (0 bit)
access : read-only
TRA : desc TRA
bits : 18 - 17 (0 bit)
access : read-write
GENCALLF : desc GENCALLF
bits : 20 - 19 (0 bit)
access : read-only
SMBDEFAULTF : desc SMBDEFAULTF
bits : 21 - 20 (0 bit)
access : read-only
SMBHOSTF : desc SMBHOSTF
bits : 22 - 21 (0 bit)
access : read-only
SMBALRTF : desc SMBALRTF
bits : 23 - 22 (0 bit)
access : read-only
desc CLR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
STARTFCLR : desc STARTFCLR
bits : 0 - -1 (0 bit)
access : write-only
SLADDR0FCLR : desc SLADDR0FCLR
bits : 1 - 0 (0 bit)
access : write-only
SLADDR1FCLR : desc SLADDR1FCLR
bits : 2 - 1 (0 bit)
access : write-only
TENDFCLR : desc TENDFCLR
bits : 3 - 2 (0 bit)
access : write-only
STOPFCLR : desc STOPFCLR
bits : 4 - 3 (0 bit)
access : write-only
RFULLFCLR : desc RFULLFCLR
bits : 6 - 5 (0 bit)
access : write-only
TEMPTYFCLR : desc TEMPTYFCLR
bits : 7 - 6 (0 bit)
access : write-only
ARLOFCLR : desc ARLOFCLR
bits : 9 - 8 (0 bit)
access : write-only
NACKFCLR : desc NACKFCLR
bits : 12 - 11 (0 bit)
access : write-only
GENCALLFCLR : desc GENCALLFCLR
bits : 20 - 19 (0 bit)
access : write-only
SMBDEFAULTFCLR : desc SMBDEFAULTFCLR
bits : 21 - 20 (0 bit)
access : write-only
SMBHOSTFCLR : desc SMBHOSTFCLR
bits : 22 - 21 (0 bit)
access : write-only
SMBALRTFCLR : desc SMBALRTFCLR
bits : 23 - 22 (0 bit)
access : write-only
desc DTR
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DT : desc DT
bits : 0 - 6 (7 bit)
access : read-write
desc DRR
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : desc DR
bits : 0 - 6 (7 bit)
access : read-write
desc CCR
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOWW : desc SLOWW
bits : 0 - 3 (4 bit)
access : read-write
SHIGHW : desc SHIGHW
bits : 8 - 11 (4 bit)
access : read-write
CKDIV : desc CKDIV
bits : 16 - 17 (2 bit)
access : read-write
desc FLTR
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DNF : desc DNF
bits : 0 - 0 (1 bit)
access : read-write
DNFEN : desc DNFEN
bits : 4 - 3 (0 bit)
access : read-write
ANFEN : desc ANFEN
bits : 5 - 4 (0 bit)
access : read-write
desc CR2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTIE : desc STARTIE
bits : 0 - -1 (0 bit)
access : read-write
SLADDR0IE : desc SLADDR0IE
bits : 1 - 0 (0 bit)
access : read-write
SLADDR1IE : desc SLADDR1IE
bits : 2 - 1 (0 bit)
access : read-write
TENDIE : desc TENDIE
bits : 3 - 2 (0 bit)
access : read-write
STOPIE : desc STOPIE
bits : 4 - 3 (0 bit)
access : read-write
RFULLIE : desc RFULLIE
bits : 6 - 5 (0 bit)
access : read-write
TEMPTYIE : desc TEMPTYIE
bits : 7 - 6 (0 bit)
access : read-write
ARLOIE : desc ARLOIE
bits : 9 - 8 (0 bit)
access : read-write
NACKIE : desc NACKIE
bits : 12 - 11 (0 bit)
access : read-write
GENCALLIE : desc GENCALLIE
bits : 20 - 19 (0 bit)
access : read-write
SMBDEFAULTIE : desc SMBDEFAULTIE
bits : 21 - 20 (0 bit)
access : read-write
SMBHOSTIE : desc SMBHOSTIE
bits : 22 - 21 (0 bit)
access : read-write
SMBALRTIE : desc SMBALRTIE
bits : 23 - 22 (0 bit)
access : read-write
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