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BDRV

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL1

SEQMAP

TRIM_DRVx

CP_CTRL

CP_CLK_CTRL

IGATECLMPONC

IGATECLMPOFFC

CTRL2

CP_IRQS

CP_IRQCLR

CP_IRQEN

OFFSEQHB1TC

OFFSEQHB1IC

ONSEQHB1TC

ONSEQHB1IC

SEQAFHB1IC

SEQAFHB1CD

OFFSEQHB2TC

OFFSEQHB2IC

ONSEQHB2TC

ONSEQHB2IC

CTRL3

SEQAFHB2IC

SEQAFHB2CD

ASEQC

ASEQSTS

ONASEQTMIN

OFFASEQTMIN

ASEQIONMIN

ASEQIOFFMIN

ONASEQTMAX

OFFASEQTMAX

ASEQIONMAX

ASEQIOFFMAX

HB1ASEQONVAL

HB1ASEQOFFVAL

PWMSRCSEL

HB2ASEQONVAL

HB2ASEQOFFVAL

ASEQERRCNT

DCTRIM_DRVx

IRQS

IRQCLR

IRQEN


CTRL1

H-Bridge Driver Control 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS1_EN LS1_PWM LS1_ON LS1_SUPERR_STS LS1_OC_DIS LS2_EN LS2_PWM LS2_ON LS2_SUPERR_STS LS2_OC_DIS HS1_EN HS1_PWM HS1_ON HS1_DCS_EN HS1_SUPERR_STS HS1_OC_DIS HS2_EN HS2_PWM HS2_ON HS2_DCS_EN HS2_SUPERR_STS HS2_OC_DIS

LS1_EN : Low Side Driver 1 Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

Driver circuit power off

0b1 : ENABLE

Driver circuit power on

End of enumeration elements list.

LS1_PWM : Low Side Driver 1 PWM Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

disables control by PWM input

0b1 : ENABLE

enables control by PWM input

End of enumeration elements list.

LS1_ON : Low Side Driver 1 On
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : OFF

Driver off

0b1 : ON

Driver on

End of enumeration elements list.

LS1_SUPERR_STS : Low Side Driver 1 Supply Error Status
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

0b0 : NORMAL

supply is in required range.

0b1 : SUPPLY_ERROR

detected this flag is an OR of the VDS_x_STS and VCP_x_STS flags.

End of enumeration elements list.

LS1_OC_DIS : Low Side Driver 1 Overcurrent Shutdown Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0x0 : Global_Shutdown

all bridges will be shut down in case of overcurrent

0x1 : Local_Shutdown

only local driver will be shut down in case of overcurrent

End of enumeration elements list.

LS2_EN : Low Side Driver 2 Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

Driver circuit power off

0b1 : ENABLE

Driver circuit power on

End of enumeration elements list.

LS2_PWM : Low Side Driver 2 PWM Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

disables control by PWM input

0b1 : ENABLE

enables control by PWM input

End of enumeration elements list.

LS2_ON : Low Side Driver 2 On
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

0b0 : OFF

Driver off

0b1 : ON

Driver on

End of enumeration elements list.

LS2_SUPERR_STS : Low Side Driver 2 Supply Error Status
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

0b0 : NORMAL

supply is in required range.

0b1 : SUPPLY_ERROR

detected this flag is an OR of the VDS_x_STS and VCP_x_STS flags.

End of enumeration elements list.

LS2_OC_DIS : Low Side Driver Overcurrent Shutdown Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0x0 : Global_Shutdown

all bridges will be shut down in case of overcurrent

0x1 : Local_Shutdown

only local driver will be shut down in case of overcurrent

End of enumeration elements list.

HS1_EN : High Side Driver 1 Enable
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

Driver circuit power off

0b1 : ENABLE

Driver circuit power on

End of enumeration elements list.

HS1_PWM : High Side Driver 1 PWM Enable
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

disables control by PWM input

0b1 : ENABLE

enables control by PWM input

End of enumeration elements list.

HS1_ON : High Side Driver 1 On
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

0b0 : OFF

Driver off

0b1 : ON

Driver on

End of enumeration elements list.

HS1_DCS_EN : High Side Driver 1 Diagnosis Current Source Enable
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

0x0 : DISABLE

disable current source

0x1 : ENABLE

enable current source short diagnosis can be performed by evaluating the LSx/HSx_DS_STS Flag

End of enumeration elements list.

HS1_SUPERR_STS : High Side Driver 1 Supply Error Status
bits : 21 - 20 (0 bit)
access : read-only

Enumeration:

0b0 : NORMAL

supply is in required range.

0b1 : SUPPLY_ERROR

detected this flag is an OR of the VDS_x_STS and VCP_x_STS flags.

End of enumeration elements list.

HS1_OC_DIS : High Side Driver Overcurrent Shutdown Select
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

0x0 : Global_Shutdown

all bridges will be shut down in case of overcurrent

0x1 : Local_Shutdown

only local driver will be shut down in case of overcurrent

End of enumeration elements list.

HS2_EN : High Side Driver 2 Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

Driver circuit power off

0b1 : ENABLE

Driver circuit power on

End of enumeration elements list.

HS2_PWM : High Side Driver 2 PWM Enable
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

disables control by PWM input

0b1 : ENABLE

enables control by PWM input

End of enumeration elements list.

HS2_ON : High Side Driver 2 On
bits : 26 - 25 (0 bit)
access : read-write

Enumeration:

0b0 : OFF

Driver off

0b1 : ON

Driver on

End of enumeration elements list.

HS2_DCS_EN : High Side Driver 2 Diagnosis Current Source Enable
bits : 27 - 26 (0 bit)
access : read-write

Enumeration:

0x0 : DISABLE

disable current source

0x1 : ENABLE

enable current source short diagnosis can be performed by evaluating the LSx/HSx_DS_STS Flag

End of enumeration elements list.

HS2_SUPERR_STS : High Side Driver 2 Supply Error Status
bits : 29 - 28 (0 bit)
access : read-only

Enumeration:

0b0 : NORMAL

supply is in required range.

0b1 : SUPPLY_ERROR

detected this flag is an OR of the VSD_x_STS and VCP_x_STS flags.

End of enumeration elements list.

HS2_OC_DIS : High Side Driver Overcurrent Shutdown Select
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

0x0 : Global_Shutdown

all bridges will be shut down in case of overcurrent

0x1 : Local_Shutdown

only local driver will be shut down in case of overcurrent

End of enumeration elements list.


SEQMAP

Slewrate Sequencer Mapping Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQMAP SEQMAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1_SEQMAP HB2_SEQMAP

HB1_SEQMAP : Half Bridge 1 Sequencer Mapping
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0x0 : LS1

slew rate sequencer is mapped to LS1

0x1 : HS1

slew rate sequencer is mapped to HS1

End of enumeration elements list.

HB2_SEQMAP : Half Bridge 2 Sequencer Mapping
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0x0 : LS2

slew rate sequencer is mapped to LS2

0x1 : HS2

slew rate sequencer is mapped to HS2

End of enumeration elements list.


TRIM_DRVx

Trimming of Driver
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIM_DRVx TRIM_DRVx read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS_HS_BT_TFILT_SEL LSDRV_DS_TFILT_SEL LS1DRV_FDISCHG_DIS LS2DRV_FDISCHG_DIS LS1DRV_OCSDN_DIS LS2DRV_OCSDN_DIS HSDRV_DS_TFILT_SEL HS1DRV_FDISCHG_DIS HS2DRV_FDISCHG_DIS HS1DRV_OCSDN_DIS HS2DRV_OCSDN_DIS CPLOW_TFILT_SEL

LS_HS_BT_TFILT_SEL : Blanking Time for Drain-Source Monitoring of Low / High Side Drivers
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0b00 : 1_us

1 us filter time

0b01 : 2_us

2 us filter time

0b10 : 4_us

4 us filter time

0b11 : 8_us

8 us filter time

End of enumeration elements list.

LSDRV_DS_TFILT_SEL : Filter Time for Drain-Source Monitoring of Low Side Drivers
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0b00 : 1_us

1 us filter time

0b01 : 2_us

2 us filter time

0b10 : 4_us

4 us filter time

0b11 : 8_us

8 us filter time

End of enumeration elements list.

LS1DRV_FDISCHG_DIS : Low Side 1 Predriver fast discharge disable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Predriver shutdown fast discharge enable

0b1 : Disable

Predriver shutdown fast discharge disable

End of enumeration elements list.

LS2DRV_FDISCHG_DIS : Low Side 2 Predriver fast discharge disable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Predriver shutdown fast discharge enable

0b1 : Disable

Predriver shutdown fast discharge disable

End of enumeration elements list.

LS1DRV_OCSDN_DIS : Low Side 1 Predriver in overcurrent situation disable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Predriver shutdown in overcurrent situation enable

0b1 : Disable

Predriver shutdown in overcurrent situation disable

End of enumeration elements list.

LS2DRV_OCSDN_DIS : Low Side 2 Predriver in overcurrent situation disable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Predriver shutdown in overcurrent situation enable

0b1 : Disable

Predriver shutdown in overcurrent situation disable

End of enumeration elements list.

HSDRV_DS_TFILT_SEL : Filter Time for Drain-Source Monitoring of High Side Drivers
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0b00 : 1_us

1 us filter time

0b01 : 2_us

2 us filter time

0b10 : 4_us

4 us filter time

0b11 : 8_us

8 us filter time

End of enumeration elements list.

HS1DRV_FDISCHG_DIS : High Side 1 Predriver fast discharge disable
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Predriver shutdown fast discharge enable

0b1 : Disable

Predriver shutdown fast discharge disable

End of enumeration elements list.

HS2DRV_FDISCHG_DIS : High Side 2 Predriver fast discharge disable
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Predriver shutdown fast discharge enable

0b1 : Disable

Predriver shutdown fast discharge disable

End of enumeration elements list.

HS1DRV_OCSDN_DIS : High Side 1 Predriver in overcurrent situation disable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Predriver shutdown in overcurrent situation enable

0b1 : Disable

Predriver shutdown in overcurrent situation disable

End of enumeration elements list.

HS2DRV_OCSDN_DIS : High Side 2 Predriver in overcurrent situation disable
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Predriver shutdown in overcurrent situation enable

0b1 : Disable

Predriver shutdown in overcurrent situation disable

End of enumeration elements list.

CPLOW_TFILT_SEL : Filter Time for Charge Pump Voltage Low Diagnosis
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0b00 : 4_us

4 us filter time

0b01 : 8_us

8 us filter time

0b10 : 16_us

16 us filter time

0b11 : 32_us

32 us filter time

End of enumeration elements list.


CP_CTRL

Charge Pump Control and Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CP_CTRL CP_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP_EN CP_RDY_EN VCP_LOWTH2 DRVx_VCPLO_DIS DRVx_VCPLO_SDEN DRVx_VCPUP_DIS DRVx_VSDLO_DIS DRVx_VSDUP_DIS CPLOPWRM_EN VCP9V_SET VTHVCP_TRIM VCP14_15V_SEL CP_STAGE_SEL

CP_EN : Charge Pump Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

Charge Pump, circuit power off

0b1 : ENABLE

Charge Pump, circuit power on

End of enumeration elements list.

CP_RDY_EN : Bridge Driver on Charge Pump Ready Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : OFF

Bridge Driver can be immediately enabled

0b1 : ON

Bridge Driver can only be enabled when Charge Pump is ready

End of enumeration elements list.

VCP_LOWTH2 : Charge Pump Output Voltage Lower Threshold Detection Level
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0b000 : 7.325_V

Threshold 0

0b001 : 7.654_V

Threshold 1

0b010 : 7.982_V

Threshold 2

0b011 : 8.309_V

Threshold 3

0b100 : 8.638_V

Threshold 4

0b101 : 8.966_V

Threshold 5

0b110 : 9.293_V

Threshold 6

0b111 : 9.620_V

Threshold 7

End of enumeration elements list.

DRVx_VCPLO_DIS : Driver On Charge Pump Low Voltage Disable
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : Driver Enable

DRVx on Charge Pump undervoltage enable.

0b1 : Driver Disable

DRVx on Charge Pump undervoltage disable.

End of enumeration elements list.

DRVx_VCPLO_SDEN : Driver Charge Pump Low Voltage Shut-Down
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

0b0 : Shut-Down Disable

DRVx Shut-Down for Charge Pump undervoltage disable.

0b1 : Shut-Down Enable

DRVx Shut-Down for Charge Pump undervoltage enable.

End of enumeration elements list.

DRVx_VCPUP_DIS : Driver On Charge Pump Upper Voltage Disable
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

0b0 : Driver Enable

DRVx on Charge Pumpe overvoltage enable.

0b1 : Driver Disable

DRVx on Charge Pump overvoltage disable.

End of enumeration elements list.

DRVx_VSDLO_DIS : Driver On VSD Lower Voltage Disable
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

0b0 : Driver Enable

DRVx on VSD undervoltage enable.

0b1 : Driver Disable

DRVx on VSD undervoltage disable.

End of enumeration elements list.

DRVx_VSDUP_DIS : Driver On VSD Upper Voltage Disable
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

0b0 : Driver Enable

DRVx on VSD overvoltage enable.

0b1 : Driver Disable

DRVx on VSD overvoltage disable.

End of enumeration elements list.

CPLOPWRM_EN : Charge Pump Low Power Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

0b0 : Low Power Mode Disable

low power mode inactive

0b1 : Low Power Mode Enable

low power mode active

End of enumeration elements list.

VCP9V_SET : Charge Pump 9 V Output Voltage Set
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

0b0 : 15_14V Set

output voltage set according to VCP14_15V_SEL

0b1 : 9V Set

output voltage set to 9V

End of enumeration elements list.

VTHVCP_TRIM : Charge Pump Output Voltage Trimming
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0b00 : 0.0_V

default

0b01 : 0.5_V

plus 0.5V nom at 15V

0b10 : 1.0_V

plus 1.0V nom at 15V

0b11 : 1.5_V

plus 1.5V nom at 15V

End of enumeration elements list.

VCP14_15V_SEL : Charge Pump 15V/14V Output Voltage Sel
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

0b0 : 14V

output voltage set to 14V

0b1 : 15V

output voltage set to 15V

End of enumeration elements list.

CP_STAGE_SEL : Charge Pump Output Voltage Trimming
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0b00 : 2-stage

2-stage mode enabled

0b01 : 1-stage1

single stage mode enable (1st stage)

0b10 : 1-stage2

single stage mode enable (2nd stage)

0b11 : auto

automatic switch to single stage mode above 18V VSD (2nd stage) and switching back to 2-stage mode below 17V VSD

End of enumeration elements list.


CP_CLK_CTRL

Charge Pump Clock Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CP_CLK_CTRL CP_CLK_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITH_LOWER DITH_UPPER F_CP CPCLK_EN CPCLKDIS_SET

DITH_LOWER : CP_CLK lower frequency boundary during dithering
bits : 0 - 3 (4 bit)
access : read-write

DITH_UPPER : CP_CLK upper frequency boundary during dithering
bits : 8 - 11 (4 bit)
access : read-write

F_CP : MSB of CP_CLK divider
bits : 13 - 13 (1 bit)
access : read-write

CPCLK_EN : Charge Pump Clock Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

Charge Pump Clock is switched off and has value of according to CPCLKDIS_SET

0b1 : ENABLE

Charge Pump Clock is running

End of enumeration elements list.

CPCLKDIS_SET : Charge Pump Clock Set If Disabled
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : LOW

Charge Pump Clock is 0 if disabled

0b1 : HIGH

Charge Pump Clock is 1 if disabled

End of enumeration elements list.


IGATECLMPONC

Gate Current Clamping Value in ON State
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IGATECLMPONC IGATECLMPONC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1_ICLMPON HB2_ICLMPON HB1AF_ICLMPON HB2AF_ICLMPON

HB1_ICLMPON : Half Bridge 1-current clamping value for ON state
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.

HB2_ICLMPON : Half Bridge 2-current clamping value for ON state
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.

HB1AF_ICLMPON : Half Bridge 1-active freewheeling-current clamping value for ON state
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.

HB2AF_ICLMPON : Half Bridge 2-active freewheeling-current clamping value for ON state
bits : 24 - 28 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.


IGATECLMPOFFC

Gate Current Clamping Value in OFF State
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IGATECLMPOFFC IGATECLMPOFFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1_ICLMPOFF HB2_ICLMPOFF HB1AF_ICLMPOFF HB2AF_ICLMPOFF

HB1_ICLMPOFF : Half Bridge 1-current clamping value for OFF state
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.

HB2_ICLMPOFF : Half Bridge 2-current clamping value for OFF state
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.

HB1AF_ICLMPOFF : Half Bridge 1-active freewheeling-current clamping value for OFF state
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.

HB2AF_ICLMPOFF : Half Bridge 2-active freewheeling-current clamping value for OFF state
bits : 24 - 28 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.


CTRL2

H-Bridge Driver Control 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1ONSEQCNF HB2ONSEQCNF HB1OFFSEQCNF HB2OFFSEQCNF DLY_DIAG_TIM DLY_DIAG_SCLR DLY_DIAG_STS DLY_DIAG_CHSEL DLY_DIAG_DIRSEL

HB1ONSEQCNF : Half Bridge 1 On Sequencer Configuration
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : Normal Mode

ON-Sequencer is disabled and driver operates with constant current.

0b1 : Sequencer Mode

ON-Sequencer is enabled.

End of enumeration elements list.

HB2ONSEQCNF : Half Bridge 2 On Sequencer Configuration
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : Normal Mode

ON-Sequencer is disabled and driver operates with constant current.

0b1 : Sequencer Mode

ON-Sequencer is enabled.

End of enumeration elements list.

HB1OFFSEQCNF : Half Bridge 1 Off Sequencer Configuration
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : Normal Mode

OFF-Sequencer is disabled and driver operates with constant current.

0b1 : Sequencer Mode

OFF-Sequencer is enabled.

End of enumeration elements list.

HB2OFFSEQCNF : Half Bridge 2 Off Sequencer Configuration
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : Normal Mode

OFF-Sequencer is disabled and driver operates with constant current.

0b1 : Sequencer Mode

OFF-Sequencer is enabled.

End of enumeration elements list.

DLY_DIAG_TIM : Ext. power diag timer result register
bits : 16 - 24 (9 bit)
access : read-only

DLY_DIAG_SCLR : Ext. power diag timer valid flag clear
bits : 26 - 25 (0 bit)
access : write-only

Enumeration:

0b0 : Diag timer valid not clear

None

0b1 : Diag timer valid clear

None

End of enumeration elements list.

DLY_DIAG_STS : Ext. power diag timer valid flag
bits : 27 - 26 (0 bit)
access : read-only

Enumeration:

0b0 : Diag_timer_invalid

diag timer measurement ongoing

0b1 : Diag_timer_valid

diag timer measurement finished

End of enumeration elements list.

DLY_DIAG_CHSEL : Ext. power diag timer channel select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0b000 : DISABLE

diag timer deactivated.

0b001 : HB1 LS select

measure LS1 on/off delay time.

0b010 : HB2 LS select

measure LS2 on/off delay time.

0b101 : HB1 HS select

measure HS1 on/off delay time.

0b110 : HB2 HS select

measure HS2 on/off delay time.

0b110 : Reserved

Reserved

0b110 : Reserved

Reserved

End of enumeration elements list.

DLY_DIAG_DIRSEL : Ext. power diag timer on / off select
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

0b0 : TURN OFF

measure turn off time

0b1 : TURN ON

measure turn on time

End of enumeration elements list.


CP_IRQS

Charge Pump Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CP_IRQS CP_IRQS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCP_OTW_IS VCP_OTSD_IS VCP_LOTH2_IS VCP_LOTH1_IS VCP_UPTH_IS VSD_LOTH_IS VSD_UPTH_IS VCP_OTW_STS VCP_OTSD_STS VCP_LOTH2_STS VCP_LOTH1_STS VCP_UPTH_STS VSD_LOTH_STS VSD_UPTH_STS

VCP_OTW_IS : Charge Pump Overtemperature Warning Interrupt Status
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Charge Pump Temperature ok, no charge pump overtemperature warning detected.

0b1 : warning

Charge Pump Overtemperature Warning, overtemperature threshold on charge pump reached.

End of enumeration elements list.

VCP_OTSD_IS : Charge Pump Overtemperature Shutdown Interrupt Status
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Charge Pump Overtemperature Shutdown Threshold not reached, no charge pump overtemperature shutdown detected.

0b1 : shutdown

Charge Pump Overtemperature Shutdown, overtemperature shutdown on charge pump occured.

End of enumeration elements list.

VCP_LOTH2_IS : Charge Pump Low Interrupt Status
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Charge Pump Output Voltage ok, no undervoltage detected.

0b1 : too_low

Charge Pump Output Voltage too low, undervoltage on chargepump output detected.

End of enumeration elements list.

VCP_LOTH1_IS : Charge Pump MU Low Interrupt Status
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Charge Pump Output Voltage ok, no undervoltage detected.

0b1 : too_low

Charge Pump Output Voltage too low, undervoltage on charge pump output detected.

End of enumeration elements list.

VCP_UPTH_IS : Charge Pump MU High Interrupt Status
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Charge Pump Output Voltage ok, no overvoltage detected

0b1 : too_high

Charge Pump Output Voltage too high, overvoltage on charge pump output detected

End of enumeration elements list.

VSD_LOTH_IS : Driver Supply MU Low Interrupt Status
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Driver Supply Voltage ok, no undervoltage detected.

0b1 : too_low

Driver Supply Voltage too low, undervoltage on VSD Pin detected.

End of enumeration elements list.

VSD_UPTH_IS : Driver Supply MU High Interrupt Status
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Driver Supply Voltage ok, no overvoltage detected

0b1 : too_high

Driver Supply Voltage too high, overvoltage on VSD Pin detected

End of enumeration elements list.

VCP_OTW_STS : Charge Pump Overtemperature Warning Status
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Charge Pump Temperature ok, no charge pump overtemperature warning detected.

0b1 : warning

harge Pump Overtemperature Warning, overtemperature threshold on charge pump reached.

End of enumeration elements list.

VCP_OTSD_STS : Charge Pump Overtemperature Shutdown Status
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Charge Pump Overtemperature Shutdown Threshold not reached, no charge pump overtemperature shutdown detected.

0b1 : shutdown

Charge Pump Overtemperature Shutdown, overtemperature shutdown on charge pump occured.

End of enumeration elements list.

VCP_LOTH2_STS : Charge Pump Low Status
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Charge Pump Output Voltage ok, no undervoltage detected.

0b1 : too_low

Charge Pump Output Voltage too low, undervoltage on chargepump output detected.

End of enumeration elements list.

VCP_LOTH1_STS : Charge Pump MU Low Status
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Charge Pump Output Voltage ok, no undervoltage detected.

0b1 : too_low

Charge Pump Output Voltage too low, undervoltage on chargepump output detected.

End of enumeration elements list.

VCP_UPTH_STS : Charge Pump MU High Status
bits : 27 - 26 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Charge Pump Output Voltage ok, no overvoltage detected

0b1 : too_high

Charge Pump Output Voltage too high, overvoltage on charge pump output detected

End of enumeration elements list.

VSD_LOTH_STS : Driver Supply MU Low Status
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Driver Supply Voltage ok, no undervoltage detected.

0b1 : too_low

Driver Supply Voltage too low, undervoltage on VSD Pin detected.

End of enumeration elements list.

VSD_UPTH_STS : Driver Supply MU High Status
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

0b0 : ok

Driver Supply Voltage ok, no overvoltage detected

0b1 : too_high

Driver Supply Voltage too high, overvoltage on VSD Pin detected

End of enumeration elements list.


CP_IRQCLR

Charge Pump Interrupt Status Clear Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CP_IRQCLR CP_IRQCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCP_OTW_ISC VCP_OTSD_ISC VCP_LOTH2_ISC VCP_LOTH1_ISC VCP_UPTH_ISC VSD_LOTH_ISC VSD_UPTH_ISC VCP_OTW_SC VCP_OTSD_SC VCP_LOTH2_SC VCP_LOTH1_SC VCP_UPTH_SC VSD_LOTH_SC VSD_UPTH_SC

VCP_OTW_ISC : Charge Pump Over-temperature Warning Interrupt Status Clear
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

VCP_OTSD_ISC : Charge Pump Over-temperature Shutdown Interrupt Status Clear
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

VCP_LOTH2_ISC : Charge Pump Low Interrupt Status Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

VCP_LOTH1_ISC : Charge Pump MU Low Interrupt Status Clear
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

VCP_UPTH_ISC : Charge Pump MU High Interrupt Status Clear
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

VSD_LOTH_ISC : Driver Supply MU Low Interrupt Status Clear
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

VSD_UPTH_ISC : Driver Supply MU High Interrupt Status Clear
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

VCP_OTW_SC : Charge Pump Over-temperature Warning Status Clear
bits : 16 - 15 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

VCP_OTSD_SC : Charge Pump Over-temperature Shutdown Status Clear
bits : 20 - 19 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

VCP_LOTH2_SC : Charge Pump Low Status Clear
bits : 24 - 23 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

VCP_LOTH1_SC : Charge Pump MU Low Status Clear
bits : 25 - 24 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

VCP_UPTH_SC : Charge Pump MU High Status Clear
bits : 27 - 26 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

VSD_LOTH_SC : Driver Supply MU Low Status Clear
bits : 29 - 28 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

VSD_UPTH_SC : Driver Supply MU High Status Clear
bits : 31 - 30 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.


CP_IRQEN

Charge Pump Interrupt Enable Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CP_IRQEN CP_IRQEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCP_OTW_IEN VCP_OTSD_IEN VCP_LOTH2_IEN VCP_LOTH1_IEN VCP_UPTH_IEN VSD_LOTH_IEN VSD_UPTH_IEN

VCP_OTW_IEN : Charge Pump Over-temperature Warning Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

VCP_OTSD_IEN : Charge Pump Over-temperature Shutdown Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

VCP_LOTH2_IEN : Charge Pump Low Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

VCP_LOTH1_IEN : Charge Pump MU Low Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

VCP_UPTH_IEN : Charge Pump MU High Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

VSD_LOTH_IEN : Driver Supply MU Low Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

VSD_UPTH_IEN : Driver Supply MU High Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.


OFFSEQHB1TC

Turn-off Slewrate Sequencer Half Bridge 1 Time Control
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFSEQHB1TC OFFSEQHB1TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1_T1OFF HB1_T2OFF HB1_T3OFF HB1_T4OFF

HB1_T1OFF : Half Bridge 1-slew rate sequencer off-phase 1 time setting
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.

HB1_T2OFF : Half Bridge 1-slew rate sequencer off-phase 2 time setting
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0x3F : 3.2us

3.2us phase duration

End of enumeration elements list.

HB1_T3OFF : Half Bridge 1-slew rate sequencer off-phase 3 time setting
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0x3F : 3.2us

3.2us phase duration

End of enumeration elements list.

HB1_T4OFF : Half Bridge 1-slew rate sequencer off-phase 4 time setting
bits : 24 - 30 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.


OFFSEQHB1IC

Turn-off Slewrate Sequencer Half Bridge 1 Current Control
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFSEQHB1IC OFFSEQHB1IC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1_I1OFF HB1_I2OFF HB1_I3OFF HB1_I4OFF

HB1_I1OFF : Half Bridge 1-slew rate sequencer off-phase 1 current setting
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.

HB1_I2OFF : Half Bridge 1-slew rate sequencer-off phase 2 current setting
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.

HB1_I3OFF : Half Bridge 1-slew rate sequencer off-phase 3 current setting
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.

HB1_I4OFF : Half Bridge 1-slew rate sequencer off-phase 4 current setting
bits : 24 - 28 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.


ONSEQHB1TC

Turn-on Slewrate Sequencer Half Bridge 1 Time Control
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ONSEQHB1TC ONSEQHB1TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1_T1ON HB1_T2ON HB1_T3ON HB1_T4ON

HB1_T1ON : Half Bridge 1-slew rate sequencer on-phase 1 time setting
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.

HB1_T2ON : Half Bridge 1-slew rate sequencer on-phase 2 time setting
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0x3F : 3.2us

3.2us phase duration

End of enumeration elements list.

HB1_T3ON : Half Bridge 1-slew rate sequencer on-phase 3 time setting
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0x3F : 3.2us

3.2us phase duration

End of enumeration elements list.

HB1_T4ON : Half Bridge 1-slew rate sequencer on-phase 4 time setting
bits : 24 - 30 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.


ONSEQHB1IC

Turn-on Slewrate Sequencer Half Bridge 1 Current Control
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ONSEQHB1IC ONSEQHB1IC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1_I1ON HB1_I2ON HB1_I3ON HB1_I4ON

HB1_I1ON : Half Bridge 1-slew rate sequencer on-phase 1 current setting
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.

HB1_I2ON : Half Bridge 1-slew rate sequencer on-phase 2 current setting
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.

HB1_I3ON : Half Bridge 1-slew rate sequencer on-phase 3 current setting
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.

HB1_I4ON : Half Bridge 1-slew rate sequencer on-phase 4 current setting
bits : 24 - 28 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.


SEQAFHB1IC

Slewrate Sequencer-Active Freewheeling-Half Bridge 1 Current Control
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQAFHB1IC SEQAFHB1IC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1AF_IOFF HB1AF_ION

HB1AF_IOFF : Half Bridge 1-active freewheeling-slew rate sequencer off-phase current setting
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.

HB1AF_ION : Half Bridge 1-active freewheeling-slew rate sequencer on-phase current setting
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.


SEQAFHB1CD

Slewrate Sequencer-Active Freewheeling- Half Bridge 1 Clamping Current Delay
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQAFHB1CD SEQAFHB1CD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1AF_TDICLMPOFF HB1AF_TDICLMPON

HB1AF_TDICLMPOFF : Clamping current delay during active freewheeling for switch off
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.

HB1AF_TDICLMPON : Clamping current delay during active freewheeling for switch on
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.


OFFSEQHB2TC

Turn-off Slewrate Sequencer Half Bridge 2 Time Control
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFSEQHB2TC OFFSEQHB2TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB2_T1OFF HB2_T2OFF HB2_T3OFF HB2_T4OFF

HB2_T1OFF : Half Bridge 2-slew rate sequencer off-phase 1 time setting
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.

HB2_T2OFF : Half Bridge 2-slew rate sequencer off-phase 2 time setting
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0x3F : 3.2us

3.2us phase duration

End of enumeration elements list.

HB2_T3OFF : Half Bridge 2-slew rate sequencer off-phase 3 time setting
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0x3F : 3.2us

3.2us phase duration

End of enumeration elements list.

HB2_T4OFF : Half Bridge 2-slew rate sequencer off-phase 4 time setting
bits : 24 - 30 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.


OFFSEQHB2IC

Turn-off Slewrate Sequencer Half Bridge 2 Current Control
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFSEQHB2IC OFFSEQHB2IC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB2_I1OFF HB2_I2OFF HB2_I3OFF HB2_I4OFF

HB2_I1OFF : Half Bridge 2-slew rate sequencer off-phase 1 current setting
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.

HB2_I2OFF : Half Bridge 2-slew rate sequencer off-phase 2 current setting
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.

HB2_I3OFF : Half Bridge 2-slew rate sequencer off-phase 3 current setting
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.

HB2_I4OFF : Half Bridge 2-slew rate sequencer off-phase 4 current setting
bits : 24 - 28 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.


ONSEQHB2TC

Turn-on Slewrate Sequencer Half Bridge 2 Time Control
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ONSEQHB2TC ONSEQHB2TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB2_T1ON HB2_T2ON HB2_T3ON HB2_T4ON

HB2_T1ON : Half Bridge 2-slew rate sequencer on-phase 1 time setting
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.

HB2_T2ON : Half Bridge 2-slew rate sequencer on-phase 2 time setting
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0x3F : 3.2us

3.2us phase duration

End of enumeration elements list.

HB2_T3ON : Half Bridge 2-slew rate sequencer on-phase 3 time setting
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0x3F : 3.2us

3.2us phase duration

End of enumeration elements list.

HB2_T4ON : Half Bridge 2-slew rate sequencer on-phase 4 time setting
bits : 24 - 30 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.


ONSEQHB2IC

Turn-on Slewrate Sequencer Half Bridge 2 Current Control
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ONSEQHB2IC ONSEQHB2IC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB2_I1ON HB2_I2ON HB2_I3ON HB2_I4ON

HB2_I1ON : Half Bridge 2-slew rate sequencer on-phase 1 current setting
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.

HB2_I2ON : Half Bridge 2-slew rate sequencer on-phase 2 current setting
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.

HB2_I3ON : Half Bridge 2-slew rate sequencer on-phase 3 current setting
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.

HB2_I4ON : Half Bridge 2-slew rate sequencer on-phase 4 current setting
bits : 24 - 28 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.


CTRL3

H-Bridge Driver Control 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL3 CTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSMONVTH DRV_CCP_TIMSEL DRV_CCP_TMUL DRV_CCP_DIS

DSMONVTH : Voltage Threshold for Drain-Source Monitoring of external FETs
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0b000 : 0.125_V

Threshold 0 for VDS at 0.125 V

0b001 : 0.25_V

Threshold 1 for VDS at 0.25 V

0b010 : 0.50_V

Threshold 2 for VDS at 0.50 V

0b011 : 0.75_V

Threshold 3 for VDS at 0.75 V

0b100 : 1.00_V

Threshold 4 for VDS at 1.00 V

0b101 : 1.25_V

Threshold 5 for VDS at 1.25 V

0b110 : 1.50_V

Threshold 6 for VDS at 1.50 V

0b111 : 1.75_V

Threshold 7 for VDS at 1.75 V

End of enumeration elements list.

DRV_CCP_TIMSEL : Minimum cross conduction protection time setting
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0b00 : 0.2us

200ns cross conduction protection time

0b01 : 0.4us

400ns cross conduction protection time

0b10 : 0.8us

800ns cross conduction protection time

0b11 : 1.6us

1.6us cross conduction protection time

End of enumeration elements list.

DRV_CCP_TMUL : Multiplier bits for cross conduction time settings in register DRV_CCP_TIMSEL
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0b00 : MUL1

DRV_CCP_TIMSEL value is multiplied by 1

0b01 : MUL2

DRV_CCP_TIMSEL value is multiplied by 2

0b10 : MUL4

DRV_CCP_TIMSEL value is multiplied by 4

0b11 : MUL8

DRV_CCP_TIMSEL value is multiplied by 8

End of enumeration elements list.

DRV_CCP_DIS : Dynamic cross conduction protection Disable
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

0b0 : CCP Enable

dynamic ccp is active.

0b1 : CCP Disable

dynamic ccp is disabled, delayed gate clamp remains active.

End of enumeration elements list.


SEQAFHB2IC

Slewrate Sequencer-Active Freewheeling- Half Bridge 2 Current Control
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQAFHB2IC SEQAFHB2IC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB2AF_IOFF HB2AF_ION

HB2AF_IOFF : Half Bridge 2-active freewheeling-slew rate sequencer off-phase current setting
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.

HB2AF_ION : Half Bridge 2-active freewheeling-slew rate sequencer on-phase current setting
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.


SEQAFHB2CD

Slewrate Sequencer-Active Freewheeling- Half Bridge 2 Clamping Current Delay
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQAFHB2CD SEQAFHB2CD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB2AF_TDICLMPOFF HB2AF_TDICLMPON

HB2AF_TDICLMPOFF : Clamping current delay during active freewheeling for switch off
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.

HB2AF_TDICLMPON : Clamping current delay during active freewheeling for switch on
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.


ASEQC

Adaptive Slewrate Sequencer Control Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASEQC ASEQC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1ASMONEN HB1ASMOFFEN HB1OPTONACT HB1OPTOFFACT HB1ONHYSTEN HB1OFFHYSTEN HB2ASMONEN HB2ASMOFFEN HB2OPTONACT HB2OPTOFFACT HB2ONHYSTEN HB2OFFHYSTEN

HB1ASMONEN : Half Bridge 1 Adaptive Sequencer Mode for Switch On Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0x0 : Disable

adaptive slew rate sequencer is disabled

0x1 : Enable

adaptive slew rate sequencer is enabled

End of enumeration elements list.

HB1ASMOFFEN : Half Bridge 1 Adaptive Sequencer Mode for Switch Off Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0x0 : Disable

adaptive slew rate sequencer is disabled

0x1 : Enable

adaptive slew rate sequencer is enabled

End of enumeration elements list.

HB1OPTONACT : Half Bridge 1 Optimizer for Switch On Active Bit
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0x0 : OFF

current optimizer is not active

0x1 : ON

current optimizer is active

End of enumeration elements list.

HB1OPTOFFACT : Half Bridge 1 Optimizer for Switch Off Active Bit
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0x0 : OFF

current optimizer is not active

0x1 : ON

current optimizer is active

End of enumeration elements list.

HB1ONHYSTEN : Half Bridge 1 Optimizer Hysteresis for Switch On Enable Bit
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0x0 : OFF

current optimizer hysteresis is not enabled

0x1 : ON

current optimizer hysteresis is enabled

End of enumeration elements list.

HB1OFFHYSTEN : Half Bridge 1 Optimizer Hysteresis for Switch Off Enable Bit
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0x0 : OFF

current optimizer hysteresis is not enabled

0x1 : ON

current optimizer hysteresis is enabled

End of enumeration elements list.

HB2ASMONEN : Half Bridge 2 Adaptive Sequencer Mode for Switch On Enable
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0x0 : Disable

adaptive slew rate sequencer is disabled

0x1 : Enable

adaptive slew rate sequencer is enabled

End of enumeration elements list.

HB2ASMOFFEN : Half Bridge 2 Adaptive Sequencer Mode for Switch Off Enable
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

0x0 : Disable

adaptive slew rate sequencer is disabled

0x1 : Enable

adaptive slew rate sequencer is enabled

End of enumeration elements list.

HB2OPTONACT : Half Bridge 2 Optimizer for Switch On Active Bit
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

0x0 : OFF

current optimizer is not active

0x1 : ON

current optimizer is active

End of enumeration elements list.

HB2OPTOFFACT : Half Bridge 2 Optimizer for Switch Off Active Bit
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

0x0 : OFF

current optimizer is not active

0x1 : ON

current optimizer is active

End of enumeration elements list.

HB2ONHYSTEN : Half Bridge 2 Optimizer Hysteresis for Switch On Enable Bit
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

0x0 : OFF

current optimizer hysteresis is not enabled

0x1 : ON

current optimizer hysteresis is enabled

End of enumeration elements list.

HB2OFFHYSTEN : Half Bridge 2 Optimizer Hysteresis for Switch Off Enable Bit
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

0x0 : OFF

current optimizer hysteresis is not enabled

0x1 : ON

current optimizer hysteresis is enabled

End of enumeration elements list.


ASEQSTS

Adaptive Slewrate Sequencer Status Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASEQSTS ASEQSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1T1OFFMAX HB1I1OFFMAX HB1T1OFFMIN HB1I1OFFMIN HB1T12ONMAX HB1I1ONMAX HB1T12ONMIN HB1I1ONMIN HB1OFFMF HB1ONMF HB2T1OFFMAX HB2I1OFFMAX HB2T1OFFMIN HB2I1OFFMIN HB2T12ONMAX HB2I1ONMAX HB2T12ONMIN HB2I1ONMIN HB2OFFMF HB2ONMF

HB1T1OFFMAX : Half Bridge 1-T1 Off Max Value reached
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Max Value not reached

0x1 : Error

Max Value reached

End of enumeration elements list.

HB1I1OFFMAX : Half Bridge 1-I1 Off Max Value reached
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Max Value not reached

0x1 : Error

Max Value reached

End of enumeration elements list.

HB1T1OFFMIN : Half Bridge 1-T1 Off Min Value reached
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Min Value not reached

0x1 : Error

Min Value reached

End of enumeration elements list.

HB1I1OFFMIN : Half Bridge 1-I1 Off Min Value reached
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Min Value not reached

0x1 : Error

Min Value reached

End of enumeration elements list.

HB1T12ONMAX : Half Bridge 1-T12 On Max Value reached
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Max Value not reached

0x1 : Error

Max Value reached

End of enumeration elements list.

HB1I1ONMAX : Half Bridge 1-I1 On Max Value reached
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Max Value not reached

0x1 : Error

Max Value reached

End of enumeration elements list.

HB1T12ONMIN : Half Bridge 1-T12 On Min Value reached
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Min Value not reached

0x1 : Error

Min Value reached

End of enumeration elements list.

HB1I1ONMIN : Half Bridge 1-I1 On Min Value reached
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Min Value not reached

0x1 : Error

Min Value reached

End of enumeration elements list.

HB1OFFMF : Half Bridge 1-Off Adaptive Mode Measurement Failure
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

No Measurement Failure

0x1 : Error

Measurement Failure

End of enumeration elements list.

HB1ONMF : Half Bridge 1-On Adaptive Mode Measurement Failure
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

No Measurement Failure

0x1 : Error

Measurement Failure

End of enumeration elements list.

HB2T1OFFMAX : Half Bridge 2-T1 Off Max Value reached
bits : 16 - 15 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Max Value not reached

0x1 : Error

Max Value reached

End of enumeration elements list.

HB2I1OFFMAX : Half Bridge 2-I1 Off Max Value reached
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Max Value not reached

0x1 : Error

Max Value reached

End of enumeration elements list.

HB2T1OFFMIN : Half Bridge 2-T1 Off Min Value reached
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Min Value not reached

0x1 : Error

Min Value reached

End of enumeration elements list.

HB2I1OFFMIN : Half Bridge 2-I1 Off Min Value reached
bits : 19 - 18 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Min Value not reached

0x1 : Error

Min Value reached

End of enumeration elements list.

HB2T12ONMAX : Half Bridge 2-T12 On Max Value reached
bits : 20 - 19 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Max Value not reached

0x1 : Error

Max Value reached

End of enumeration elements list.

HB2I1ONMAX : Half Bridge 2-I1 On Max Value reached
bits : 21 - 20 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Max Value not reached

0x1 : Error

Max Value reached

End of enumeration elements list.

HB2T12ONMIN : Half Bridge 2-T12 On Min Value reached
bits : 22 - 21 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Min Value not reached

0x1 : Error

Min Value reached

End of enumeration elements list.

HB2I1ONMIN : Half Bridge 2-I1 On Min Value reached
bits : 23 - 22 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

Min Value not reached

0x1 : Error

Min Value reached

End of enumeration elements list.

HB2OFFMF : Half Bridge 2- Off Adaptive Mode Measurement Failure
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

No Measurement Failure

0x1 : Error

Measurement Failure

End of enumeration elements list.

HB2ONMF : Half Bridge 2- On Adaptive Mode Measurement Failure
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

0x0 : no Error

No Measurement Failure

0x1 : Error

Measurement Failure

End of enumeration elements list.


ONASEQTMIN

Turn ON Adaptive Slewrate Sequencer Minimum Time Setting
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ONASEQTMIN ONASEQTMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T12ONMIN

T12ONMIN : Slew rate sequencer on-phase 12 min. time setting
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.


OFFASEQTMIN

Turn OFF Adaptive Slewrate Sequencer Minimum Time Setting
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFASEQTMIN OFFASEQTMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1OFFMIN HB1T1OFFADDDLY HB2T1OFFADDDLY

T1OFFMIN : Slew rate sequencer off-phase 1 min. time setting
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.

HB1T1OFFADDDLY : HB1 adaptive sequencer T1OFF additional delay setting.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0ns

0ns added to HB1T1OFF

0xF : 750ns

750ns added to HB1T1OFF

End of enumeration elements list.

HB2T1OFFADDDLY : HB2 adaptive sequencer T1OFF additional delay setting.
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0x0 : 0ns

0ns added to HB2T1OFF

0xF : 750ns

750ns added to HB2T1OFF

End of enumeration elements list.


ASEQIONMIN

Adaptive Slewrate Sequencer On Phase Minimum Current Setting
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASEQIONMIN ASEQIONMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I1ONMIN

I1ONMIN : Slew rate sequencer on-phase 1 min. current setting
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.


ASEQIOFFMIN

Adaptive Slewrate Sequencer Off Phase Minimum Current Setting
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASEQIOFFMIN ASEQIOFFMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I1OFFMIN

I1OFFMIN : Slew rate sequencer off-phase 1 min. current setting
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.


ONASEQTMAX

Adaptive Slewrate On Sequencer Maximum Time Setting
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ONASEQTMAX ONASEQTMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T12ONMAX

T12ONMAX : Slew rate sequencer on-phase 12 max. time setting
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.


OFFASEQTMAX

Adaptive Slewrate Off Sequencer Maximum Time Setting
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFASEQTMAX OFFASEQTMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1OFFMAX

T1OFFMAX : Slew rate sequencer off-phase 1 max. time setting
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.


ASEQIONMAX

Adaptive Slewrate Sequencer On Phase Maximum Current Setting
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASEQIONMAX ASEQIONMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I1ONMAX

I1ONMAX : Slew rate sequencer on-phase 1 max. current setting
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.


ASEQIOFFMAX

Adaptive Slewrate Sequencer Off Phase Maximum Current Setting
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASEQIOFFMAX ASEQIOFFMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I1OFFMAX

I1OFFMAX : Slew rate sequencer off-phase 1 max. current setting
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x0 : min. current

IDISCHGmin

0x3F : max. current

IDISCHGmax

End of enumeration elements list.


HB1ASEQONVAL

Half Bridge 1 Adaptive Sequencer On Values
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HB1ASEQONVAL HB1ASEQONVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1_T12ONCNT HB1_I1ONVAL HB1_T3ONCNT HB1_T3MERR HB1_ONVALVF HB1_ONVALVF_CLR

HB1_T12ONCNT : Half Bridge 1-Turn on slew rate-time value measured from beginning of phase 1 to end of phase 2.
bits : 0 - 6 (7 bit)
access : read-only

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.

HB1_I1ONVAL : Half Bridge 1-slew rate sequencer on-phase 1 current setting
bits : 8 - 12 (5 bit)
access : read-only

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.

HB1_T3ONCNT : Half Bridge 1-Turn on slew rate-time value measured from beginning of phase 3 to end of phase 3.
bits : 16 - 20 (5 bit)
access : read-only

Enumeration:

0x0 : 50ns

50ns phase duration

0x3F : 3.2us

3.2us phase duration

End of enumeration elements list.

HB1_T3MERR : Half Bridge 1-T3 Measurement Error.
bits : 22 - 21 (0 bit)
access : read-only

Enumeration:

0b0 : VALID

T3 value valid

0b1 : ERROR

T3 value not valid - Measurement Error

End of enumeration elements list.

HB1_ONVALVF : Half Bridge 1-Turn on slew rate values - Valid Flag.
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

0b0 : NOT VALID

no new valid LS1/HS1_ON values available

0b1 : VALID

LS1/HS1_ON fields contain valid data and have not been read

End of enumeration elements list.

HB1_ONVALVF_CLR : Half Bridge 1-Turn on slew rate values Valid Flag - Clear.
bits : 31 - 30 (0 bit)
access : write-only

Enumeration:

0b0 : NOT CLEAR

no clear of HB1_ONVALVF flag

0b1 : CLEAR

clear of HB1_ONVALVF flag

End of enumeration elements list.


HB1ASEQOFFVAL

Half Bridge 1 Adaptive Sequencer Off Values
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HB1ASEQOFFVAL HB1ASEQOFFVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1_T1OFFCNT HB1_I1OFFVAL HB1_T2OFFCNT HB1_T2MERR HB1_OFFVALVF HB1_OFFVALVF_CLR

HB1_T1OFFCNT : Half Bridge 1-Turn off slew rate-time value measured from beginning of phase 1 to end of phase 1.
bits : 0 - 6 (7 bit)
access : read-only

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.

HB1_I1OFFVAL : Half Bridge 1-slew rate sequencer off-phase 1 current setting
bits : 8 - 12 (5 bit)
access : read-only

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.

HB1_T2OFFCNT : Half Bridge 1-Turn off slew rate-time value measured from beginning of phase 2 to end of phase 2.
bits : 16 - 20 (5 bit)
access : read-only

Enumeration:

0x0 : 50ns

50ns phase duration

0x3F : 3.2us

3.2us phase duration

End of enumeration elements list.

HB1_T2MERR : Half Bridge 1-T2 Measurement Error.
bits : 22 - 21 (0 bit)
access : read-only

Enumeration:

0b0 : VALID

T2 value valid

0b1 : ERROR

T2 value not valid - Measurement Error

End of enumeration elements list.

HB1_OFFVALVF : Half Bridge 1-Turn off slew rate values - Valid Flag.
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

0b0 : NOT VALID

no new valid LS1/HS1_OFF values available

0b1 : VALID

LS1/HS1_OFF fields contain valid data and have not been read

End of enumeration elements list.

HB1_OFFVALVF_CLR : Half Bridge 1-Turn off slew rate values Valid Flag - Clear.
bits : 31 - 30 (0 bit)
access : write-only

Enumeration:

0b0 : NOT CLEAR

no clear of HB1_OFFVALVF flag

0b1 : CLEAR

clear of HB1_OFFVALVF flag

End of enumeration elements list.


PWMSRCSEL

PWM Source Selection Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMSRCSEL PWMSRCSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS1_SRC_SEL LS2_SRC_SEL HS1_SRC_SEL HS2_SRC_SEL

LS1_SRC_SEL : LS1 PWM Source Selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0b00 : CC60

PWM output of CCU6

0b01 : CC61

PWM output of CCU6

0b10 : COUT60

PWM output of CCU6

0b11 : COUT61

PWM output of CCU6

End of enumeration elements list.

LS2_SRC_SEL : LS2 PWM Source Selection
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0b00 : CC60

PWM output of CCU6

0b01 : CC61

PWM output of CCU6

0b10 : COUT60

PWM output of CCU6

0b11 : COUT61

PWM output of CCU6

End of enumeration elements list.

HS1_SRC_SEL : HS1 PWM Source Selection
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0b00 : CC60

PWM output of CCU6

0b01 : CC61

PWM output of CCU6

0b10 : COUT60

PWM output of CCU6

0b11 : COUT61

PWM output of CCU6

End of enumeration elements list.

HS2_SRC_SEL : HS2 PWM Source Selection
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0b00 : CC60

PWM output of CCU6

0b01 : CC61

PWM output of CCU6

0b10 : COUT60

PWM output of CCU6

0b11 : COUT61

PWM output of CCU6

End of enumeration elements list.


HB2ASEQONVAL

Half Bridge 2 Adaptive Sequencer On Values
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HB2ASEQONVAL HB2ASEQONVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB2_T12ONCNT HB2_I1ONVAL HB2_T3ONCNT HB2_T3MERR HB2_ONVALVF HB2_ONVALVF_CLR

HB2_T12ONCNT : Half Bridge 2-Turn on slew rate-time value measured from beginning of phase 1 to end of phase 2.
bits : 0 - 6 (7 bit)
access : read-only

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.

HB2_I1ONVAL : Half Bridge 2-slew rate sequencer on-phase 1 current setting
bits : 8 - 12 (5 bit)
access : read-only

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.

HB2_T3ONCNT : Half Bridge 2-Turn on slew rate-time value measured from beginning of phase 3 to end of phase 3.
bits : 16 - 20 (5 bit)
access : read-only

Enumeration:

0x0 : 50ns

50ns phase duration

0x3F : 3.2us

3.2us phase duration

End of enumeration elements list.

HB2_T3MERR : Half Bridge 2-T3 Measurement Error.
bits : 22 - 21 (0 bit)
access : read-only

Enumeration:

0b0 : VALID

T3 value valid

0b1 : ERROR

T3 value not valid - Measurement Error

End of enumeration elements list.

HB2_ONVALVF : Half Bridge 2-Turn on slew rate values - Valid Flag.
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

0b0 : NOT VALID

no new valid LS2/HS2_ON values available

0b1 : VALID

LS2/HS2_ON fields contain valid data and have not been read

End of enumeration elements list.

HB2_ONVALVF_CLR : Half Bridge 2-Turn on slew rate values Valid Flag - Clear.
bits : 31 - 30 (0 bit)
access : write-only

Enumeration:

0b0 : NOT CLEAR

no clear of HB2_ONVALVF flag

0b1 : CLEAR

clear of HB2_ONVALVF flag

End of enumeration elements list.


HB2ASEQOFFVAL

Half Bridge 2 Adaptive Sequencer Off Values
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HB2ASEQOFFVAL HB2ASEQOFFVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB2_T1OFFCNT HB2_I1OFFVAL HB2_T2OFFCNT HB2_T2MERR HB2_OFFVALVF HB2_OFFVALVF_CLR

HB2_T1OFFCNT : Half Bridge 2-Turn off slew rate-time value measured from beginning of phase 1 to end of phase 1.
bits : 0 - 6 (7 bit)
access : read-only

Enumeration:

0x0 : 50ns

50ns phase duration

0xFF : 12.8us

12.8us phase duration

End of enumeration elements list.

HB2_I1OFFVAL : Half Bridge 2-slew rate sequencer off-phase 1 current setting
bits : 8 - 12 (5 bit)
access : read-only

Enumeration:

0x0 : min. current

ICHGmin

0x3F : max. current

ICHGmax

End of enumeration elements list.

HB2_T2OFFCNT : Half Bridge 2-Turn off slew rate-time value measured from beginning of phase 2 to end of phase 2.
bits : 16 - 20 (5 bit)
access : read-only

Enumeration:

0x0 : 50ns

50ns phase duration

0x3F : 3.2us

3.2us phase duration

End of enumeration elements list.

HB2_T2MERR : Half Bridge 2-T2 Measurement Error.
bits : 22 - 21 (0 bit)
access : read-only

Enumeration:

0b0 : VALID

T2 value valid

0b1 : ERROR

T2 value not valid - Measurement Error

End of enumeration elements list.

HB2_OFFVALVF : Half Bridge 2-Turn off slew rate values - Valid Flag.
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

0b0 : NOT VALID

no new valid LS2/HS2_OFF values available

0b1 : VALID

LS2/HS2_OFF fields contain valid data and have not been read

End of enumeration elements list.

HB2_OFFVALVF_CLR : Half Bridge 2-Turn off slew rate values Valid Flag - Clear.
bits : 31 - 30 (0 bit)
access : write-only

Enumeration:

0b0 : NOT CLEAR

no clear of HB2_OFFVALVF flag

0b1 : CLEAR

clear of HB2_OFFVALVF flag

End of enumeration elements list.


ASEQERRCNT

Adaptive Slewrate Sequencer Error Counter Control Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASEQERRCNT ASEQERRCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1T1OFFERRCNT HB1T12ONERRCNT HB1MFERRCNT HB2T1OFFERRCNT HB2T12ONERRCNT HB2MFERRCNT

HB1T1OFFERRCNT : Half Bridge 1-T1 Off Error Counter Setting
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0b00 : 2 Events

Error Flag is set after 2 Events

0b01 : 4 Events

Error Flag is set after 4 Events

0b10 : 8 Events

Error Flag is set after 8 Events

0b11 : 15 Events

Error Flag is set after 15 Events

End of enumeration elements list.

HB1T12ONERRCNT : Half Bridge 1-T12 On Error Counter Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0b00 : 2 Events

Error Flag is set after 2 Events

0b01 : 4 Events

Error Flag is set after 4 Events

0b10 : 8 Events

Error Flag is set after 8 Events

0b11 : 15 Events

Error Flag is set after 15 Events

End of enumeration elements list.

HB1MFERRCNT : Half Bridge 1-Measurement Failure Error Counter Setting
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0b00 : 2 Events

Error Flag is set after 2 Events

0b01 : 4 Events

Error Flag is set after 4 Events

0b10 : 8 Events

Error Flag is set after 8 Events

0b11 : 15 Events

Error Flag is set after 15 Events

End of enumeration elements list.

HB2T1OFFERRCNT : Half Bridge 2-T1 Off Error Counter Setting
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0b00 : 2 Events

Error Flag is set after 2 Events

0b01 : 4 Events

Error Flag is set after 4 Events

0b10 : 8 Events

Error Flag is set after 8 Events

0b11 : 15 Events

Error Flag is set after 15 Events

End of enumeration elements list.

HB2T12ONERRCNT : Half Bridge 2-T12 On Error Counter Setting
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0b00 : 2 Events

Error Flag is set after 2 Events

0b01 : 4 Events

Error Flag is set after 4 Events

0b10 : 8 Events

Error Flag is set after 8 Events

0b11 : 15 Events

Error Flag is set after 15 Events

End of enumeration elements list.

HB2MFERRCNT : Half Bridge 2-Measurement Failure Error Counter Setting
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0b00 : 2 Events

Error Flag is set after 2 Events

0b01 : 4 Events

Error Flag is set after 4 Events

0b10 : 8 Events

Error Flag is set after 8 Events

0b11 : 15 Events

Error Flag is set after 15 Events

End of enumeration elements list.


DCTRIM_DRVx

Current Trimming of Driver
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCTRIM_DRVx DCTRIM_DRVx read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPENS_HS COMPENS_LS

COMPENS_HS : Current Settings for High Side Charge Current Compensation
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0b000 : DISABLE

Dynamic Compensation is disabled.

0b001 : gain_1

gain setting 1 (min)

0b010 : gain_2

gain setting 2

0b011 : gain_3

gain setting 3

0b100 : gain_4

gain setting 4 (max)

End of enumeration elements list.

COMPENS_LS : Gain Settings for Low Side Charge Current Compensation
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0b000 : DISABLE

Dynamic Compensation is disabled.

0b001 : gain_1

gain setting 1 (min)

0b010 : gain_2

gain setting 2

0b011 : gain_3

gain setting 3

0b100 : gain_4

gain setting 4 (max)

End of enumeration elements list.


IRQS

H-Bridge Driver Interrupt Status
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQS IRQS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1_ASEQ_IS HB2_ASEQ_IS LS1_DS_IS LS1_DS_STS LS1_OC_IS LS2_DS_IS LS2_DS_STS LS2_OC_IS HS1_DS_IS HS1_DS_STS HS1_OC_IS HS2_DS_IS HS2_DS_STS HS2_OC_IS SEQ_ERR_IS

HB1_ASEQ_IS : Half Bridge 1 Adaptive Sequencer Interrupt Status
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : no error in SEQ

no sequencer Error detected.

0b1 : error in SEQ

sequencer Error detected.

End of enumeration elements list.

HB2_ASEQ_IS : Half Bridge 2 Adaptive Sequencer Interrupt Status
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : no error in SEQ

no sequencer Error detected.

0b1 : error in SEQ

sequencer Error detected.

End of enumeration elements list.

LS1_DS_IS : Low Side Driver 1 Drain Source Monitoring Interrupt Status in OFF-State
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : no short on external FET

no short detected.

0b1 : short on external FET detected

short detected.

End of enumeration elements list.

LS1_DS_STS : Low Side Driver 1 Drain Source Monitoring Status in OFF-State
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : no short on external FET

no short detected.

0b1 : short on external FET detected

short detected.

End of enumeration elements list.

LS1_OC_IS : External Low Side 1 FET Over-current Interrupt Status
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : no Over-current

no over-current Condition occurred.

0b1 : Over-current

over-current occurred switch is automatically shutdown.

End of enumeration elements list.

LS2_DS_IS : Low Side Driver 2 Drain Source Monitoring Interrupt Status in OFF-State
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

0b0 : no short on external FET

no short detected.

0b1 : short on external FET detected

short detected.

End of enumeration elements list.

LS2_DS_STS : Low Side Driver 2 Drain Source Monitoring Status in OFF-State
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

0b0 : no short on external FET

no short detected.

0b1 : short on external FET detected

short detected.

End of enumeration elements list.

LS2_OC_IS : External Low Side 2 FET Over-current Interrupt Status
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : no Over-current

no over-current Condition occurred.

0b1 : Over-current

over-current occurred switch is automatically shutdown.

End of enumeration elements list.

HS1_DS_IS : High Side Driver 1 Drain Source Monitoring Interrupt Status in OFF-State
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

0b0 : no short on external FET

no short detected.

0b1 : short on external FET detected

short detected.

End of enumeration elements list.

HS1_DS_STS : High Side Driver 1 Drain Source Monitoring Status in OFF-State
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

0b0 : no short on external FET

no short detected.

0b1 : short on external FET detected

short detected.

End of enumeration elements list.

HS1_OC_IS : External High Side 1 FET Over-current Interrupt Status
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

0b0 : no Over-current

no over-current Condition occurred.

0b1 : Over-current

over-current occurred switch is automatically shutdown.

End of enumeration elements list.

HS2_DS_IS : High Side Driver 2 Drain Source Monitoring Interrupt Status in OFF-State
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

0b0 : no short on external FET

no short detected.

0b1 : short on external FET detected

short detected.

End of enumeration elements list.

HS2_DS_STS : High Side Driver 2 Drain Source Monitoring Status in OFF-State
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

0b0 : no short on external FET

no short detected.

0b1 : short on external FET detected

short detected.

End of enumeration elements list.

HS2_OC_IS : External High Side 2 FET Over-current Interrupt Status
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

0b0 : no Over-current

no over-current Condition occurred.

0b1 : Over-current

over-current occurred switch is automatically shut down.

End of enumeration elements list.

SEQ_ERR_IS : Driver Sequence Error Interrupt Status
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

0b0 : Driver Sequence ok

no cross current

0b1 : Driver Sequence fail

HS and LS of same bridge concurrently activated, output protection activated

End of enumeration elements list.


IRQCLR

H-Bridge Driver Interrupt Status Clear Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCLR IRQCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1_ASEQ_ISC HB2_ASEQ_ISC LS1_DS_ISC LS1_DS_SC LS1_OC_ISC LS2_DS_ISC LS2_DS_SC LS2_OC_ISC HS1_DS_ISC HS1_DS_SC HS1_OC_ISC HS2_DS_ISC HS2_DS_SC HS2_OC_ISC SEQ_ERR_ISC

HB1_ASEQ_ISC : Half Bridge 1 Adaptive Sequencer Interrupt Status Clear
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

HB2_ASEQ_ISC : Half Bridge 2 Adaptive Sequencer Interrupt Status Clear
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

LS1_DS_ISC : Low Side Driver 1 Drain Source Monitoring Interrupt Status Clear in OFF-State
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

LS1_DS_SC : Low Side Driver 1 Drain Source Monitoring Status Clear in OFF-State
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

LS1_OC_ISC : External Low Side 1 FET Over-current Status Clear
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

LS2_DS_ISC : Low Side Driver 2 Drain Source Monitoring Interrupt Status Clear in OFF-State
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

LS2_DS_SC : Low Side Driver 2 Drain Source Monitoring Status Clear in OFF-State
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

LS2_OC_ISC : External Low Side 2 FET Over-current Status Clear
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

HS1_DS_ISC : High Side Driver 1 Drain Source Monitoring Interrupt Status Clear in OFF-State
bits : 20 - 19 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

HS1_DS_SC : High Side Driver 1 Drain Source Monitoring Status Clear in OFF-State
bits : 21 - 20 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

HS1_OC_ISC : External High Side 1 FET Over-current Status Clear
bits : 22 - 21 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

HS2_DS_ISC : High Side Driver 2 Drain Source Monitoring Interrupt Status Clear in OFF-State
bits : 28 - 27 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

HS2_DS_SC : High Side Driver 2 Drain Source Monitoring Status Clear in OFF-State
bits : 29 - 28 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

HS2_OC_ISC : External High Side 2 FET Over-current Status Clear
bits : 30 - 29 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

SEQ_ERR_ISC : Driver Sequence Error Status Clear
bits : 31 - 30 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.


IRQEN

H-Bridge Driver Control
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQEN IRQEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB1_ASEQ_IEN HB2_ASEQ_IEN LS1_DS_IEN LS1_OC_IEN LS2_DS_IEN LS2_OC_IEN HS1_DS_IEN HS1_OC_IEN HS2_DS_IEN HS2_OC_IEN SEQ_ERR_IEN

HB1_ASEQ_IEN : Half Bridge 1 Adaptive Sequencer Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

HB2_ASEQ_IEN : Half Bridge 2 Adaptive Sequencer Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

LS1_DS_IEN : Low Side Driver 1 Drain Source Monitoring Interrupt Enable in OFF-State
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

LS1_OC_IEN : External Low Side 1 FET Over-current Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

LS2_DS_IEN : Low Side Driver 2 Drain Source Monitoring Interrupt Enable in OFF-State
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

LS2_OC_IEN : External Low Side 2 FET Over-current Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

HS1_DS_IEN : High Side Driver 1 Drain Source Monitoring Interrupt Enable in OFF-State
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

HS1_OC_IEN : External High Side 1 FET Over-current Interrupt Enable
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

HS2_DS_IEN : High Side Driver 2 Drain Source Monitoring Interrupt Enable in OFF-State
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

HS2_OC_IEN : External High Side 2 FET Over-current Interrupt Enable
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

SEQ_ERR_IEN : Driver Sequence Error Interrupt Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.



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