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CCU6

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CC63R

CMPMODIF

CC60SR

CC61SR

CC62SR

CC63SR

T12PR

T13PR

T12DTC

TCTR0

CC60R

CC61R

CC62R

TCTR4

T12MSEL

IEN

INP

ISS

PSLR

MCMCTR

TCTR2

MODCTR

TRPCTR

MCMOUT

IS

PISEL0

PISEL2

T12

T13

MCMOUTS

CMPSTAT

ISR


CC63R

Capture/Compare Register for Channel CC63
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC63R CC63R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCV

CCV : Channel CC63 Compare Value Low Byte
bits : 0 - 14 (15 bit)
access : read-only


CMPMODIF

Compare State Modification Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPMODIF CMPMODIF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCC60S MCC61S MCC62S MCC63S MCC60R MCC61R MCC62R MCC63R

MCC60S : Capture/Compare Status Modification Bit 0 (Set)
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b00 : Not_changed

Bit CC60ST is not changed.

0b01 : Set

Bit CC60ST is set.

0b10 : Reset

Bit CC60ST is reset.

End of enumeration elements list.

MCC61S : Capture/Compare Status Modification Bit 1 (Set)
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

0b00 : Not_changed

Bit CC61ST is not changed.

0b01 : Set

Bit CC61ST is set.

0b10 : Reset

Bit CC61ST is reset.

End of enumeration elements list.

MCC62S : Capture/Compare Status Modification Bit 2 (Set)
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

0b00 : Not_changed

Bit CC62ST is not changed.

0b01 : Set

Bit CC62ST is set.

0b10 : Reset

Bit CC62ST is reset.

End of enumeration elements list.

MCC63S : Capture/Compare Status Modification Bits (Set)
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

0b00 : Not_changed

Bit CC63ST is not changed.

0b01 : Set

Bit CC63ST is set.

0b10 : Reset

Bit CC63ST is reset.

End of enumeration elements list.

MCC60R : Capture/Compare Status Modification Bit 0(Reset)
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

0b00 : Not_changed

Bit CC60ST is not changed.

0b01 : Set

Bit CC60ST is set.

0b10 : Reset

Bit CC60ST is reset.

End of enumeration elements list.

MCC61R : Capture/Compare Status Modification Bit 1(Reset)
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

0b00 : Not_changed

Bit CC61ST is not changed.

0b01 : Set

Bit CC61ST is set.

0b10 : Reset

Bit CC61ST is reset.

End of enumeration elements list.

MCC62R : Capture/Compare Status Modification Bit 2(Reset)
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

0b00 : Not_changed

Bit CC62ST is not changed.

0b01 : Set

Bit CC62ST is set.

0b10 : Reset

Bit CC62ST is reset.

End of enumeration elements list.

MCC63R : Capture/Compare Status Modification Bits (Reset)
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

0b00 : Not_changed

Bit CC63ST is not changed.

0b01 : Set

Bit CC63ST is set.

0b10 : Reset

Bit CC63ST is reset.

End of enumeration elements list.


CC60SR

Capture/Compare Shadow Register for Channel CC60
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC60SR CC60SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCS

CCS : Shadow Register for Channel 0 Capture/Compare Value
bits : 0 - 14 (15 bit)
access : read-write


CC61SR

Capture/Compare Shadow Register for Channel CC61
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC61SR CC61SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCS

CCS : Shadow Register for Channel 1 Capture/Compare Value
bits : 0 - 14 (15 bit)
access : read-write


CC62SR

Capture/Compare Shadow Register for Channel CC62
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC62SR CC62SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCS

CCS : Shadow Register for Channel 2 Capture/Compare Value
bits : 0 - 14 (15 bit)
access : read-write


CC63SR

Capture/Compare Shadow Register for Channel CC63
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC63SR CC63SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCS

CCS : Shadow Register for Channel CC63 Compare Value
bits : 0 - 14 (15 bit)
access : read-write


T12PR

Timer T12 Period Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T12PR T12PR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T12PV

T12PV : T12 Period Value
bits : 0 - 14 (15 bit)
access : read-write


T13PR

Timer T13 Period Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T13PR T13PR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T13PV

T13PV : T13 Period Value
bits : 0 - 14 (15 bit)
access : read-write


T12DTC

Dead-Time Control Register for Timer T12 Low
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T12DTC T12DTC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTM DTE0 DTE1 DTE2 DTR0 DTR1 DTR2

DTM : Dead-Time
bits : 0 - 6 (7 bit)
access : read-write

DTE0 : Dead-Time Enable Bit 0
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay.

0b1 : Enabled

Dead-time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM.

End of enumeration elements list.

DTE1 : Dead-Time Enable Bit 1
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay.

0b1 : Enabled

Dead-time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM.

End of enumeration elements list.

DTE2 : Dead-Time Enable Bit 2
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay.

0b1 : Enabled

Dead-time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM.

End of enumeration elements list.

DTR0 : Dead-Time Run Indication Bit 0
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

0b0 : Zero

The value of the corresponding dead-time counter channel is 0.

0b1 : Not Zero

The value of the corresponding dead-time counter channel is not 0.

End of enumeration elements list.

DTR1 : Dead-Time Run Indication Bit 1
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

0b0 : Zero

The value of the corresponding dead-time counter channel is 0.

0b1 : Not Zero

The value of the corresponding dead-time counter channel is not 0.

End of enumeration elements list.

DTR2 : Dead-Time Run Indication Bit 2
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

0b0 : Zero

The value of the corresponding dead-time counter channel is 0.

0b1 : Not Zero

The value of the corresponding dead-time counter channel is not 0.

End of enumeration elements list.


TCTR0

Timer Control Register 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCTR0 TCTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T12CLK T12PRE T12R STE12 CDIR CTM T13CLK T13PRE T13R STE13

T12CLK : Timer T12 Input Clock Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0b000 : 1

fT12 = fCCU

0b001 : 2

fT12 = fCCU / 2

0b010 : 4

fT12 = fCCU / 4

0b011 : 8

fT12 = fCCU / 8

0b100 : 16

fT12 = fCCU / 16

0b101 : 32

fT12 = fCCU / 32

0b110 : 64

fT12 = fCCU / 64

0b111 : 128

fT12 = fCCU / 128

End of enumeration elements list.

T12PRE : Timer T12 Prescaler Bit
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

The additional prescaler for T12 is disabled.

0b1 : Enabled

The additional prescaler for T12 is enabled.

End of enumeration elements list.

T12R : Timer T12 Run Bit
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

0b0 : Stop

Timer T12 is stopped.

0b1 : Run

Timer T12 is running.

End of enumeration elements list.

STE12 : Timer T12 Shadow Transfer Enable
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

0b0 : Disabled

The shadow register transfer is disabled.

0b1 : Enabled

The shadow register transfer is enabled.

End of enumeration elements list.

CDIR : Count Direction of Timer T12
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

0b0 : UP

T12 counts up.

0b1 : DOWN

T12 counts down.

End of enumeration elements list.

CTM : T12 Operating Mode
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : Edge-aligned Mode

T12 always counts up and continues counting from zero after reaching the period value.

0b1 : Center-aligned Mode

T12 counts down after detecting a period-match and counts up after detecting a one-match.

End of enumeration elements list.

T13CLK : Timer T13 Input Clock Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0b000 : 1

fT13 = fCCU

0b001 : 2

fT13 = fCCU / 2

0b010 : 4

fT13 = fCCU / 4

0b011 : 8

fT13 = fCCU / 8

0b100 : 16

fT13 = fCCU / 16

0b101 : 32

fT13 = fCCU / 32

0b110 : 64

fT13 = fCCU / 64

0b111 : 128

fT13 = fCCU / 128

End of enumeration elements list.

T13PRE : Timer T13 Prescaler Bit
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

The additional prescaler for T13 is disabled.

0b1 : Enabled

The additional prescaler for T13 is enabled.

End of enumeration elements list.

T13R : Timer T13 Run Bit
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

0b0 : Stop

Timer T13 is stopped.

0b1 : Run

Timer T13 is running.

End of enumeration elements list.

STE13 : Timer T13 Shadow Transfer Enable
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

0b0 : Disabled

The shadow register transfer is disabled.

0b1 : Enabled

The shadow register transfer is enabled.

End of enumeration elements list.


CC60R

Capture/Compare Register for Channel CC60
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC60R CC60R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCV

CCV : Channel 0 Capture/Compare Value
bits : 0 - 14 (15 bit)
access : read-only


CC61R

Capture/Compare Register for Channel CC61
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC61R CC61R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCV

CCV : Channel 1 Capture/Compare Value
bits : 0 - 14 (15 bit)
access : read-only


CC62R

Capture/Compare Register for Channel CC62
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC62R CC62R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCV

CCV : Channel 2 Capture/Compare Value
bits : 0 - 14 (15 bit)
access : read-only


TCTR4

Timer Control Register 4
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCTR4 TCTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T12RR T12RS T12RES DTRES T12CNT T12STR T12STD T13RR T13RS T13RES T13CNT T13STR T13STD

T12RR : Timer T12 Run Reset
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b0 : No influence

T12R is not influenced.

0b1 : T12R cleared

T12R is cleared, T12 stops counting.

End of enumeration elements list.

T12RS : Timer T12 Run Set
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

0b0 : No influence

T12R is not influenced.

0b1 : T12R set

T12R is set, T12 counts.

End of enumeration elements list.

T12RES : Timer T12 Reset
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

0b0 : No effect

No effect on T12.

0b1 : Zero

The T12 counter register is reset to zero. The switching of the output signals is according to the switching rules. Setting of T12RES has no impact on bit T12R.

End of enumeration elements list.

DTRES : Dead-Time Counter Reset
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

0b0 : No effect

No effect on the dead-time counters.

0b1 : Zero

The three dead-time counter channels are reset to zero.

End of enumeration elements list.

T12CNT : Timer T12 Count Event
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Count

If enabled (PISEL2), timer T12 counts one step.

End of enumeration elements list.

T12STR : Timer T12 Shadow Transfer Request
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : STE12 set

STE12 is set, enabling the shadow transfer.

End of enumeration elements list.

T12STD : Timer T12 Shadow Transfer Disable
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : STE12 reset

STE12 is reset without triggering the shadow transfer.

End of enumeration elements list.

T13RR : Timer T13 Run Reset
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

0b0 : No influence

T13R is not influenced.

0b1 : T13R cleared

T13R is cleared, T13 stops counting.

End of enumeration elements list.

T13RS : Timer T13 Run Set
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

0b0 : No influence

T13R is not influenced.

0b1 : T13R set

T13R is set, T13 counts.

End of enumeration elements list.

T13RES : Timer T13 Reset
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

0b0 : No effect

No effect on T13.

0b1 : Zero

The T13 counter register is reset to zero. The switching of the output signals is according to the switching rules. Setting of T13RES has no impact on bit T13R.

End of enumeration elements list.

T13CNT : Timer T13 Count Event
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Count

If enabled (PISEL2), timer T13 counts one step.

End of enumeration elements list.

T13STR : Timer T13 Shadow Transfer Request
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : STE13 set

STE13 is set, enabling the shadow transfer.

End of enumeration elements list.

T13STD : Timer T13 Shadow Transfer Disable
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : STE13 reset

STE13 is reset without triggering the shadow transfer.

End of enumeration elements list.


T12MSEL

T12 Capture/Compare Mode Select Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T12MSEL T12MSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSEL60 MSEL61 MSEL62 HSYNC DBYP

MSEL60 : Capture/Compare Mode Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0b0000 : Compare outputs disabled

Compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action.

0b0001 : Pin CC6n, pin COUT6n

Compare output on pin CC6n, pin COUT6n can be used for I/O. No capture action.

0b0010 : Pin COUT6n, Pin CC6n

Compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action.

0b0011 : Pins COUT6n and CC6n

Compare output on pins COUT6n and CC6n.

0b01XX : Double-Register Capture modes

see .

0b1000 : Hysteresis-like_mode

see . In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall Sensor mode.

0b11XX : Multi-Input_Capture_modes

see .

End of enumeration elements list.

MSEL61 : Capture/Compare Mode Selection
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0b0000 : Compare outputs disabled

Compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action.

0b0001 : Pin CC6n, pin COUT6n

Compare output on pin CC6n, pin COUT6n can be used for I/O. No capture action.

0b0010 : Pin COUT6n, Pin CC6n

Compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action.

0b0011 : Pins COUT6n and CC6n

Compare output on pins COUT6n and CC6n.

0b01XX : Double-Register Capture modes

see .

0b1000 : Hysteresis-like_mode

see . In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall Sensor mode.

0b11XX : Multi-Input_Capture_modes

see .

End of enumeration elements list.

MSEL62 : Capture/Compare Mode Selection
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0b0000 : Compare outputs disabled

Compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action.

0b0001 : Pin CC6n, pin COUT6n

Compare output on pin CC6n, pin COUT6n can be used for I/O. No capture action.

0b0010 : Pin COUT6n, Pin CC6n

Compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action.

0b0011 : Pins COUT6n and CC6n

Compare output on pins COUT6n and CC6n.

0b01XX : Double-Register Capture modes

see .

0b1000 : Hall Sensor mode

see . In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall Sensor mode.

0b1001 : Hysteresis-like_mode

see .

0b101X : Multi-Input_Capture_modes

see .

0b101X : Multi-Input_Capture_modes

see .

End of enumeration elements list.

HSYNC : Hall Synchronization
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0b000 : Any

Any edge at one of the inputs CCPOSx (x = 0, 1, 2) triggers the sampling.

0b001 : T13 compare-match

A T13 compare-match triggers the sampling.

0b010 : T13 period-match

A T13 period-match triggers the sampling.

0b011 : Hall

The Hall sampling triggered by hardware sources is switched off.

0b100 : T12 period-match

A T12 period-match (while counting up) triggers the sampling.

0b101 : T12 one-match

A T12 one-match (while counting down) triggers the sampling.

0b110 : T12 compare-match UP

A T12 compare-match of channel 0 (while counting up) triggers the sampling.

0b111 : T12 compare-match DOWN

A T12 compare-match of channel 0 (while counting down) triggers the sampling.

End of enumeration elements list.

DBYP : Delay Bypass
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0b0 : Not active

The delay bypass is not active. The dead-time counter DTC0 is generating a delay after the source signal becomes active.

0b1 : Active

The delay bypass is active. The dead-time counter DTC0 is not used by the sampling of the Hall pattern.

End of enumeration elements list.


IEN

Capture/Compare Interrupt Enable Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENCC60R ENCC60F ENCC61R ENCC61F ENCC62R ENCC62F ENT12OM ENT12PM ENT13CM ENT13PM ENTRPF ENCHE ENWHE ENIDLE ENSTR

ENCC60R : Capture, Compare-Match Rising Edge Interrupt Enable for Channel 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit CC60R in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit CC60R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC60.

End of enumeration elements list.

ENCC60F : Capture, Compare-Match Falling Edge Interrupt Enable for Channel 0
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit CC60F in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit CC60F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC60.

End of enumeration elements list.

ENCC61R : Capture, Compare-Match Rising Edge Interrupt Enable for Channel 1
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit CC61R in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit CC61R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC61.

End of enumeration elements list.

ENCC61F : Capture, Compare-Match Falling Edge Interrupt Enable for Channel 1
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit CC61F in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit CC61F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC61.

End of enumeration elements list.

ENCC62R : Capture, Compare-Match Rising Edge Interrupt Enable for Channel 2
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit CC62R in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit CC62R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC62.

End of enumeration elements list.

ENCC62F : Capture, Compare-Match Falling Edge Interrupt Enable for Channel 2
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit CC62F in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit CC62F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC62.

End of enumeration elements list.

ENT12OM : Enable Interrupt for T12 One-Match
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit T12OM in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit T12OM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT12.

End of enumeration elements list.

ENT12PM : Enable Interrupt for T12 Period-Match
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit T12PM in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit T12PM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT12.

End of enumeration elements list.

ENT13CM : Enable Interrupt for T13 Compare-Match
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit T13CM in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit T13CM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT13.

End of enumeration elements list.

ENT13PM : Enable Interrupt for T13 Period-Match
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit T13PM in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit T13PM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT13.

End of enumeration elements list.

ENTRPF : Enable Interrupt for Trap Flag
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit TRPF in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit TRPF in register IS occurs. The interrupt line that will be activated is selected by bit field INPERR.

End of enumeration elements list.

ENCHE : Enable Interrupt for Correct Hall Event
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit CHE in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit CHE in register IS occurs. The interrupt line that will be activated is selected by bit field INPCHE.

End of enumeration elements list.

ENWHE : Enable Interrupt for Wrong Hall Event
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit WHE in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit WHE in register IS occurs. The interrupt line that will be activated is selected by bit field INPERR.

End of enumeration elements list.

ENIDLE : Enable Idle
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : IDLE not set

The bit IDLE is not automatically set when a wrong hall event is detected.

0b1 : IDLE set

The bit IDLE is automatically set when a wrong hall event is detected.

End of enumeration elements list.

ENSTR : Enable Multi-Channel Mode Shadow Transfer Interrupt
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0b0 : No interrupt

No interrupt will be generated if the set condition for bit STR in register IS occurs.

0b1 : Interrupt

An interrupt will be generated if the set condition for bit STR in register IS occurs. The interrupt line that will be activated is selected by bit field INPCHE.

End of enumeration elements list.


INP

Capture/Compare Interrupt Node Pointer Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INP INP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INPCC60 INPCC61 INPCC62 INPCHE INPERR INPT12 INPT13

INPCC60 : Interrupt Node Pointer for Channel 0 Interrupts
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0b00 : SR0

Interrupt output line SR0 is selected.

0b01 : SR1

Interrupt output line SR1 is selected.

0b10 : SR2

Interrupt output line SR2 is selected.

0b11 : SR3

Interrupt output line SR3 is selected.

End of enumeration elements list.

INPCC61 : Interrupt Node Pointer for Channel 1 Interrupts
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0b00 : SR0

Interrupt output line SR0 is selected.

0b01 : SR1

Interrupt output line SR1 is selected.

0b10 : SR2

Interrupt output line SR2 is selected.

0b11 : SR3

Interrupt output line SR3 is selected.

End of enumeration elements list.

INPCC62 : Interrupt Node Pointer for Channel 2 Interrupts
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0b00 : SR0

Interrupt output line SR0 is selected.

0b01 : SR1

Interrupt output line SR1 is selected.

0b10 : SR2

Interrupt output line SR2 is selected.

0b11 : SR3

Interrupt output line SR3 is selected.

End of enumeration elements list.

INPCHE : Interrupt Node Pointer for the CHE Interrupt
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0b00 : SR0

Interrupt output line SR0 is selected.

0b01 : SR1

Interrupt output line SR1 is selected.

0b10 : SR2

Interrupt output line SR2 is selected.

0b11 : SR3

Interrupt output line SR3 is selected.

End of enumeration elements list.

INPERR : Interrupt Node Pointer for Error Interrupts
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0b00 : SR0

Interrupt output line SR0 is selected.

0b01 : SR1

Interrupt output line SR1 is selected.

0b10 : SR2

Interrupt output line SR2 is selected.

0b11 : SR3

Interrupt output line SR3 is selected.

End of enumeration elements list.

INPT12 : Interrupt Node Pointer for Timer T12 Interrupts
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0b00 : SR0

Interrupt output line SR0 is selected.

0b01 : SR1

Interrupt output line SR1 is selected.

0b10 : SR2

Interrupt output line SR2 is selected.

0b11 : SR3

Interrupt output line SR3 is selected.

End of enumeration elements list.

INPT13 : Interrupt Node Pointer for Timer T13 Interrupts
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0b00 : SR0

Interrupt output line SR0 is selected.

0b01 : SR1

Interrupt output line SR1 is selected.

0b10 : SR2

Interrupt output line SR2 is selected.

0b11 : SR3

Interrupt output line SR3 is selected.

End of enumeration elements list.


ISS

Capture/Compare Interrupt Status Set Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISS ISS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCC60R SCC60F SCC61R SCC61F SCC62R SCC62F ST12OM ST12PM ST13CM ST13PM STRPF SWHC SCHE SWHE SIDLE SSTR

SCC60R : Set Capture, Compare-Match Rising Edge Flag
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit CC60R in register IS will be set.

End of enumeration elements list.

SCC60F : Set Capture, Compare-Match Falling Edge Flag
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit CC60F in register IS will be set.

End of enumeration elements list.

SCC61R : Set Capture, Compare-Match Rising Edge Flag
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit CC61R in register IS will be set.

End of enumeration elements list.

SCC61F : Set Capture, Compare-Match Falling Edge Flag
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit CC61F in register IS will be set.

End of enumeration elements list.

SCC62R : Set Capture, Compare-Match Rising Edge Flag
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit CC62R in register IS will be set.

End of enumeration elements list.

SCC62F : Set Capture, Compare-Match Falling Edge Flag
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit CC62F in register IS will be set.

End of enumeration elements list.

ST12OM : Set Timer T12 One-Match Flag
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit T12OM in register IS will be set.

End of enumeration elements list.

ST12PM : Set Timer T12 Period-Match Flag
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit T12PM in register IS will be set.

End of enumeration elements list.

ST13CM : Set Timer T13 Compare-Match Flag
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit T13CM in register IS will be set.

End of enumeration elements list.

ST13PM : Set Timer T13 Period-Match Flag
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit T13PM in register IS will be set.

End of enumeration elements list.

STRPF : Set Trap Flag
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bits TRPF and TRPS in register IS will be set.

End of enumeration elements list.

SWHC : Software Hall Compare
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

The Hall compare action is triggered.

End of enumeration elements list.

SCHE : Set Correct Hall Event Flag
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit CHE in register IS will be set.

End of enumeration elements list.

SWHE : Set Wrong Hall Event Flag
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit WHE in register IS will be set.

End of enumeration elements list.

SIDLE : Set IDLE Flag
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit IDLE in register IS will be set.

End of enumeration elements list.

SSTR : Set STR Flag
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Set

Bit STR in register IS will be set.

End of enumeration elements list.


PSLR

Passive State Level Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSLR PSLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSL PSL63

PSL : Compare Outputs Passive State Level
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0b0 : Level 0

The passive level is 0.

0b1 : Level 1

The passive level is 1.

End of enumeration elements list.

PSL63 : Passive State Level of Output COUT63
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : Level 0

The passive level is 0.

0b1 : Level 1

The passive level is 1.

End of enumeration elements list.


MCMCTR

Multi-Channel Mode Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCMCTR MCMCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWSEL SWSYN STE12U STE12D STE13U

SWSEL : Switching Selection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0b000 : No request

no trigger request will be generated

0b001 : Correct pattern

correct hall pattern on CCPOSx detected

0b010 : T13 period-match

T13 period-match detected (while counting up)

0b011 : T12 one-match

T12 one-match (while counting down)

0b100 : T12 channel1 compare-match

T12 channel 1 compare-match detected (phase delay function)

0b101 : T12 period-match

T12 period match detected (while counting up) else reserved, no trigger request will be generated

End of enumeration elements list.

SWSYN : Switching Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0b00 : Direct

the trigger event directly causes the shadow transfer

0b01 : T13 zero-match

T13 zero-match triggers the shadow transfer

0b10 : T12 zero-match

a T12 zero-match (while counting up) triggers the shadow transfer

End of enumeration elements list.

STE12U : Shadow Transfer Enable for T12 Upcounting
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : No action

None

0b1 : Enabled

The T12_ST shadow transfer mechanism is enabled if MCMEN = 1.

End of enumeration elements list.

STE12D : Shadow Transfer Enable for T12 Downcounting
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : No action

None

0b1 : Enabled

The T12_ST shadow transfer mechanism is enabled if MCMEN = 1.

End of enumeration elements list.

STE13U : Shadow Transfer Enable for T13 Upcounting
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

0b0 : No action

None

0b1 : Enabled

The T13_ST shadow transfer mechanism is enabled if MCMEN = 1.

End of enumeration elements list.


TCTR2

Timer Control Register 2
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCTR2 TCTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T12SSC T13SSC T13TEC T13TED T12RSEL T13RSEL

T12SSC : Timer T12 Single Shot Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

The single-shot mode is disabled, no hardware action on T12R.

0b1 : Enabled

The single shot mode is enabled, the bit T12R is reset by hardware if: - T12 reaches its period value in edge-aligned mode - T12 reaches the value 1 while down counting in center-aligned mode. In parallel to the reset action of bit T12R, the bits CC6xST (x = 0, 1, 2) are reset.

End of enumeration elements list.

T13SSC : Timer T13 Single Shot Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : No action

No hardware action on T13R

0b1 : Enabled

The single-shot mode is enabled, the bit T13R is reset by hardware if T13 reaches its period value. In parallel to the reset action of bit T13R, the bit CC63ST is reset.

End of enumeration elements list.

T13TEC : T13 Trigger Event Control
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0b000 : No action

None

0b001 : Channel 0

set T13R on a T12 compare event on channel 0

0b010 : Channel 1

set T13R on a T12 compare event on channel 1

0b011 : Channel 2

set T13R on a T12 compare event on channel 2

0b100 : Channel 0,1,2

set T13R on any T12 compare event on the channels 0, 1, or 2

0b101 : Period-match

set T13R upon a period-match of T12

0b110 : Zero-match

set T13R upon a zero-match of T12 (while counting up)

0b111 : CCPOSx

set T13R on any edge of inputs CCPOSx

End of enumeration elements list.

T13TED : Timer T13 Trigger Event Direction
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0b00 : No action

None

0b01 : Up

while T12 is counting up

0b10 : Down

while T12 is counting down

0b11 : Independent

independent on the count direction of T12

End of enumeration elements list.

T12RSEL : Timer T12 External Run Selection
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0b00 : Disabled

The external setting of T12R is disabled.

0b01 : Rising edge

Bit T12R is set if a rising edge of signal T12HR is detected.

0b10 : Falling edge

Bit T12R is set if a falling edge of signal T12HR is detected.

0b11 : Edge

Bit T12R is set if an edge of signal T12HR is detected.

End of enumeration elements list.

T13RSEL : Timer T13 External Run Selection
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0b00 : Disabled

The external setting of T13R is disabled.

0b01 : Rising edge

Bit T13R is set if a rising edge of signal T13HR is detected.

0b10 : Falling edge

Bit T13R is set if a falling edge of signal T13HR is detected.

0b11 : Edge

Bit T13R is set if an edge of signal T13HR is detected.

End of enumeration elements list.


MODCTR

Modulation Control Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODCTR MODCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T12MODEN MCMEN T13MODEN ECT13O

T12MODEN : T12 Modulation Enable
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0b0 : Disabled

The modulation of the corresponding output signal by a T12 PWM pattern is disabled.

0b1 : Enabled

The modulation of the corresponding output signal by a T12 PWM pattern is enabled.

End of enumeration elements list.

MCMEN : Multi-Channel Mode Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMOUT is disabled.

0b1 : Enabled

The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMOUT is enabled.

End of enumeration elements list.

T13MODEN : T13 Modulation Enable
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0b0 : Disabled

The modulation of the corresponding output signal by a T13 PWM pattern is disabled.

0b1 : Enabled

The modulation of the corresponding output signal by a T13 PWM pattern is enabled.

End of enumeration elements list.

ECT13O : Enable Compare Timer T13 Output
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

The alternate output function COUT63 is disabled.

0b1 : Enabled

The alternate output function COUT63 is enabled for the PWM signal generated by T13.

End of enumeration elements list.


TRPCTR

Trap Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRPCTR TRPCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRPM10 TRPM2 TRPEN TRPEN13 TRPPEN

TRPM10 : Trap Mode Control Bits 1, 0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0b00 : T12 zero-match

The trap state is left (return to normal operation according to TRPM2) when a zero-match of T12 (while counting up) is detected (synchronization to T12).

0b01 : T13 zero-match

The trap state is left (return to normal operation according to TRPM2) when a zero-match of T13 is detected (synchronization to T13).

0b11 : Immediately

The trap state is left (return to normal operation according to TRPM2) immediately without any synchronization to T12 or T13.

End of enumeration elements list.

TRPM2 : Trap Mode Control Bit 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : Hardware reset

The trap state can be left (return to normal operation = bit TRPS = 0) as soon as the input CTRAP becomes inactive. Bit TRPF is automatically cleared by hardware if the input pin CTRAP becomes 1. Bit TRPS is automatically cleared by hardware if bit TRPF is 0 and if the synchronization condition (according to TRPM10) is detected.

0b1 : Software reset

The trap state can be left (return to normal operation = bit TRPS = 0) as soon as bit TRPF is reset by software after the input CTRAP becomes inactive (TRPF is not cleared by hardware). Bit TRPS is automatically cleared by hardware if bit TRPF = 0 and if the synchronization condition (according to TRPM10) is detected.

End of enumeration elements list.

TRPEN : Trap Enable Control
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0b0 : Disabled

The trap functionality of the corresponding output signal is disabled. The output state is independent from bit TRPS.

0b1 : Enabled

The trap functionality of the corresponding output signal is enabled. The output is set to the passive state while TRPS = 1.

End of enumeration elements list.

TRPEN13 : Trap Enable Control for Timer T13
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

The trap functionality for T13 is disabled. Timer T13 (if selected and enabled) provides PWM functionality even while TRPS = 1.

0b1 : Enabled

The trap functionality for T13 is enabled. The timer T13 PWM output signal is set to the passive state while TRPS = 1.

End of enumeration elements list.

TRPPEN : Trap Pin Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

The trap functionality based on the input pin CTRAP is disabled. A trap can only be generated by software by setting bit TRPF.

0b1 : Enabled

The trap functionality based on the input pin CTRAP is enabled. A trap can be generated by software by setting bit TRPF or by CTRAP = 0.

End of enumeration elements list.


MCMOUT

Multi-Channel Mode Output Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCMOUT MCMOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCMP R EXPH CURH

MCMP : Multi-Channel PWM Pattern
bits : 0 - 4 (5 bit)
access : read-only

Enumeration:

0b0 : Passive

The output is set to the passive state. The PWM generated by T12 or T13 is not taken into account.

0b1 : PWM

The output can deliver the PWM generated by T12 or T13 (according to register MODCTR).

End of enumeration elements list.

R : Reminder Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

0b0 : No shadow transfer

Currently, no shadow transfer from MCMPS to MCMP is requested.

0b1 : Shadow transfer

A shadow transfer from MCMPS to MCMP has been requested by the selected trigger source, but it has not yet been executed, because the selected synchronization condition has not yet occurred.

End of enumeration elements list.

EXPH : Expected Hall Pattern
bits : 8 - 9 (2 bit)
access : read-only

CURH : Current Hall Pattern
bits : 11 - 12 (2 bit)
access : read-only


IS

Capture/Compare Interrupt Status Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IS IS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICC60R ICC60F ICC61R ICC61F ICC62R ICC62F T12OM T12PM T13CM T13PM TRPF TRPS CHE WHE IDLE STR

ICC60R : Capture, Compare-Match Rising Edge Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : Not occurred

The event has not yet occurred since this bit has been reset for the last time.

0b1 : Detected

The event described above has been detected.

End of enumeration elements list.

ICC60F : Capture, Compare-Match Falling Edge Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0b0 : Not occurred

The event has not yet occurred since this bit has been reset for the last time.

0b1 : Detected

The event described above has been detected.

End of enumeration elements list.

ICC61R : Capture, Compare-Match Rising Edge Flag
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

0b0 : Not occurred

The event has not yet occurred since this bit has been reset for the last time.

0b1 : Detected

The event described above has been detected.

End of enumeration elements list.

ICC61F : Capture, Compare-Match Falling Edge Flag
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

0b0 : Not occurred

The event has not yet occurred since this bit has been reset for the last time.

0b1 : Detected

The event described above has been detected.

End of enumeration elements list.

ICC62R : Capture, Compare-Match Rising Edge Flag
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

0b0 : Not occurred

The event has not yet occurred since this bit has been reset for the last time.

0b1 : Detected

The event described above has been detected.

End of enumeration elements list.

ICC62F : Capture, Compare-Match Falling Edge Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

0b0 : Not occurred

The event has not yet occurred since this bit has been reset for the last time.

0b1 : Detected

The event described above has been detected.

End of enumeration elements list.

T12OM : Timer T12 One-Match Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

0b0 : Not detected

A timer T12 one-match (while counting down) has not yet been detected since this bit has been reset for the last time.

0b1 : Detected

A timer T12 one-match (while counting down) has been detected.

End of enumeration elements list.

T12PM : Timer T12 Period-Match Flag
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

0b0 : Not detected

A timer T12 period-match (while counting up) has not yet been detected since this bit has been reset for the last time.

0b1 : Detected

A timer T12 period-match (while counting up) has been detected.

End of enumeration elements list.

T13CM : Timer T13 Compare-Match Flag
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

0b0 : Not detected

A timer T13 compare-match has not yet been detected since this bit has been reset for the last time.

0b1 : Detected

A timer T13 compare-match has been detected.

End of enumeration elements list.

T13PM : Timer T13 Period-Match Flag
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

0b0 : Not detected

A timer T13 period-match has not yet been detected since this bit has been reset for the last time.

0b1 : Detected

A timer T13 period-match has been detected.

End of enumeration elements list.

TRPF : Trap Flag
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

0b0 : Not detected

The trap condition has not been detected.

0b1 : Detected

The trap condition has been detected (input CTRAP has been 0 or by software).

End of enumeration elements list.

TRPS : Trap State
bits : 11 - 10 (0 bit)
access : read-only

Enumeration:

0b0 : Not active

The trap state is not active.

0b1 : Active

The trap state is active. Bit TRPS is set while bit TRPF = 1. It is reset according to the mode selected in register TRPCTR.

End of enumeration elements list.

CHE : Correct Hall Event
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

0b0 : Not detected

A transition to a correct (= expected) hall event has not yet been detected since this bit has been reset for the last time.

0b1 : Detected

A transition to a correct (= expected) hall event has been detected.

End of enumeration elements list.

WHE : Wrong Hall Event
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

0b0 : Not detected

A transition to a wrong hall event (not the expected one) has not yet been detected since this bit has been reset for the last time.

0b1 : Detected

A transition to a wrong hall event (not the expected one) has been detected.

End of enumeration elements list.

IDLE : IDLE State
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

0b0 : No action

None

0b1 : Idle

Bit field MCMP is cleared and held to 0, the selected outputs are set to passive state.

End of enumeration elements list.

STR : Multi-Channel Mode Shadow Transfer Request
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

0b0 : No

The shadow transfer has not yet taken place.

0b1 : Yes

The shadow transfer has taken place.

End of enumeration elements list.


PISEL0

Port Input Select Register 0
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PISEL0 PISEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISCC60 ISCC61 ISCC62 ISTRP ISPOS0 ISPOS1 ISPOS2 IST12HR

ISCC60 : Input Select for CC60
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0b00 : CC60_0

The input pin for CC60_0.

0b01 : CC60_1

The input pin for CC60_1.

End of enumeration elements list.

ISCC61 : Input Select for CC61
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0b00 : CC61_0

The input pin for CC61_0.

0b01 : CC61_1

The input pin for CC61_1.

End of enumeration elements list.

ISCC62 : Input Select for CC62
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0b00 : CC62_0

The input pin for CC62_0.

0b01 : CC62_1

The input pin for CC62_1.

End of enumeration elements list.

ISTRP : Input Select for CTRAP
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0b00 : CTRAP_0

The input pin for CTRAP_0.

0b01 : CTRAP_1

The input pin for CTRAP_1.

0b10 : CTRAP_2

The input pin for CTRAP_2.

0b11 : DU1_UP_STS

The output DU1_UP_STS of the Differential Measurement Unit is selected.

End of enumeration elements list.

ISPOS0 : Input Select for CCPOS0
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0b00 : CCPOS0_0

The input pin for CCPOS0_0.

0b01 : CCPOS0_1

The input pin for CCPOS0_1.

0b10 : CCPOS0_2

The input pin for CCPOS0_2.

End of enumeration elements list.

ISPOS1 : Input Select for CCPOS1
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0b00 : CCPOS1_0

The input pin for CCPOS1_0.

0b01 : CCPOS1_1

The input pin for CCPOS1_1.

0b10 : CCPOS1_2

The input pin for CCPOS1_2.

End of enumeration elements list.

ISPOS2 : Input Select for CCPOS2
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0b00 : CCPOS2_0

The input pin for CCPOS2_0.

0b01 : CCPOS2_1

The input pin for CCPOS2_1.

0b10 : CCPOS2_2

The input pin for CCPOS2_2.

End of enumeration elements list.

IST12HR : Input Select for T12HR
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0b00 : T12HRA

Either signal T12HRA (if T12EXT = 0) or T12HRE (if T12EXT = 1) is selected.

0b01 : T12HRB

Either signal T12HRB (if T12EXT = 0) or T12HRF (if T12EXT = 1) is selected.

0b10 : T12HRC

Either signal T12HRC (if T12EXT = 0) or T12HRG (if T12EXT = 1) is selected.

0b11 : T12HRD

Either signal T12HRD (if T12EXT = 0) or T12HRH (if T12EXT = 1) is selected.

End of enumeration elements list.


PISEL2

Port Input Select Register 2
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PISEL2 PISEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IST13HR ISCNT12 ISCNT13 T12EXT T13EXT

IST13HR : Input Select for T13HR
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0b00 : T13HRA

Either signal T13HRA (if T13EXT = 0) or T13HRE (if T13EXT = 1) is selected.

0b01 : T13HRB

Either signal T13HRB (if T13EXT = 0) or T13HRF (if T13EXT = 1) is selected.

0b10 : T13HRC

Either signal T13HRC (if T13EXT = 0) or T13HRG (if T13EXT = 1) is selected.

0b11 : T13HRD

Either signal T13HRD (if T13EXT = 0) or T13HRH (if T13EXT = 1) is selected.

End of enumeration elements list.

ISCNT12 : Input Select for T12 Counting Input
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0b00 : T12 prescaler

The T12 prescaler generates the counting events. Bit TCTR4.T12CNT is not taken into account.

0b01 : TCTR4.T12CNT

Bit TCTR4.T12CNT written with 1 is a counting event. The T12 prescaler is not taken into account.

0b10 : Rising edge

The timer T12 is counting each rising edge detected in the selected T12HR signal.

0b11 : Falling edge

The timer T12 is counting each falling edge detected in the selected T12HR signal.

End of enumeration elements list.

ISCNT13 : Input Select for T13 Counting Input
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0b00 : T13 prescaler

The T13 prescaler generates the counting events. Bit TCTR4.T13CNT is not taken into account.

0b01 : TCTR4.T13CNT

Bit TCTR4.T13CNT written with 1 is a counting event. The T13 prescaler is not taken into account.

0b10 : Rising edge

The timer T13 is counting each rising edge detected in the selected T13HR signal.

0b11 : Falling Edge

The timer T13 is counting each falling edge detected in the selected T13HR signal.

End of enumeration elements list.

T12EXT : Extension for T12HR Inputs
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : T12HR_D_A

One of the signals T12HR[D:A] is selected.

0b1 : T12HR_H_E

One of the signals T12HR[H:E] is selected.

End of enumeration elements list.

T13EXT : Extension for T13HR Inputs
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : T13HR_D_A

One of the signals T13HR[D:A] is selected.

0b1 : T13HR_H_E

One of the signals T13HR[H:E] is selected.

End of enumeration elements list.


T12

Timer T12 Counter Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T12 T12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T12CV

T12CV : Timer T12 Counter Value
bits : 0 - 14 (15 bit)
access : read-write


T13

Timer T13 Counter Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T13 T13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T13CV

T13CV : Timer T13 Counter Value
bits : 0 - 14 (15 bit)
access : read-write


MCMOUTS

Multi-Channel Mode Output Shadow Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCMOUTS MCMOUTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCMPS STRMCM EXPHS CURHS STRHP

MCMPS : Multi-Channel PWM Pattern Shadow
bits : 0 - 4 (5 bit)
access : read-write

STRMCM : Shadow Transfer Request for MCMPS
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

0b0 : by Hardware

Bit field MCMP is updated according to the defined hardware action. The write access to bit field MCMPS does not modify bit field MCMP.

0b1 : by Software

Bit field MCMP is updated by the value written to bit field MCMPS.

End of enumeration elements list.

EXPHS : Expected Hall Pattern Shadow
bits : 8 - 9 (2 bit)
access : read-write

CURHS : Current Hall Pattern Shadow
bits : 11 - 12 (2 bit)
access : read-write

STRHP : Shadow Transfer Request for the Hall Pattern
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

0b0 : by Hardware

The bit fields CURH and EXPH are updated according to the defined hardware action. The write access to bit fields CURHS and EXPHS does not modify the bit fields CURH and EXPH.

0b1 : by Software

The bit fields CURH and EXPH are updated by the value written to the bit fields CURHS and EXPHS.

End of enumeration elements list.


CMPSTAT

Compare State Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPSTAT CMPSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC60ST CC61ST CC62ST CCPOS0 CCPOS1 CCPOS2 CC63ST CC60PS COUT60PS CC61PS COUT61PS CC62PS COUT62PS COUT63PS T13IM

CC60ST : Capture/Compare State Bits
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : Less

In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time.

0b1 : Greater

In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected.

End of enumeration elements list.

CC61ST : Capture/Compare State Bits
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0b0 : Less

In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time.

0b1 : Greater

In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected.

End of enumeration elements list.

CC62ST : Capture/Compare State Bits
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

0b0 : Less

In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time.

0b1 : Greater

In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected.

End of enumeration elements list.

CCPOS0 : Sampled Hall Pattern Bit 0
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

0b0 : Zero

The input CCPOS0 has been sampled as 0.

0b1 : One

The input CCPOS0 has been sampled as 1.

End of enumeration elements list.

CCPOS1 : Sampled Hall Pattern Bit 1
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

0b0 : Zero

The input CCPOS1 has been sampled as 0.

0b1 : One

The input CCPOS1 has been sampled as 1.

End of enumeration elements list.

CCPOS2 : Sampled Hall Pattern Bit 2
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

0b0 : Zero

The input CCPOS2 has been sampled as 0.

0b1 : One

The input CCPOS2 has been sampled as 1.

End of enumeration elements list.

CC63ST : Capture/Compare State Bits
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

0b0 : Less

In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time.

0b1 : Greater

In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected.

End of enumeration elements list.

CC60PS : Passive State Select for Compare Outputs
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : Zero

The corresponding compare output drives passive level while CC6xST is 0.

0b1 : One

The corresponding compare output drives passive level while CC6xST is 1.

End of enumeration elements list.

COUT60PS : Passive State Select for Compare Outputs
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : Zero

The corresponding compare output drives passive level while CC6xST is 0.

0b1 : One

The corresponding compare output drives passive level while CC6xST is 1.

End of enumeration elements list.

CC61PS : Passive State Select for Compare Outputs
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

0b0 : Zero

The corresponding compare output drives passive level while CC6xST is 0.

0b1 : One

The corresponding compare output drives passive level while CC6xST is 1.

End of enumeration elements list.

COUT61PS : Passive State Select for Compare Outputs
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

0b0 : Zero

The corresponding compare output drives passive level while CC6xST is 0.

0b1 : One

The corresponding compare output drives passive level while CC6xST is 1.

End of enumeration elements list.

CC62PS : Passive State Select for Compare Outputs
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

0b0 : Zero

The corresponding compare output drives passive level while CC6xST is 0.

0b1 : One

The corresponding compare output drives passive level while CC6xST is 1.

End of enumeration elements list.

COUT62PS : Passive State Select for Compare Outputs
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

0b0 : Zero

The corresponding compare output drives passive level while CC6xST is 0.

0b1 : One

The corresponding compare output drives passive level while CC6xST is 1.

End of enumeration elements list.

COUT63PS : Passive State Select for Compare Outputs
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : Zero

The corresponding compare output drives passive level while CC6xST is 0.

0b1 : One

The corresponding compare output drives passive level while CC6xST is 1.

End of enumeration elements list.

T13IM : T13 Inverted Modulation
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0b0 : Not inverted

T13 output is not inverted.

0b1 : Inverted

T13 output is inverted for further modulation.

End of enumeration elements list.


ISR

Capture/Compare Interrupt Status Reset Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCC60R RCC60F RCC61R RCC61F RCC62R RCC62F RT12OM RT12PM RT13CM RT13PM RTRPF RCHE RWHE RIDLE RSTR

RCC60R : Reset Capture, Compare-Match Rising Edge Flag
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit CC60R in register IS will be reset.

End of enumeration elements list.

RCC60F : Reset Capture, Compare-Match Falling Edge Flag
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit CC60F in register IS will be reset.

End of enumeration elements list.

RCC61R : Reset Capture, Compare-Match Rising Edge Flag
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit CC61R in register IS will be reset.

End of enumeration elements list.

RCC61F : Reset Capture, Compare-Match Falling Edge Flag
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit CC61F in register IS will be reset.

End of enumeration elements list.

RCC62R : Reset Capture, Compare-Match Rising Edge Flag
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit CC62R in register IS will be reset.

End of enumeration elements list.

RCC62F : Reset Capture, Compare-Match Falling Edge Flag
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit CC62F in register IS will be reset.

End of enumeration elements list.

RT12OM : Reset Timer T12 One-Match Flag
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit T12OM in register IS will be reset.

End of enumeration elements list.

RT12PM : Reset Timer T12 Period-Match Flag
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit T12PM in register IS will be reset.

End of enumeration elements list.

RT13CM : Reset Timer T13 Compare-Match Flag
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit T13CM in register IS will be reset.

End of enumeration elements list.

RT13PM : Reset Timer T13 Period-Match Flag
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit T13PM in register IS will be reset.

End of enumeration elements list.

RTRPF : Reset Trap Flag
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit TRPF in register IS will be reset (not taken into account while input CTRAP = 0 and TRPPEN = 1.

End of enumeration elements list.

RCHE : Reset Correct Hall Event Flag
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit CHE in register IS will be reset.

End of enumeration elements list.

RWHE : Reset Wrong Hall Event Flag
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit WHE in register IS will be reset.

End of enumeration elements list.

RIDLE : Reset IDLE Flag
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit IDLE in register IS will be reset.

End of enumeration elements list.

RSTR : Reset STR Flag
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

0b0 : No action

None

0b1 : Reset

Bit STR in register IS will be reset.

End of enumeration elements list.



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