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GPT12E

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ID

T4CON

T5CON

T6CON

CAPREL

T2

T3

T4

T5

T6

PISEL

T2CON

T3CON


ID

Module Identification Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ID ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOD_REV MOD_TYPE

MOD_REV : Module Revision Number
bits : 0 - 6 (7 bit)
access : read-only

MOD_TYPE : Module Identification Number
bits : 8 - 14 (7 bit)
access : read-only


T4CON

Timer T4 Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T4CON T4CON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T4I T4M T4R T4UD T4UDE T4RC CLRT2EN CLRT3EN T4IRDIS T4EDGE T4CHDIR T4RDIR

T4I : Timer T4 Input Parameter Selection
bits : 0 - 1 (2 bit)
access : read-write

T4M : Timer T4 Mode Control (Basic Operating Mode)
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0b000 : value1

Timer Mode

0b001 : value2

Counter Mode

0b010 : value3

Gated Timer Mode with gate active low

0b011 : value4

Gated Timer Mode with gate active high

0b100 : value5

Reload Mode

0b101 : value6

Capture Mode

0b110 : value7

Incremental Interface Mode (Rotation Detection Mode)

0b111 : value8

Incremental Interface Mode (Edge Detection Mode)

End of enumeration elements list.

T4R : Timer T4 Input Run Bit
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : Stop

Timer T4 stops

0b1 : Run

Timer T4 runs

End of enumeration elements list.

T4UD : Timer T2 Up/Down Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : Up

Timer T2 counts up

0b1 : Down

Timer T2 counts down

End of enumeration elements list.

T4UDE : Timer T4 External Up/Down Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : T4UD

Count direction is controlled by bit T4UD input T4EUD is disconnected

0b1 : T4EUD

Count direction is controlled by input T4EUD

End of enumeration elements list.

T4RC : Timer T4 Remote Control
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : T4R

Timer T4 is controlled by its own run bit T4R

0b1 : T3R

Timer T4 is controlled by the run bit T3R of core timer T3, but not by bit T4R

End of enumeration elements list.

CLRT2EN : Clear Timer T2 Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

0b0 : No effect

No effect of T4EUD on timer T2

0b1 : Clear

A falling edge on T4EUD clears timer T2

End of enumeration elements list.

CLRT3EN : Clear Timer T3 Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

0b0 : No effect

No effect of T4IN on Timer T3

0b1 : Clear

A falling edge on T4In clears timer T3

End of enumeration elements list.

T4IRDIS : Timer T4 Interrupt Disable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

0b0 : Enabled

Interrupt generation for T4CHDIR and T4EDGE interrupts in Incremental Interface Mode is enabled

0b1 : Disabled

Interrupt generation for T4CHDIR and T4EDGE interrupts in Incremental Interface Mode is disabled

End of enumeration elements list.

T4EDGE : Timer T4 Edge Direction
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

0b0 : No count

No count edge was detected

0b1 : Count

A count edge was detected

End of enumeration elements list.

T4CHDIR : Timer T4 Count Direction Change
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : No change

No change in count direction was detected

0b1 : Change

A change in count direction was detected

End of enumeration elements list.

T4RDIR : Timer T4 Rotation Direction
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

0b0 : Up

Timer T4 counts up

0b1 : Down

Timer T4 counts down

End of enumeration elements list.


T5CON

Timer T5 Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T5CON T5CON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T5I T5M T5R T5UD T5UDE T5RC CT3 CI T5CLR T5SC

T5I : Timer T5 Input Parameter Selection
bits : 0 - 1 (2 bit)
access : read-write

T5M : Timer T5 Input Mode Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0b00 : value1

Timer Mode

0b01 : value2

Counter Mode

0b10 : value3

Gated Timer Mode with gate active low

0b11 : value4

Gated Timer Mode with gate active high

End of enumeration elements list.

T5R : Timer T5 Run Bit
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : Stop

Timer T5 stops

0b1 : Run

Timer T5 runs

End of enumeration elements list.

T5UD : Timer T2 Up/Down Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : Up

Timer T5 counts up

0b1 : Down

Timer T5 counts down

End of enumeration elements list.

T5UDE : Timer T5 External Up/Down Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : T5UD

Count direction is controlled by bit T5UD input T5EUD is disconnected

0b1 : T5EUD

Count direction is controlled by input T5EUD

End of enumeration elements list.

T5RC : Timer T5 Remote Control
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : T5R

Timer T5 is controlled by its own run bit T5R

0b1 : T6R

Timer T5 is controlled by the run bit T6R of core timer T6, not by bit T5R

End of enumeration elements list.

CT3 : Timer T3 Capture Trigger Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

0b0 : CAPIN

Capture trigger from input line CAPIN

0b1 : T3IN

Capture trigger from T3 input lines T3IN and/or T3EUD

End of enumeration elements list.

CI : Register CAPREL Capture Trigger Selection
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0b00 : Disabled

Capture disabled

0b01 : Positive

Positive transition (rising edge) on CAPIN or any transition on T3IN

0b10 : Negative

Negative transition (falling edge) on CAPIN or any transition on T3EUD

0b11 : Any

Any transition (rising or falling edge) on CAPIN or any transition on T3IN or T3EUD

End of enumeration elements list.

T5CLR : Timer T5 Clear Enable Bit
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : Not cleared

Timer T5 is not cleared on a capture event

0b1 : Cleared

Timer T5 is cleared on a capture event

End of enumeration elements list.

T5SC : Timer T5 Capture Mode Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

Capture into register CAPREL disabled

0b1 : Enabled

Capture into register CAPREL enabled

End of enumeration elements list.


T6CON

Timer T6 Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T6CON T6CON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T6I T6M T6R T6UD T6UDE T6OE T6OTL BPS2 T6CLR T6SR

T6I : Timer T6 Input Parameter Selection
bits : 0 - 1 (2 bit)
access : read-write

T6M : Timer T6 Mode Control
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0b000 : value1

Timer Mode

0b001 : value2

Counter Mode

0b010 : value3

Gated Timer Mode with gate active low

0b011 : value4

Gated Timer Mode with gate active high

End of enumeration elements list.

T6R : Timer T6 Input Run Bit
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : Stop

Timer T3 stops

0b1 : Run

Timer T3 runs

End of enumeration elements list.

T6UD : Timer T6 Up/Down Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : Up

Timer T3 counts up

0b1 : Down

Timer T3 counts down

End of enumeration elements list.

T6UDE : Timer T6 External Up/Down Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : T6UD

Count direction is controlled by bit T6UD input T6EUD is disconnected

0b1 : T6EUD

Count direction is controlled by input T6EUD

End of enumeration elements list.

T6OE : Overflow/Underflow Output Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

Alternate Output Function Disabled

0b1 : T6OUT

State of T6 toggle latch is output on pin T6OUT

End of enumeration elements list.

T6OTL : Timer T6 Overflow Toggle Latch
bits : 10 - 9 (0 bit)
access : read-write

BPS2 : GPT2 Block Prescaler Control
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0b00 : 4

fGPT/4

0b01 : 2

fGPT/2

0b10 : 16

fGPT/16

0b11 : 8

fGPT/8

End of enumeration elements list.

T6CLR : Timer T6 Clear Enable Bit
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : Not cleared

Timer T6 is not cleared on a capture event

0b1 : Cleared

Timer T6 is cleared on a capture event

End of enumeration elements list.

T6SR : Timer T6 Reload Mode Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

Reload from register CAPREL disabled

0b1 : Enabled

Reload from register CAPREL enabled

End of enumeration elements list.


CAPREL

Capture/Reload Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPREL CAPREL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPREL

CAPREL : Current reload value or Captured value
bits : 0 - 14 (15 bit)
access : read-write


T2

Timer T2 Count Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T2 T2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T2

T2 : Timer T2 Current Value
bits : 0 - 14 (15 bit)
access : read-write


T3

Timer T3 Count Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T3 T3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T3

T3 : Timer T3 Current Value
bits : 0 - 14 (15 bit)
access : read-write


T4

Timer T4 Count Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T4 T4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T4

T4 : Timer T4 Current Value
bits : 0 - 14 (15 bit)
access : read-write


T5

Timer 5 Count Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T5 T5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T5

T5 : Timer T5 Current Value
bits : 0 - 14 (15 bit)
access : read-write


T6

Timer 6 Count Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T6 T6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T6

T6 : Timer T6 Current Value
bits : 0 - 14 (15 bit)
access : read-write


PISEL

Port Input Select Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PISEL PISEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IST2IN IST2EUD IST3IN IST3EUD IST4IN IST4EUD IST5IN IST5EUD IST6IN IST6EUD ISCAPIN

IST2IN : Input Select for T2IN
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : T2INA

Signal T2INA is selected

0b1 : T2INB

Signal T2INB is selected

End of enumeration elements list.

IST2EUD : Input Select for T2EUD
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : T2EUDA

Signal T2EUDA is selected

0b1 : T2EUDB

Signal T2EUDB is selected

End of enumeration elements list.

IST3IN : Input Select for T3IN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0b00 : T3INA

Signal T3INA is selected

0b01 : T3INB

Signal T3INB is selected

0b10 : T3INC

Signal T3INC is selected

0b11 : T3IND

Signal T3IND is selected

End of enumeration elements list.

IST3EUD : Input Select for T3EUD
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0b00 : T3EUDA

Signal T3EUDA is selected

0b01 : T3EUDB

Signal T3EUDB is selected

0b10 : T3EUDC

Signal T3EUDC is selected

0b11 : T3EUDD

Signal T3EUDD is selected

End of enumeration elements list.

IST4IN : Input Select for T4IN
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0b00 : T4INA

Signal T4INA is selected

0b01 : T4INB

Signal T4INB is selected

0b10 : T4INC

Signal T4INC is selected

0b11 : T4IND

Signal T4IND is selected

End of enumeration elements list.

IST4EUD : Input Select for TEUD
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0b00 : T4EUDA

Signal T4EUDA is selected

0b01 : T4EUDB

Signal T4EUDB is selected

0b10 : T4EUDC

Signal T4EUDC is selected

0b11 : T4EUDD

Signal T4EUDD is selected

End of enumeration elements list.

IST5IN : Input Select for T5IN
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

0b0 : T5INA

Signal T5INA is selected

0b1 : T5INB

Signal T5INB is selected

End of enumeration elements list.

IST5EUD : Input Select for T5EUD
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

0b0 : T5EUDA

Signal T5EUDA is selected

0b1 : T5EUDB

Signal T5EUDB is selected

End of enumeration elements list.

IST6IN : Input Select for T6IN
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

0b0 : T6INA

Signal T6INA is selected

0b1 : T6INB

Signal T6INB is selected

End of enumeration elements list.

IST6EUD : Input Select for T6EUD
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

0b0 : T6EUDA

Signal T6EUDA is selected

0b1 : T6EUDB

Signal T6EUDB is selected

End of enumeration elements list.

ISCAPIN : Input Select for CAPIN
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0b00 : CAPINA

Signal CAPINA is selected

0b01 : CAPINB

Signal CAPINB is selected

0b10 : CAPINC

Signal CAPINC (Read trigger from T3) is selected

0b11 : CAPIND

Signal CAPIND (Read trigger from T2 or T3 or T4) is selected

End of enumeration elements list.


T2CON

Timer T2 Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T2CON T2CON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T2I T2M T2R T2UD T2UDE T2RC T2IRIDIS T2EDGE T2CHDIR T2DIR

T2I : Timer T2 Input Parameter Selection
bits : 0 - 1 (2 bit)
access : read-write

T2M : Timer T2 Input Mode Control
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0b000 : value1

Timer Mode

0b001 : value2

Counter Mode

0b010 : value3

Gated Timer Mode with gate active low

0b011 : value4

Gated Timer Mode with gate active high

0b100 : value5

Reload Mode

0b101 : value6

Capture Mode

0b110 : value7

Incremental Interface Mode (Rotation Detection Mode)

0b111 : value8

Incremental Interface Mode (Edge Detection Mode)

End of enumeration elements list.

T2R : Timer T2 Input Run Bit
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : Stop

Timer T2 stops

0b1 : Run

Timer T2 runs

End of enumeration elements list.

T2UD : Timer T2 Up/Down Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : Up

Timer T2 counts up

0b1 : Down

Timer T2 counts down

End of enumeration elements list.

T2UDE : Timer T2 External Up/Down Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : T2UD

Count direction is controlled by bit T2UD input T2EUD is disconnected

0b1 : T2EUD

Count direction is controlled by input T2EUD

End of enumeration elements list.

T2RC : Timer T2 Remote Control
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : T2R

Timer T2 is controlled by its own run bit T2R

0b1 : T3R

Timer T2 is controlled by the run bit T3R of core timer T3, not by bit T2R

End of enumeration elements list.

T2IRIDIS : Timer T2 Interrupt Disable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

0b0 : Enabled

Interrupt generation for T2CHDIR and T2EDGE interrupts in Incremental Interface Mode is enabled

0b1 : Disabled

Interrupt generation for T2CHDIR and T2EDGE interrupts in Incremental Interface Mode is disabled

End of enumeration elements list.

T2EDGE : Timer T2 Edge Detection
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

0b0 : No count

No count edge was detected

0b1 : Count

A count edge was detected

End of enumeration elements list.

T2CHDIR : Timer T2 Count Direction Change
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : No change

No change of count direction was detected

0b1 : Change

A change of count direction was detected

End of enumeration elements list.

T2DIR : Timer T2 Rotation Direction
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

0b0 : Up

Timer T2 counts up

0b1 : Down

Timer T2 counts down

End of enumeration elements list.


T3CON

Timer T3 Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T3CON T3CON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T3I T3M T3R T3UD T3UDE T3OE T3OTL BPS1 T3EDGE T3CHDIR T3DIR

T3I : Timer T3 Input Parameter Selection
bits : 0 - 1 (2 bit)
access : read-write

T3M : Timer T3 Input Mode Control
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0b000 : value1

Timer Mode

0b001 : value2

Counter Mode

0b010 : value3

Gated Timer Mode with gate active low

0b011 : value4

Gated Timer Mode with gate active high

0b110 : value7

Incremental Interface Mode (Rotation Detection Mode)

0b111 : value8

Incremental Interface Mode (Edge Detection Mode)

End of enumeration elements list.

T3R : Timer T3 Input Run Bit
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : Stop

Timer T3 stops

0b1 : Run

Timer T3 runs

End of enumeration elements list.

T3UD : Timer T3 Up/Down Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : Up

Timer T3 counts up

0b1 : Down

Timer T3 counts down

End of enumeration elements list.

T3UDE : Timer T3 External Up/Down Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : T3UD

Count direction is controlled by bit T3UD input T3EUD is disconnected

0b1 : T3EUD

Count direction is controlled by input T3EUD

End of enumeration elements list.

T3OE : Overflow/Underflow Output Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : Disabled

Alternate Output Function Disabled

0b1 : T3OUT

State of T3 toggle latch is output on pin T3OUT

End of enumeration elements list.

T3OTL : Timer T3 Overflow Toggle Latch
bits : 10 - 9 (0 bit)
access : read-write

BPS1 : GPT1 Block Prescaler Control
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0b00 : 8

fGPT/8

0b01 : 4

fGPT/4

0b10 : 32

fGPT/32

0b11 : 16

fGPT/16

End of enumeration elements list.

T3EDGE : Timer T3 Edge Detection Flag
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

0b0 : No count

No count edge was detected

0b1 : Count

A count edge was detected

End of enumeration elements list.

T3CHDIR : Timer T3 Count Direction Change Flag
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : No change

No change of count direction was detected

0b1 : Change

A change of count direction was detected

End of enumeration elements list.

T3DIR : Timer T3 Rotation Direction Flag
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

0b0 : Up

Timer T3 counts up

0b1 : Down

Timer T3 counts down

End of enumeration elements list.



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